R5109G NISSHINBO | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 20
Technical content
Microprocessor Supervisory Circuit with 2 Clock Input Pin NO.EA-172-200602 OUTLINE The R5109G is a microprocessor supervisory circuit and has high accuracy and ultra low supply current voltage detector with built-in delay circuit and watchdog timer. When the supply voltage is down across the threshold, or the watchdog timer does not detect the system clock from the microprocessor, the reset output is generated. The voltage detector circuit is used for the system reset, etc. The detector threshold is fixed internally, and the accuracy is ±1.0%. The released delay time (Power-on Reset Delay) circuit is built-in, and output delay time is adjustable with an external capacitor, and the accuracy is ± 16%(1). When the supply voltage becomes the released voltage, the reset state will be maintained during the delay time. The output type of the reset is selectable, Nch open-drain, or CMOS. The time out period of the watchdog timer can be also set with an external capacitor, and the accuracy is ±33% (1). The function to stop supervising clock by the watchdog timer (INH function) and the function to supervise two different clocks are built in this IC. There are another 4 products by the difference of packages and the function of voltage detector and watchdog timer. The package of R5109G is SSOP-8G.
FEATURES
< Voltage Detector Part > < Watchdog Timer Part >
APPLICATIONS
- Supervisory circuit for equipment with using microprocessors. (1) Accuracy to center value of (Min.+Max.)/2
NO.EA-172-200602 SELECTION GUIDE The detector threshold, the output type and the taping type for the ICs can be selected at the user s’ request. The selection can be made with designating the part number as shown below; Product Name Package Quantity per Reel Pb Free Halogen Free R5109Gxx1∗-TR-FE SSOP-8G 3,000 pcs Yes Yes xx : The detector threshold (-VDET) can be designated in the range from 1.5V(15) to 5.5V(55) in 0.1V steps. ∗ : Designation of Output Type (A) Nch Open Drain (C) CMOS Series Selection R5105N R5106N R5107G R5108G R5109G Package SOT-23-6 SSOP-8G With INH pin (Inhibit) No Yes 2 clock input No Yes With MR pin (Manual Reset) No Yes No With SENSE pin No Yes No Remarks CD pin and CTW pin are combined uses. Operating Voltage Range 1.5V to 6.0V Supply Current 11.5µA
NO.EA-172-200602 BLOCK DIAGRAMS R5109Gxx1A (Nch Open Drain Output) R5109Gxx1C (CMOS Output) VDD GND SCK1 CTW WATCHDOG TIMER CLOCK DETECTOR RESETB INH CD Vref1 Vref2 SCK2 CLOCK DETECTOR VDD GND SCK1 CTW WATCHDOG TIMER CLOCK DETECTOR RESETB INH CD Vref1 Vref2 SCK2 CLOCK DETECTOR PIN DESCRIPTIONS
- SSOP-8G 1 2 3 4 8 7 6 5 Pin No. Symbol Description 1 RESETB Output Pin for Reset signal of Watchdog timer and Voltage Detector. (Output "L" at detecting Detector Threshold and Watchdog Timer Reset.)
2 INH Inhibit Pin ("L": Inhibit the watchdog timer)
3 CD External Capacitor Pin for Setting Delay Time of Voltage Detector
4 GND Ground Pin
5 SCK1 Clock Input Pin 1 from Microprocessor
6 SCK2 Clock Input Pin 2 from Microprocessor
7 CTW External Capacitor Pin for Setting Reset and Watchdog Timeout Periods
8 VDD Power supply Pin
NO.EA-172-200602 ABSOLUTE MAXIMUM RATINGS (Ta=25°C) Symbol Item Rating Unit VDD Supply Voltage −0.3 to 7.0 V VCD Output Voltage Voltage of CD Pin −0.3 to VDD + 0.3 V VCTW Voltage of CTW Pin −0.3 to VDD + 0.3 V VRESETB Voltage of RESETB Pin −0.3 to 7.0 V VSCK Input Voltage Voltage of SCK1, SCK2 Pin −0.3 to 7.0 V VINH Voltage of INH Pin −0.3 to 7.0 V IRESETB Output Current Current of RESETB Pin 20 mA PD Power Dissipation(1) (SSOP-8G) 380 mW Tj Junction Temperature −40 to 125 °C Tstg Storage Temperature Range −55 to 125 °C ABSOLUTE MAXIMUM RATINGS Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause permanent damage and may degrade the life time and safety for both device and system using the device in the field. The functional operation at or over these absolute maximum ratings are not assured. RECOMMENDED OPERATING CONDITONS Symbol Item Rating Unit VIN Input Voltage 0.9 to 6.0 V Ta Operating Temperature Range −40 to 105 °C RECOMMENDED OPERATING CONDITIONS All of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating conditions. The semiconductor devices cannot operate normally over the recommended operating condition s, even if they are used over such rating s by momentary electronic noise or surge. And the semiconductor devices may receive serious damage when they continue to operate over the recommended operating conditions. (1) Refer to POWER DISSIPATION for detailed information.
NO.EA-172-200602
ELECTRICAL CHARACTERISTICS
VDD=6.0V, CTW=0.1µF, CD=0.1µF, In case of Nch Open Drain Output type, the output pin is pulled up with a resistance of 100kΩ (R5109Gxx1A), unless otherwise noted. The specification in is checked and guaranteed by design engineering at −40°C ≤ Ta ≤ 105°C. R5109Gxx1A/C (Ta =25°C) Symbol Item Conditions Min. Typ. Max. Unit ISS Supply Current VDD= -VDET+0.5V, Clock pulse input 11.5 15.5 µA VD Part Symbol Item Conditions Min. Typ. Max. Unit -VDET Detector Threshold V VHYS Detector Threshold Hysteresis -VDET ×0.03 -VDET ×0.05 -VDET ×0.07 V Δ-VDET/ ΔTa Detector Threshold Temperature Coefficient −40°C ≤ Ta ≤ 105°C ±100 ppm/°C tPLH Output Delay Time CD=0.1µF (1) 340 370 467 ms IRESETB Output Current (RESETB Output pin) Nch VDD=1.2V VDS=0.1V 0.38 0.8 mA Pch (2) VDD=6.0V VDS=0.5V 0.65 0.9 mA WDT Part Symbol Item Conditions Min. Typ. Max. Unit tWD Watchdog Timeout period CTW=0.1µF (1) 230 310 450 ms tWR Reset Hold Time of WDT CTW=0.1µF (1) 29 34 48 ms VSCKH SCK Input "H" SCK1, SCK2 VDD×0.8 6.0 V VSCKL SCK Input "L" SCK1, SCK2 0 VDD×0.2 V VINHH INH Input "H" 1.0 6.0 V VINHL INH Input "L" 0 0.35 V RINH INH pull-up Resistance 60 110 164 kΩ tSCKW SCK Input Pulse Width VSCKL=VDD×0.2 VSCKH=VDD×0.8 500 ns All test items listed under Electrical Characteristics are done under the pulse load condition (Tj ≈ Ta = 25°C) except for Detector Threshold Temperature Coefficient. (1) The specification does not contain the temperature characteristics of the external capacitor. (2) In case of CMOS type (R5109Gxx1C)
NO.EA-172-200602 Product-specific Electrical Characteristics Product Name -VDET VHYS Ta = 25°C -40°C ≤ Ta ≤ 105 °C
NO.EA-172-200602 THEORY OF OPERATION TIMING CHART -VDET +VDET VRESETB VCTW VSCK1 VDD Vref2H Vref2L (1) (2) (3) VINH tWD VSCK2 VCD -VTCD (13) (11) tWDI tPLH tWR tPLH tPHL tPHL tPHL +VTCD (5) (6) (7) tPLH (2) (12) VDDL Undefined Undefined ∗) VTCD : Threshold voltage of CD pin when a power-on reset pulse inverting. ∗) Vref2H : CTW pin voltage at the end of WDT timeout period. ∗) Vref2L : CTW pin voltage at the begin of WDT timeout period ∗) VDDL : 0.9 V (Max.)
NO.EA-172-200602 Operating Description (1) When the power supply, V DD pin voltage becomes more than the released voltage (+V DET), after the released delay time (or the power on reset time tPLH), the output of RESETB becomes "H" level. (2) After the SCK1 pulse is input, when the SCK2 pulse is input, the watchdog timer is cleared, and C TW pin mode changes from the discharge mode to the charge mode. When the C TW pin voltage becomes higher than Vref2H, the mode will change into the discharge mode, and next watchdog time count starts. (3) After the SCK1 pulse is input, unless the SCK 2 pulse is input, WDT will not be cleared, and during the charging period of CTW pin, RESETB="L". (4) When the VDD pin becomes lower than the detector threshold voltage ( -VDET), RESETB outputs "L" after the tPHL. (5) If "L" signal is input to the INH pin, the RESETB outputs "H", regardless the SCK clock state. (6) During the "L" period of INH pin, the voltage detector monitors the supply voltage. (7) When the signal to the INH pin is set from "L" to "H", the watchdog starts supervising the system cloc k, or charge cycle to the C TW pin starts, the capacitor connected to the C TW pin is charged with the current of setting Reset time of WDT. (8) After the SCK1 pulse is input, when the SCK2 is input, the WDT will be cleared. (9) Without the input of SCK1 pulse input, even if the SCK2 pulse is input, the WDT will not be cleared. (10) After the SCK1 pulse is input, when the SCK2 is input, the WDT will be cleared. (11) If SCK1 pulse and SCK2 pulse are input at the same time, the WDT will not be cleared. (12) After from the discharge of the external capacitor even if the clock pulse is input during the time period "tWDI", the clock pulse is ignored. (13) After the SCK1 pulse is input, when the SCK2 is input, the WDT will be cleared. (14) The WDT supervises SCK1 pulse and SCK2 pulse by turns, therefore, for example, if only SCK1 pulse is input twice or more without SCK2 pulse, the second or later consecutive SCK1 pulse will be ignored. After the SCK1 pulse is input, and when the SCK2 pulse is input, the WDT will be cleared. In the same way, if only SCK2 pulse is input twice or more without SCK1 pulse, the second or later consecutive SCK2 pulse will be ignored. Too close timing of SCK1 pulse input and SCK2 pulse input means the rising edge interval time range from 0ns to 50ns. (Guaranteed by design, not mass production tested.) Even if the SCK1 and SCK2 are input at almost the same time as above, the WDT will still try to supervise these two clock by turns. Therefore, after the SCK1 pulse is input, if SCK1 pulse and SCK2 pulse are input at almost the same time, the WDT will be cleared. (as the status (8)) Likewise, after the SCK1 pulse and SCK2 pulse are input at almost the same time, when the SCK2 pulse is input, the WDT will be cleared. (as the status (10)) If the almost same timing input of SCK1 and SCK2 continues twice, the WDT will be cleared. (as the status (13))
NO.EA-172-200602 t SCK2 SCK1 0~50ns Example timing of too close input pulses (This pattern will be recognized the clock timing is same by the WDT) Watchdog Timeout period/Reset hold time The watchdog timeout period and reset hold time can be set with an external capacitor to C TW pin. The next equations describe the relation between the watchdog timeout period and the external capacitor value, or the reset hold time and the external capacitor value. t WR (s) = tWD/9 The watchdog timer (WDT) timeout period is determined with the discharge time of the external capacitor. During the watchdog timeout period, if the clock pulse from the system is detected, WDT is cleared and the capacitor is charged. When the charge of the capacitor completes, another watchdog timeout period starts again. During the watchdog timeout period, if the clock pulse from the system is not detected, during the next reset hold time RESETB pin outputs "L". During the reset time, (while charging the external capacitor) and after starting the watchdog timeout period, (just after from the discharge of the external capacitor) even if the clock pulse is input during the time period WDI", the clock pulse is ignored. tWDI (s) = tWD/10 Released Delay Time (Power-on Reset delay time) The released delay time can be set with an external capacitor connected to the C D pin. The next equation describes the relation between the capacitance value and the released delay time (t PLH). tPLH (s) =3.7 × 106 × C (F) The capacitor connected to CD pin determines tWD, tWR, and tPLH. When the VDD voltage becomes equal or less than ( -VDET), discharge of the capacitor connected to the C D pin starts. Therefore, if the discharge is not enough and VDD voltage returns to (+VDET) or more, thereafter the delay time will be shorter than tPLH which is expected.
NO.EA-172-200602 Power on Reset Operation against the input glitch (tPLH1 < tPLH) VDD VCD VRESETB Complete Discharge +VDET -VDET +VTCD -VTCD tPLH1 tPLH Incomplete Discharge Minimum Operating Voltage We specified the minimum operating voltage as the minimum input voltage in which the condition of RESETB pin being 0.1V or lower than 0.1V. (Herein, pull- up resistance is set as 100k Ω in the case of the Nch open- drain output type.) Inhibit (INH) Function If INH pin is set at "L", the watchdog timer stops monitoring the clock, and the RESETB output will be dominant by the voltage detector's operation. Therefore, if the supply voltage is set at more than the detector threshold level, RESETB outputs "H" regardless the clock pulse. INH pin is pulled up with a resistor (Typ.110kΩ) internally. RESETB Output RESETB pin's output type is selectable either the Nch open- drain output or CMOS output. If the Nch open- drain type output is selected, the RESETB pin is pulled up with an external resistor to an appropriate voltage source. Clock Pulse Input Built-in watchdog timer is cleared with the SCK clock pulse within the watchdog timeout period. After the SCK1 clock pulse is input, when the SCK2 pulse is input, the watchdog timer will be cleared. If the system requires only one clock supervise, SCK1 pin and SCK2 pin must connect each other. In this case, the watchdog timer is cleared with every other clock pulse. Depending on the timing of these two clock pulses, SCK1 pulse and SCK2 pulse are recognized at almost the same time by the watchdog timer, during the watchdog timeout period, after the SCK1 clock pulse, two or more SCK2 clock pulses are desirable to put into.
NO.EA-172-200602
APPLICATION INFORMATION
Typical Application Circuits R5109Gxx1A CD VDD RESET I/O R CTW GND VDD CD RESETB SCK2 CTW Microprocessor 1 Power Supply SW INH SCK1 VDD RESET I/O Microprocessor 2 R5109Gxx1A R5109Gxx1C CD VDD RESET I/O CTW GND VDD CD RESETB SCK2 CTW Microprocessor 1 Power Supply SW INH SCK1 VDD RESET I/O Microprocessor 2 R5109Gxx1C
NO.EA-172-200602 TECHNICAL NOTES When connecting resistors to the device’s input pin When connecting a resistor (R1) to an input of this device, the input voltage decreases by [Device’ s Consumption Current] x [Resistance Value] only. And, the cross conduction current (1 ), which occurs when changing from the detecting state to the release state, is decreased the input voltage by [Cross Conduction Current] x [Resistance Value] only. And then, this device will enter the re -detecting state if the input voltage reduction is larger than the difference between the detector voltage and the released voltage. When the input resistance value is large and the VDD is gone up at mildly in the vicinity of the released voltage, repeating the above operation may result in the occurrence of output. As shown in Figure A/B, set R1 to become 100kΩ or less as a guide, and connect C IN(2) of 0.1μF and more to between the input pin and GND. Besides, make evaluations including temperature properties under the actual usage condition, with using the evaluation board like this way. As result, make sure that the cross conduction current has no problem. VDD GND OUT pin CIN(2) Figure A Voltage Detector VDD GND OUT pin CIN(2) Figure B Voltage Detector (1) In the CMOS output type, a charging current for OUT pin is included. (2) Note the bias dependence of capacitors.
NO.EA-172-200602 TYPICAL CHARACTERISTICS Note: Typical Characteristics are intended to be used as reference data; they are not guaranteed. 1) Supply Current vs. Input Voltage R510xx151x R510xx301x 2) Detector Threshold vs. Temperature R510xx151x R510xx271x R510xx421x
NO.EA-172-200602 3) Detector Threshold Hysteresis vs. Temperature R510xx151x R510xx271x R510xx421x 4) Nch Driver Output Current vs. VDS R510xx
NO.EA-172-200602 5) Nch Driver Output Current vs. Input Voltage R510xx R510xx 6) Pch Driver Output Current vs. Input Voltage R510xx R510xx R510xx
NO.EA-172-200602 7) Released Delay Time vs. Input Voltage 8 ) Released Delay Time vs. Temperature R510xx R510xx 9) Detector Output Delay Time vs. Temperature 10) WDT Reset Timer vs. Temperature R510xx R510xx 11) WDT Timeout Period vs. Temperature 12) WDT Reset Timer vs. Input Voltage R510xx R510xx
NO.EA-172-200602 13) WDT Timeout Period vs. Input Voltage 14) Output Delay Time vs. External Capacitance R510xx R510xx
Ver. A i The power dissipation of the package is dependent on PCB material, layout, and environmental conditions. The following conditions are used in this measurement. Measurement Conditions Standard Test Land Pattern Environment Mounting on Board (Wind Velocity = 0 m/s) Board Material Glass Cloth Epoxy Plastic (Double-Sided Board) Board Dimensions 40 mm × 40 mm × 1.6 mm Copper Ratio Top Side: Approx. 50% Bottom Side: Approx. 50% Through-holes φ 0.5 mm × 44 pcs Measurement Result (Ta = 25°C, Tjmax = 125°C) Standard Test Land Pattern Power Dissipation 380 mW Thermal Resistance θjc = 60°C/W IC Mount Area (mm) Power Dissipation vs. Ambient Temperature Measurement Board Pattern 100 150 200 250 300 350 400 0 25 50 75 100 125 150 Power Dissipation PD (mW) Ambient Temperature (℃) 380
PACKAGE DIMENSIONS SSOP-8G Ver. A i 2.9±0.2 8 5 1 4 0.475nom. 2.8±0.2 4.0±0.2 0.45±0.15 0.65 0.1 1.3 max (1.2 ) +0.1 -0.2 0.2±0.1 0.15 M 0.1±0.1 1.1±0.1 0°-15° 0.125 +0.1 -0.05
1.5IFQSPEVDUTBOEUIFQSPEVDUTQFDJpDBUJPOTEFTDSJCFEJOUIJTEPDVNFOUBSFTVCKFDUUPDIBOHFPSEJTDPOUJOVBUJPOPG QSPEVDUJPOXJUIPVUOPUJDFGPSSFBTPOTTVDIBTJNQSPWFNFOU5IFSFGPSF,CFGPSFEFDJEJOHUPVTFUIFQSPEVDUT QMFBTFSFGFS UPourTBMFTSFQSFTFOUBUJWFTGPSUIFMBUFTUJOGPSNBUJPOUIFSFPO. 2.5IFNBUFSJBMTJOUIJTEPDVNFOUNBZOPUCFDPQJFEPSPUIFSXJTFSFQSPEVDFEJOXIPMFPSJOQBSUXJUIPVUQSJPSXSJUUFO DPOTFOUPGour company. 3.1MFBTFCFTVSFUPUBLFBOZOFDFTTBSZ GPSNBMJUJFTVOEFSSFMFWBOUMBXTPSSFHVMBUJPOTCFGPSFFYQPSUJOHPSPUIFSXJTF UBLJOHPVUPGZPVSDPVOUSZUIFQSPEVDUTPSUIFUFDIOJDBMJOGPSNBUJPOEFTDSJCFEIFSFJO 4.5IFUFDIOJDBMJOGPSNBUJPOEFTDSJCFEJOUIJTEPDVNFOUTIPXTUZQJDBMDIBSBDUFSJTUJDTPGBOEFYBNQMFBQQMJDBUJPODJSDVJUT GPSUIFQSPEVDUT5IFSFMFBTFPGTVDIJOGPSNBUJPOJTOPUUPCFDPOTUSVFEBTBXBSSBOUZPGPSBHSBOUPGMJDFOTFVOEFS our company's PSBOZUIJSEQBSUZTJOUFMMFDUVBMQSPQFSUZSJHIUTPSBOZPUIFSSJHIUT. 5.5IFQSPEVDUTMJTUFEJOUIJTEPDVNFOUBSFJOUFOEFEBOEEFTJHOFEGPSVTFBTHFOFSBMFMFDUSPOJDDPNQPOFOUTJOTUBOEBSE BQQMJDBUJPOT P⒏DFFRVJQNFOU UFMFDPNNVOJDBUJPOFRVJQNFOU NFBTVSJOHJOTUSVNFOUT DPOTVNFSFMFDUSPOJDQSPEVDUT BNVTFNFOUFRVJQNFOUFUD 5IPTFDVTUPNFSTJOUFOEJOHUPVTFBQSPEVDUJOBOBQQMJDBUJPOSFRVJSJOHFYUSFNFRVBMJUZBOE SFMJBCJMJUZ GPSFYBNQMF JOBIJHIMZTQFDJpDBQQMJDBUJPOXIFSFUIFGBJMVSFPSNJTPQFSBUJPOPGUIFQSPEVDUDPVMESFTVMUJO IVNBOJOKVSZPSEFBUI BJSDSBGU TQBDFWFIJDMF OVDMFBSSFBDUPSDPOUSPMTZTUFN USB⒏DDPOUSPMTZTUFN BVUPNPUJWFBOE USBOTQPSUBUJPOFRVJQNFOU DPNCVTUJPOFRVJQNFOU TBGFUZEFWJDFT MJGFTVQQPSUTZTUFNFUD TIPVMEpSTUDPOUBDUVT. 6.8FBSFNBLJOHPVSDPOUJOVPVTF⒎PSUUPJNQSPWFUIFRVBMJUZBOESFMJBCJMJUZPGPVSQSPEVDUT CVUTFNJDPOEVDUPSQSPEVDUT BSFMJLFMZUPGBJMXJUIDFSUBJOQSPCBCJMJUZ*OPSEFSUPQSFWFOUBOZJOKVSZUPQFSTPOTPSEBNBHFTUPQSPQFSUZSFTVMUJOHGSPN TVDIGBJMVSF DVTUPNFSTTIPVMECFDBSFGVMFOPVHIUPJODPSQPSBUFTBGFUZNFBTVSFTJOUIFJSEFTJHO TVDIBTSFEVOEBODZ GFBUVSF pSFDPOUBJONFOUGFBUVSFBOEGBJMTBGFGFBUVSF8FEPOPUBTTVNFBOZMJBCJMJUZPSSFTQPOTJCJMJUZGPSBOZMPTTPS EBNBHFBSJTJOHGSPNNJTVTFPSJOBQQSPQSJBUFVTFPGUIFQSPEVDUT. 7."OUJSBEJBUJPOEFTJHOJTOPUJNQMFNFOUFEJOUIFQSPEVDUTEFTDSJCFEJOUIJTEPDVNFOU 8.5IF9SBZFYQPTVSFDBOJOqVFODFGVODUJPOTBOEDIBSBDUFSJTUJDTPGUIFQSPEVDUT$POpSNUIFQSPEVDUGVODUJPOTBOE DIBSBDUFSJTUJDTJOUIFFWBMVBUJPOTUBHF. 9.8-$41QSPEVDUTTIPVMECFVTFEJOMJHIUTIJFMEFEFOWJSPONFOUT5IFMJHIUFYQPTVSFDBOJOqVFODFGVODUJPOTBOE DIBSBDUFSJTUJDTPGUIFQSPEVDUTVOEFSPQFSBUJPOPSTUPSBHF. 10.5IFSFDBOCFWBSJBUJPOJOUIFNBSLJOHXIFOEJ⒎FSFOU"0* "VUPNBUFE0QUJDBM*OTQFDUJPO FRVJQNFOUJTVTFE*OUIFDBTF PGSFDPHOJ[JOHUIFNBSLJOHDIBSBDUFSJTUJDXJUI"0*,QMFBTFDPOUBDUourTBMFTPSPVSEJTUSJCVUPSCFGPSFBUUFNQUJOHUPVTF "0*. 11.1MFBTFDPOUBDUourTBMFTSFQSFTFOUBUJWFTTIPVMEZPVIBWFBOZRVFTUJPOTPSDPNNFOUTDPODFSOJOHUIFQSPEVDUTPS UIFUFDIOJDBMJOGPSNBUJPO. Official website https://www.nisshinbo-microdevices.co.jp/en/ Purchase information https://www.nisshinbo -microdevices.co.jp/en/buy/