R5106N191X

R5106N NISSHINBO | Alldatasheet

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Technical content

Microprocessor Supervisory Circuit with Inhibit pin NO.EA-169-200602 OUTLINE The R5106N is a microprocessor supervisory circuit and has high accuracy and ultra low supply current voltage detector with built-in delay circuit and watchdog timer. When the supply voltage is down across the threshold, or the watchdog timer does not detect the system clock from the microprocessor, the reset output is generated. The voltage detector circuit is used for the system reset, etc. The detector threshold is fixed internally, and the accuracy is ±1.0%. The released delay time (Power-on Reset Delay) circuit is built-in, and output delay time is adjustable with an external capacitor, and the accuracy is ±16% (1). When the supply voltage becomes higher than the released voltage, the reset state will be maintained during the delay time. The output type of the reset is selectable, Nch open-drain, or CMOS. The time out period of the watchdog timer can be also set with an external capacitor, and the accuracy is ±33% (1). There is a function to stop supervising clock by the watchdog timer (INH function). There are another 4 products by the difference of packages and the function of voltage detector and watchdog timer. The package of R5106N is SOT-23-6.

FEATURES

< Voltage Detector Part > < Watchdog Timer Part >

APPLICATIONS

• Supervisory circuit for equipment with using microprocessors. (1) Accuracy to center value of (Min.+Max.)/2

NO.EA-169-200602 SELECTION GUIDE The detector threshold, the output type and the taping type for the ICs can be selected at the user s’ request. The selection can be made with designating the part number as shown below; Product Name Package Quantity per Reel Pb Free Halogen Free R5106Nxx1∗-TR-FE SOT-23-6 3,000 pcs Yes Yes xx : The detector threshold (-VDET) can be designated in the range from 1.5V(15) to 5.5V(55) in 0.1V steps. ∗ : Designation of Output Type (A) Nch Open Drain (C) CMOS Series Selection R5105N R5106N R5107G R5108G R5109G Package SOT-23-6 SSOP-8G With INH pin (Inhibit) No Yes 2 clock input No Yes With MR pin (Manual Reset) No Yes No With SENSE pin No Yes No Remarks CD pin and CTW pin are combined uses. Operating Voltage Range 1.5V to 6.0V Supply Current 11.5µA

NO.EA-169-200602 BLOCK DIAGRAMS R5106Nxx1A (Nch Open Drain Output) R5106Nxx1C (CMOS Output) VDD GND SCK RESETB CT WATCHDOG TIMER CLOCK DETECTOR

2 INH

SW1: "L"=ON, SW2: "H"=ON PIN DESCRIPTIONS

• SOT-23-6 6 5 4 1 2 3 (mark side)
• SOT-23-6 Pin No. Symbol Description

1 SCK Clock Input Pin from Microprocessor

2 INH Inhibit Pin ("L": Inhibit the watchdog timer)

3 VDD Power supply Pin

4 RESETB

Output Pin for Reset signal of Watchdog timer and Voltage Detector. (Output "L" at detecting Detector Threshold and Watchdog Timer Reset.)

5 GND Ground Pin

6 CT External Capacitor Pin for Setting Reset and Watchdog Timeout

Periods and delay time of Voltage Detector

NO.EA-169-200602 ABSOLUTE MAXIMUM RATINGS (Ta=25°C) Symbol Item Rating Unit VDD Supply Voltage -0.3 to 7.0 V VCT Output Voltage Voltage of CT Pin -0.3 to VDD + 0.3 V VRESETB Voltage of RESETB Pin -0.3 to 7.0 V VSCK Input Voltage Voltage of SCK Pin -0.3 to 7.0 V VINH Voltage of INH Pin -0.3 to 7.0 V IRESETB Output Current Current of RESETB Pin 20 mA PD Power Dissipation(1) (SOT-23-6, JEDEC STD. 51-7) 660 mW Tj Junction Temperature -40 to 125 °C Tstg Storage Temperature Range -55 to 125 °C ABSOLUTE MAXIMUM RATINGS Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause permanent damage and may degrade the life time and safety for both device and system using the device in the field. The functional operation at or over these absolute maximum ratings are not assured. RECOMMENDED OPERATING CONDITIONS Symbol Item Rating Unit VDD Operating Voltage 0.9 to 6.0 V Ta Operating Temperature Range −40 to 105 °C RECOMMENDED OPERATING CONDITIONS All of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating conditions. The semiconductor devices cannot operate normally over the recommended operating condition s, even if they are used ov er such rating s by momentary electronic noise or surge. And the semiconductor devices may receive serious damage when they continue to operate over the recommended operating conditions. (1) Refer to POWER DISSIPATION for detailed information.

NO.EA-169-200602

ELECTRICAL CHARACTERISTICS

VDD=6.0V, CT=0.1µF, In case of Nch Open Drain Output type, the output pin is pulled up with a resistance of 100kΩ (R5106Nxx1A), unless otherwise noted. The specification in is checked and guaranteed by design engineering at −40°C ≤ Ta ≤ 105°C. R5106Nxx1A/C (Ta=25°C) Symbol Item Conditions Min. Typ. Max. Unit ISS Supply Current VDD= -VDET+0.5V, Clock pulse input 11 15 µA VD Part Symbol Item Conditions Min. Typ. Max. Unit -VDET Detector Threshold V ∆-VDET /∆Ta Detector Threshold Temperature Coefficient −40°C ≤ Ta ≤ 105°C ±100 ppm /°C VHYS Detector Threshold Hysteresis -VDET ×0.03 -VDET ×0.05 -VDET ×0.07 V tPLH Output Delay Time CT=0.1µF (1) 340 370 467 ms IRESETB Output Current (RESETB Output pin) Nch VDD=1.2V, VDS=0.1V 0.38 0.8 mA Pch (2) VDD=6.0V, VDS=0.5V 0.65 0.9 mA WDT Part Symbol Item Conditions Min. Typ. Max. Unit tWD Watchdog Timeout period CT=0.1µF (1) 230 310 450 ms tWR Reset Hold Time of WDT CT=0.1µF (1) 29 34 48 ms VSCKH SCK Input "H" VDD×0.8 6.0 V VSCKL SCK Input "L" 0 VDD×0.2 V VINHH INH Input "H" 1.0 6.0 V VINHL INH Input "L" 0 0.35 V RINH INH pull-up Resistance 60 110 164 kΩ tSCKW SCK Input Pulse Width VSCKL=VDD×0.2 VSCKH=VDD×0.8 500 ns All test items listed under Electrical Characteristics are done under the pulse load condition (Tj ≈ Ta = 25°C) except for Detector Threshold Temperature Coefficient. (1) The specification does not contain the temperature characteristics of the external capacitor. (2) In case of CMOS type (R5105Nxx1C)

NO.EA-169-200602 Product-specific Electrical Characteristics Product Name -VDET VHYS Ta = 25°C -40°C ≤ Ta ≤ 105 °C

NO.EA-169-200602 THEORY OF OPERATION Timing Chart -VDET +VDET VRESETB VCT VSCK VDD Vref2H Vref2L VINH tPLH tWDI (1) (2) (4) (3) tWD (5) (6) (7) tPLH tWR tPHL VDDL Undefined Undefined ∗) Vref2H : CT pin voltage at the end of WDT timeout period. ∗) Vref2L : CT pin voltage at the begin of WDT timeout period. ∗) VDDL : 0.9 V (Max.)

NO.EA-169-200602 Operating Description (1) When the power supply, V DD pin voltage becomes more than the released voltage (+V DET), after the released delay time (or the power on reset time tPLH), the output of RESETB becomes "H" level. (2) When the SCK pulse is input, the watchdog timer (WDT) is cleared, and C T pin mode changes from the discharge mode to the charge mode. When the C T pin voltage becomes higher than V ref2H, the mode will change into the discharge mode, and next watchdog time count starts. (3) Unless the SCK pulse is input, WDT will not be cleared, and during the charging period of C T pin, RESETB="L". (4) When the VDD pin becomes lower than the detector threshold voltage (-VDET), RESETB outputs "L". (5) If "L" signal is input to the INH pin, the RESETB outputs "H", regardless the SCK clock state. (6) During the "L" period of INH pin, the voltage detector monitors the supply voltage. (7) When the signal to the INH pin is set from "L" to "H", the watchdog starts supervising the system clock, or charge cycle to the CT pin starts, the capacitor connected to the CT pin is charged with the current of setting Reset time of WDT. Watchdog Timeout period/Reset hold time The watchdog timeout period and reset hold time can be set with an external capacitor to C T pin. The next equations describe the relation between the watchdog timeout period and the external capacitor value, or the reset hold time and the external capacitor value. t WD (s) = 3.1×106×C (F) t WR (s) = tWD/9 The watchdog timer (WDT) timeout period is determined with the discharge time of the external capac itor. During the watchdog timeout period, if the clock pulse from the system is detected, WDT is cleared and the capacitor is charged. When the charge of the capacitor completes, another watchdog timeout period starts again. During the watchdog timeout period, if the clock pulse from the system is not detected, during the next reset hold time RESETB pin outputs "L". During the reset time, (while charging the external capacitor) and after starting the watchdog timeout period, (just after from the discharge of the external capacitor) even if the clock pulse is input during the time period WDI", the clock pulse is ignored. tWDI (s) = tWD/10 Released Delay Time (Power-on Reset delay time) The released delay time can be set with an external capacitor connected to the C T pin. The next equation describes the relation between the capacitance value and the released delay time (t PLH). tPLH (s) =3.7×106× C (F) The capacitor connected to CT pin determines tWD, tWR, and tPLH. When the VDD voltage becomes equal or less than ( -VDET), discharge of the capacitor connected to the C T pin starts. Therefore, if the discharge is not enough and VDD voltage returns to (+VDET) or more, thereafter the delay time will be shorter than tPLH which is expected.

NO.EA-169-200602 Power on Reset Operation against the input glitch (tPLH1 < tPLH) VDD VCT VRESETB Complete Discharge +VDET -VDET +VTCT -VTCT tPHL tPLH1 Incomplete Discharge tPLH tPHL Minimum Operating Voltage We specified the minimum operating voltage as the minimum input voltage in which the condition of RESETB pin being 0.1V or lower than 0.1V. (Herein, pull- up resistance is set as 100k Ω in the case of the Nch open- drain output type.) Inhibit (INH) Function If INH pin is set at "L", the watchdog timer stops monitoring the clock, and the RESETB output will be dominant by the voltage detector's operation. Therefore, if the supply voltage is set at more than the detector threshold level, RESETB outputs "H" regardless the clock pulse. INH pin is pulled up with a resistor (TYP.110k Ω) internally. RESETB Output RESETB pin's output type is selectable either the Nch open- drain output or CMOS output. If the Nch open- drain type output is selected, the RESETB pin is pulled up with an external resistor to an appropriate voltage source. Clock Pulse Input Built-in watchdog timer is cleared with the SCK clock pulse within the watchdog timeout period.

NO.EA-169-200602

APPLICATION INFORMATION

R CT GND VDD INH RESETB SCK CT Microprocessor Power Supply R5106Nxx1A R5106Nxx1C SW VDD RESET I/O CT GND VDD INH RESETB SCK CT Microprocessor Power Supply R5106Nxx1C

NO.EA-169-200602 TECHNICAL NOTES When connecting resistors to the device’s input pin When connecting a resistor (R1) to an input of this device, the input voltage decreases by [Device’ s Consumption Current] x [Resistance Value] only. And, the cross conduction current (1 ), which occurs when changing from the detecting state to the release state, is decreased the input voltage by [Cross Conduction Current] x [Resistance Value] only. And then, this device will enter the re -detecting state if the input voltage reduction is larger than the difference between the detector voltage and the released voltage. When the input resistance value is large and the VDD is gone up at mildly in the vicinity of the released voltage, repeating the above operation may result in the occurrence of output. As shown in Figure A/B, set R1 to become 100kΩ or less as a guide, and connect C IN(2) of 0.1μF and more to between the input pin and GND. Besides, make evaluations including temperature properties under the actual usage condition, with using the evaluation board like this way. As result, make sure that the cross conduction current has no problem. VDD GND OUT pin CIN(2） Figure A Voltage Detector VDD GND OUT pin CIN(2） Figure B Voltage Detector (1) In the CMOS output type, a charging current for OUT pin is included. (2) Note the bias dependence of capacitors.

NO.EA-169-200602 TYPICAL CHARACTERISTICS Note: Typical Characteristics are intended to be used as reference data; they are not guaranteed. 1) Supply Current vs. Input Voltage R510xx151x R510xx301x 2) Detector Threshold vs. Temperature R510xx151x R510xx271x R510xx421x

NO.EA-169-200602 3) Detector Threshold Hysteresis vs. Temperature R510xx151x R510xx271x R510xx421x 4) Nch Driver Output Current vs. VDS R510xx

NO.EA-169-200602 5) Nch Driver Output Current vs. Input Voltage R510xx R510xx 6) Pch Driver Output Current vs. Input Voltage R510xx R510xx R510xx

NO.EA-169-200602 7) Released Delay Time vs. Input Voltage 8 ) Released Delay Time vs. Temperature R510xx R510xx 9) Detector Output Delay Time vs. Temperature 10) WDT Reset Timer vs. Temperature R510xx R510xx 11) WDT Timeout Period vs. Temperature 12) WDT Reset Timer vs. Input Voltage R510xx R510xx

NO.EA-169-200602 13) WDT Timeout Period vs. Input Voltage 14) Output Delay Time vs. External Capacitance R510xx R510xx

POWER DISSIPATION SOT-23-6 Ver. A i The power dissipation of the package is dependent on PCB material, layout, and environmental conditions. The following measurement conditions are based on JEDEC STD. 51-7. Measurement Conditions Item Measurement Conditions Environment Mounting on Board (Wind Velocity = 0 m/s) Board Material Glass Cloth Epoxy Plastic (Four-Layer Board) Board Dimensions 76.2 mm × 114.3 mm × 0.8 mm Copper Ratio Outer Layer (First Layer): Less than 95% of 50 mm Square Inner Layers (Second and Third Layers): Approx. 100% of 50 mm Square Outer Layer (Fourth Layer): Approx. 100% of 50 mm Square Through-holes φ 0.3 mm × 7 pcs Measurement Result (Ta = 25°C, Tjmax = 125°C) Item Measurement Result Power Dissipation 660 mW Thermal Resistance (θja) θja = 150°C/W Thermal Characterization Parameter (ψjt) ψjt = 51°C/W θja: Junction-to-Ambient Thermal Resistance ψjt: Junction-to-Top Thermal Characterization Parameter Power Dissipation vs. Ambient Temperature Measurement Board Pattern 100 200 300 400 500 600 700 800 900 1000 0 25 50 75 100 125 150 Power Dissipation (mW) Ambient Temperature (°C) 105 660

PACKAGE DIMENSIONS SOT-23-6 Ver. A i 2.9±0.2 1.9±0.2 (0.95) (0.95) 6 4 1 2 3 1.6-0.1 +0.2 2.8±0.3 0.4-0.2 Unit : mm +0.1 0.8±0.1 1.1-0.1 +0.2 0 to 0.1 0.15-0.05 +0.1 0.2MIN.

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