R3500S-Y NISSHINBO | Alldatasheet

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42 V Input 4ch Window Voltage Detector for Industrial Applications

No. EY-521-250725 The R35 00S is a 4ch window voltage de tector with manual reset function suited for systems requiring functional safety. This device monitors over and under voltage from the multiple power suppl ies to SoCs, memories and sensors to continuously supervise the system operat ing at normal voltage. This is a high - reliability semiconductor device for industrial applications ( -Y) that has passed both the screening at high temperature and the reliability test with extended hours.

  • Power supply from battery enables the voltage detector to operate independently from the power source.
  • Management of multiple power supplies with a single chip to save space.
  • Operating Voltage Range (Max. Rating): 3.0 V to 42.0 V (50.0 V)
  • Operating Temperature Range: −40°C to 125°C
  • Supply Current: Typ. 10 µA
  • Overvoltage Detection: 1.0 V to 5.9 V (0.01 V step)
  • Undervoltage Detection:0.9 V to 5.0 V (0.01 V step)
  • Detection Release Hysteresis: Max. 0.75% (−40°C to 125°C)
  • Detection Voltage Accuracy: ±0.5% (Ta = 25°C)
  • Detection Delay Time: Typ.20 µs
  • Release Delay Time: Typ. 4 ms (CD = 0.01 µF)
  • Output Type: Nch. Open Drain Product Name Package Quantity per Reel R3500SxxxA-E2-YE HSOP-18 1,000 pcs xxx: The combination of an overvoltage detection setting voltage (VOVSET) and an undervoltage detection setting voltage (VUVSET) applied to 4ch. Refer to “Product-Specific Electrical Characteristic” for details HSOP-18 5.2 x 6.2 x 1.45 (mm)
  • Factory Automation Equipment, Smart meters
  • High Temperature Devices: Surveillance Cameras and Vending Machines
  • Self-heating Devices: Motors and Lightings OVERVIEW KEY BENEFITS KEY SPECIFICATIONS SELECTION GUIDE PACKAGE

APPLICATIONS

TYPICAL APPLICATION CIRCUIT VDD VDD CD1 GND R3500S SENSE3 Battery SENSE2 SENSE1 CD DCDC DCDC DCDC LDO Vin1 Vin2 Vin3 Vin4 SOC SENSE4 DOUT1 DOUT2 DOUT3 DOUT4 VCCDET GPI0 GPI1 GPI2 GPI3 GPI4 CD2 CD3 CD4 MR GPO RVCCDET R1 R2 R4

No. EY-521-250725 SELECTION GUIDE The overvoltage detection setting voltage (VOVSET) and the undervoltage detection setting voltage (VUVSET) are user-selectable options. Selection Guide Product Name Package Quantity per Reel Pb Free Halogen Free R3500SxxxA-E2-YE HSOP-18 1,000 pcs Yes Yes xxx: The combination of an overvoltage detection setting voltage (VOVSET) and an undervoltage detection setting voltage (VUVSET). Refer to Product-specific Electrical Characteristics for more details. BLOCK DIAGRAM R3500S Block Diagram DOUT 1 - 4 SENSE 1 - 4 VREF 1 - 4 GND Delay Circuit 1 - 4 CD 1- 4 VDD OVCMP 1 - 4 UVCMP1 - 4 DRV 1 - 4 VCCDET INT Regulator OVLO UVLO MR MR UVCMP 1 - 4 OVCMP 1 - 4 VCC VCC GND GND

No. EY-521-250725 PIN DESCRIPTIONS Top View Bottom View R3500S (HSOP-18) Pin Configuration ∗ The tab on the bottom of the package shown by blue circle is substrate potential (GND). It is recommended that this tab be connected to the ground plane pin on the board. R3500S Pin Description Pin No. Symbol Description

1 VDD Supply Voltage Pin

2 NC No Connection(1)

3 VCCDET(2) Over/Under Voltage Detection for Internal Supply Output Pin

(“Low” at detection)

4 SENSE1 VD Voltage SENSE Pin 1

5 SENSE2 VD Voltage SENSE Pin 2

6 SENSE3 VD Voltage SENSE Pin 3

7 SENSE4 VD Voltage SENSE Pin 4

8 NC No Connection

9 MR Manual Reset Pin (“Low” at reset)

10 GND GND Pin

11 CD4 VD Release Delay Time Set Pin 4 (“OPEN” when not connected)

12 CD3 VD Release Delay Time Set Pin 3 (“OPEN” when not connected)

13 CD2 VD Release Delay Time Set Pin 2 (“OPEN” when not connected)

14 CD1 VD Release Delay Time Set Pin 1 (“OPEN” when not connected)

15 DOUT4(3) Over/Under Voltage Detection Output Pin 4 (“Low” at detection)

16 DOUT3(3) Over/Under Voltage Detection Output Pin 3 (“Low” at detection)

17 DOUT2(3) Over/Under Voltage Detection Output Pin 2 (“Low” at detection)

18 DOUT1(3) Over/Under Voltage Detection Output Pin 1 (“Low” at detection)

(1) NC pin should be set to “OPEN”. (2) VCCDET pin is required to pull up to a suitable voltage with an external resistor. (3) DOUT1 to 4 pins are required to pull up to a suitable voltage with an external resistor.

No. EY-521-250725 Internal Equivalent Circuit for Each Pin DOUT1 to 4 Pin VCCDET Pin DOUT1 - 4 Driver VCCDET Driver CD1 to 4 Pin SENSE1 to 4 Pin CD1 - 4 Driver VCC SENSE1 - 4 MR Pin MR VCC

No. EY-521-250725 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings Symbol Parameter Rating Unit VDD Supply Voltage −0.3 to 50.0 V Peak Voltage(1) 60 V VCD1 to 4 CD1 to 4 Pin Output Voltage −0.3 to 20.0 V VDOUT1 to 4 DOUT1 to 4 Pin Output Voltage −0.3 to 20.0 V VVCCDET VCCDET Pin Output Voltage −0.3 to 20.0 V VSENSE1 to 4 SENSE1 to 4 Pin Input Voltage −0.3 to 20.0 V VMR MR Pin Voltage −0.3 to 20.0 V IDOUT1 to 4 DOUT1 to 4 Pin Output Current 30 mA IVCCDET VCCDET Pin Output Current 15 mA PD Power Dissipation Refer to Appendix “POWER DISSIPATION” Tj Junction Temperature Range −40 to 150 °C Tstg Storage Temperature Range −55 to 150 °C ABSOLUTE MAXIMUM RATINGS Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause permanent damage and may degrade the life time and safety for both device and system using the device in the field. The functional operation at or over these absolute maximum ratings are not assured. RECOMMENDED OPERATING CONDITIONS Recommended Operating Conditions Symbol Parameter Rating Unit VDD Operating Voltage 3.0 to 42 V VSENSE1 to 4 SENSE 1 to 4 Pin Input Voltage 0 to 6.0 V VMR MR Pin Voltage 0 to 6.0 V Ta Operating Temperature Range −40 to 125 C RECOMMENDED OPERATING CONDITIONS All of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating condition s. The semiconductor devices cannot operate normally over the recommended operating condition s, even if they are used over such ratings by momentary electronic noise or surge. And the semiconductor devices may receive serious damage when they continue to operate over the recommended operating conditions. (1) Duration Time: within 200 ms

No. EY-521-250725

ELECTRICAL CHARACTERISTICS

VDD = 14 V, CD = 0.01 µF, pulled-up to 5 V with 100 kΩ, unless otherwise specified. The specifications surrounded by are guaranteed by design engineering at -40°C ≤ Ta ≤ 125°C. R3500S (-YE) Electrical Characteristics (Ta= 25°C) Symbol Parameter Conditions Min. Typ. Max. Unit VOVDET1 to 4 Overvoltage (OV) Detector Threshold Ta = 25°C x0.995 x1.005 V –40°C ≤ Ta ≤ 125°C x0.9875 x1.0075 V VUVDET1 to 4 Undervoltage (UV) Detector Threshold Ta = 25°C x0.995 x1.005 V –40°C ≤ Ta ≤ 125°C x0.9875 x1.0075 V VOVHYS1 to 4 Overvoltage (OV) Threshold Hysteresis VOVDET 0.0025 VOVDET 0.005 VOVDET 0.0075 V VUVHYS1 to 4 Undervoltage (UV) Threshold Hysteresis VUVDET 0.0025 VUVDET 0.005 VUVDET 0.0075 V ISS Supply Current VDD = 42 V, VUVDET < VSENSE < VOVDET 10 25 µA RSENSE1 to 4 SENSE1 to 4 Pin Resistance(1) 2.5 30 MΩ VUVLO UVLO Detector Voltage 1.8 2.8 V VUVLOHYS UVLO Threshold Hysteresis 0.1 0.2 V VDDLDOUT1 to 4 Supply Voltage with Low-operating DOUT1 to 4 Pin Output Voltage(2) 1.7 V IDOUT1 to 4 DOUT1 to 4 Pin Driver ILEAK1 to 4 DOUT1 to 4 Pin Leak Current VDOUT1 to 4 = 5.5 V 0 1.0 µA VMRH MR Input Voltage “High” 1.6 V VMRL MR Input Voltage “Low” 0.5 V tDELAY1 to 4 Release Delay Time CD = 0.01 µF 2.5 4 8 ms IVCCDET VCCDET Pin ILEAKVCCDET VCCDET Pin Driver Leakage Current VDS = 5.5 V 0 0.3 µA All test items listed in Electrical Characteristics are done under the pulse load condition (Tj ≈ Ta = 25°C). (1) Typ. value is varied depending on the set value of detection voltage. (2) Minimum value of the power supply voltage when the detection output voltage becomes 0.1 V or lower. (Pull-up resistance: 100 kΩ, Pull-up voltage: 5 V)

No. EY-521-250725 VDD = 14 V, CD = 0.01 µF, pulled-up to 5 V with 100 kΩ, unless otherwise specfied. R3500S (-YE) Product-specific Electrical Characteristics (Ta = 25°C) Product name VUVDET (V) VOVDET (V) R3500S001A R3500S002A R3500S003A R3500S004A R3500S005A R3500S006A R3500S007A R3500S008A R3500S009A R3500S010A

No. EY-521-250725 VDD = 14 V, CD = 0.01 µF, pulled-up to 5 V with 100 kΩ, unless otherwise specfied. R3500S (-YE) Product-specific Electrical Characteristics (Ta = 25°C) Product name VUVDET (V) VOVDET (V) R3500S011A R3500S012A R3500S013A

No. EY-521-250725 VDD = 14 V, CD = 0.01 µF, pulled-up to 5 V with 100 kΩ, unless otherwise specfied. The specifications surrounded by are guaranteed by design engineering at −40°C ≤ Ta ≤ 125°C. R3500S (-YE) Product-specific Electrical Characteristics (−40°C ≤ Ta ≤ 125°C) Product name VUVDET (V) VOVDET (V) VUVHYS (V) VOVHYS (V) R3500S001A R3500S002A R3500S003A R3500S004A R3500S005A R3500S006A R3500S007A R3500S008A R3500S009A R3500S010A

No. EY-521-250725 VDD = 14 V, CD = 0.01 µF, pulled-up to 5 V with 100 kΩ, unless otherwise specfied. The specifications surrounded by are guaranteed by design engineering at −40°C ≤ Ta ≤ 125°C. R3500S (-YE) Product-specific Electrical Characteristics (−40°C ≤ Ta ≤ 125°C) Product name VUVDET (V) VOVDET (V) VUVHYS (V) VOVHYS (V) R3500S011A R3500S012A 1ch 3.101 3.14 3.163 3.417 3.46 3.485 0.008 R3500S013A

No. EY-521-250725 TYPICAL APPLICATION CIRCUIT R3500S Typical Application External Components Symbol Description CD Capacitors should be selected corresponding to the set Release Delay Time. Refer to “Delay in Operation and Release Delay Time (tDELAY)” in THEORY OF OPERATION for details. When the Release Delay Time is unnecessary, layout the circuit without any capacitors. Rn RVCCDET The on-resistance of the driver is max. 270 Ω calculated from the DOUTn (n=1 to 4) pin driver output current shown in “Electrical Characteristics”. The maximum voltage at DOUTn=“Low” is determined by the maximum on-resistance, pull-up voltage and Rn. The off-resistance of the driver is min. 5.5 MΩ calculated from the driver leakage current shown in “Electrical Characteristics”. The minimum voltage at DOUTn=“High” is determined by the minimum off- resistance, pull-up voltage and Rn. Set the VCCDET pin in the same way. “Electrical Characteristic” is evaluated in conditions that Pull-up voltage = 5 V and Rn = 100 kΩ. SENSEn and DOUTn pins should be set to open when they are not connected. VDD VDD CD1 GND R3500S SENSE3 Battery SENSE2 SENSE1 CD DCDC DCDC DCDC LDO Vin1 Vin2 Vin3 Vin4 SOC SENSE4 DOUT1 DOUT2 DOUT3 DOUT4 VCCDET GPI0 GPI1 GPI2 GPI3 GPI4 CD2 CD3 CD4 MR GPO RVCCDET R1 R2 R4

No. EY-521-250725 THEORY OF OPERATION R3500S Timing Chart (1) When the SENSEn pin voltage (VSENSEn) exceeds the undervoltage release voltage (VUVRELn), the DOUTn pin outputs “High” after the release delay time (tDELAYn). (2) When VSENSEn exceeds the overvoltage detection voltage (VOVDETn), the DOUTn pin outputs “Low” after the detection delay time (Typ.20 µs) and this triggers the overvoltage detecting state. (3) When VSENSEn drops below the overvoltage release voltage (VOVRELn), the DOUTn pin outputs “High” after the release delay time (tDELAYn). (4) When VSENSEn drops further below the undervoltage detection voltage (VUVDETn), the DOUTn pin outputs “Low” after the detection delay time (Typ.20 µs) and this triggers the undervoltage detecting state. (5) When the VDD pin voltage (VDD) drops below the UVLO detection voltage (VUVLO), the DOUTn pin outputs “Low”. Note that DOUT n cannot maintain "Low" when the VDD pin voltage drops further and becomes lower than VDDLDOUTn. VDD VSENSEn CDn DOUTn VUVRELn tDELAYn VUVDETn VUVRELn tDELAYn VUVLOVUVLO+VUVLOHYS VOVDETn tDELAYn VOVRELn (n=1 to 4) tDELAYn depends on the capacity connected to the CDn pin. UVLO Release Voltage: VUVLO+VUVLOHYS UVLO Detection Voltage: VUVLO Overvoltage Detection Voltage: VOVDETn Overvoltage Release Voltage：VOVRELn Undervoltage Release Voltage ：VUVRELn Undervoltage Detection Voltage：VUVDETn

No. EY-521-250725 Delay Operation and Release Delay Time (tDELAY) At Undervoltage Detection A higher voltage than the undervoltage release voltage (VUVRELn) supplied to the SENSEn pin triggers charging of the external capacitor then the CDn pin voltage (VCDn) increases. The DOUTn pin voltage (VDOUTn) maintains “Low” until VCDn reaches the CDn pin threshold voltage (VTCDn). When VCDn exceeds VTCDn, VDOUTn transitions from “Low” to “High”. The release delay time (t DELAYn) is the period until VDOUTn transitions to “High” after the SENSEn pin voltage (VSENSEn) exceeds VUVRELn. The output voltage transitions from “Low” to “High” and it leads to discharging of the external capacitor. Without CD capacitors, the release delay time (Typ. 20 µs) becomes short depending on the circuit delay and CDn pin stray capacitance. When the lower voltage than VUVDETn is supplied to the SENSEn pin, the detection delay time (tPHLn) for which VDOUTn transitions from “High” to “Low” is independent from the external capacitor and will be constant. VTCDn VUVRELn GND GND VUVDETn Detection Delay Time (tPHLn) Release Delay Time (tDELAYn) SENSEn Pin CDn Pin Voltage DOUTn Pin Undervoltage Release Delay Timing Diagram Calculation of Release Delay Time (tDELAY) The typical value of the release delay time ( tDELAYn) with the capacitance of the external capacitor (CD) is calculated in the following equation: tDELAYn (s) = 0.73  CD (F) / (1.810-6) tDELAYn is the period until the DOUT n pin voltage ( VDOUTn) reaches 2.5 V after the pulse voltage of (VUVDETn+VOVDETn) /2 V increased from (VUVDETn x 0.97) V is supplied to the SENSEn pin when VDOUTn is pulled up to 5 V with 100 kΩ. (VUVDETn + VOVDETn) / 2 V SENSEn Pin GND 5.0 V 2.5 V GND DOUTn Pin tDELAYn tPHLn (VUVDETnx 0.97) V VUVRELn VUVDETn

No. EY-521-250725 At Overvoltage Detection A lower voltage than the overvoltage release voltage (VOVRELn) supplied to the SENSEn pin triggers charging of the external capacitor then the CDn pin voltage (VCDn) increases. The DOUTn pin voltage (VDOUTn) maintains “Low” until VCDn reaches the CDn pin threshold voltage (VTCDn). When VCDn exceeds VTCDn, VDOUTn transitions from “Low” to “High”. The release delay time (t DELAYn) is the period until VDOUTn transitions to “High” after the SENSEn pin voltage (VSENSEn) exceeds VOVRELn. The output voltage transitions from “Low” to “High” and it leads to discharging of the external capacitor. Without CD capacitors, the release delay time (Typ. 20 µs) becomes short depending on the circuit delay and CD n pin stray capacitance. When the higher voltage than VOVDETn is supplied to the SENSEn pin, the detection delay time (tPHLn) for which VDOUTn transitions from “High” to “Low” is independent from the external capacitor and will be constant. Overvoltage Release Delay Timing Diagram Calculation of Release Delay Time (tDELAY) The typical value of the release delay time ( tDELAYn) with the capacitance of the external capacitor (CD) is calculated in the following equation: tDELAYn (s) = 0.73  CD (F) / (1.810-6) tDELAYn is the period until the DOUT n pin voltage ( VDOUTn) reaches 2.5 V after the pulse voltage of (VUVDETn+VOVDETn) /2 V decreased from (VOVDETn x 1.03) V is supplied to the SENSEn pin when VDOUTn is pulled up to 5 V with 100 kΩ. (VUVDETn + VOVDETn) / 2 V SENSEn Pin GND 5.0 V 2.5 V GND DOUTn Pin tDELAYn tPHLn (VOVDETn x 1.03) V VOVDETn VOVRELn VTCDn VOVDETn GND GND VOVRELn Detection Delay Time (tPHLn) Release Delay Time (tDELAYn) SENSEn Pin CDn Pin Voltage DOUTn Pin

No. EY-521-250725 Manual Reset Function with MR Pin The manual reset function is to set DOUTn to "Low" by inputting "Low" to the MR pin even when VSENSEn is within a range of the release voltage . In other cases , set the MR pin voltage to "H igh" or open. In a system without using the manual reset function, set the MR pin voltage to "High" or open. (Pull-up resistance: Typ. 100 kΩ) (1) (2) (3) VSENSEn VCDn VDOUTn VMR VOVREL VTCD VUVREL tDELAYn VUVDET tDELAYn VMRL VMRH (1) When inputting “Low” to the MR pin, DOUTn is fixed to "Low" after the manual reset detection delay time (Typ. 20 µs) even if the SENSEn pin voltage (VSENSEn) is within a range of the release voltage. The “Low” signal should be 50 µs or more. (2) When the MR pin transitions from "Low" to "High", DOUTn becomes "H igh" after the release delay time (tDELAYn). At this time, the MR pin should maintain "High" for the release delay time or longer. Even if the external capacitor (CDn capacitance) is not connected, it should maintain "High" for 50 µs or more. (3) When VSENSEn is lower than V UVDETn or higher than V OVDETn, and DOUTn is "L ow", DOUT n does not transition even when the MR pin is set to "Low". Manual Reset Timing Chart

No. EY-521-250725

APPLICATION INFORMATION

Internal Supply Voltage Monitoring with VCCDET The R3500 has a voltage regulator (INT regulator) inside the IC. Major functions of the IC are operated by VCC (Typ. 3.3V) generated by INT regulator from input voltage, VDD. The overvoltage detection circuit, OVLO and the undervoltage detection circuit, U VLO monitor the VCC being within the normal voltage range. When VCC is out of the normal range, NMOS driver connected to VCCDET pin turns on. By pulling up VCCDET pin, when OVLO or UVLO detects an abnormal VCC voltage, the output of VCCDET pin becomes “L”. By monitoring VCC, UVLO also monitors undervoltage of VDD indirectly. Even if pulled up VCCDET pin becomes “L”, the R3500 doesn’t lose the voltage detector function immediately. VCCDET pin should be set to open when it is unused. R3500 Fault Detection Utilizing the Manual Reset Function When a DOUTn pin output is ”H”, it’s very important to know whether it’s a result of normal voltage detector function or malfunction. Utilizing the R3500 manual reset function, one part of IC faults can be detected. By the manual reset function, when “L” signal is input to MR pin, DOUTn pin output is fixed to ”L” forcibly. If DOUTn pin doesn’t become ”L” even though SENSE pin voltage is within the released voltage range and ”L” is input to MR pin, this can be determined as an IC fault. When DOUTn is fixed to ”H” due to an IC fault, DOUTn pin doesn’t become ”L” even "L" signal is input to MR pin. The faults can be detected with the manual reset function of the R3500 by checking DOUTn pin condition as above, are a wire open fault of DOUTn pin or an open fault of the output driver. When detect IC faults with the manual reset function, follow the “Manual Reset Function with MR Pin” noted previously. The system which usually receives output from DOUTn pin should not receive output from DOUTn pin during a fault detection test.

No. EY-521-250725 The concept of “H” level of MR pin The R3500 has a voltage regulator (INT regulator) inside the IC. Major functions of the IC are operated by VCC (Typ. 3.3V) generated by INT regulator from input voltage, VDD. MR pin is pulled up to VCC voltage via 100kΩ as it can be set to open when MR pin is unused. When the manual reset function is in use, when input “L” signal to MR pin, then DOUTn pin becomes “L”. But when the manual reset function is in no use, if “H” voltage is input to MR pin, the current which is determined by the following equation flows continuously. This makes the supply current increase. (VCC – MR ”H” voltage) /100kΩ (VCC＞MR ”H” voltage) Unless there’s a specific reason to avoid an OPEN pin condition, it’s recommended to be left OPEN when MR pin is not used. As the circuit configuration prevents a reverse current from MR pin to VCC, even when being used in condition of MR “H” voltage＞VCC, supply current doesn’t increase and VCC voltage doesn’t vary.

No. EY-521-250725 TYPICAL CHARACTERISTICS Note: Typical Characteristics are intended to be used as reference data; they are not guaranteed. 1) Supply Current vs. Input Voltage VUVSET = 0.97V / VOVSET = 1.04V 2) SENSE Current vs. Input Voltage VUVSET = 3.18V / VOVSET = 3.43V 0 6 12 18 24 30 36 42 Supply Current ISS[uA] Input Voltage VDD [V] -40℃ 25℃ 105℃ 125℃ 0 2 4 6 Supply Current ISS[uA] Input Voltage VDD [V] -40℃ 25℃ 105℃ 125℃ 0.1 0.2 0.3 0.4 0.5 0.6 0.7 ISENSE[uA] Input Voltage VSENSE [V] -40℃ 25℃ 105℃ 125℃

No. EY-521-250725 3) UV / OV Detection・Release Voltage vs. Temperature VDD = 14V, VOVSET = 5.21V / VUVSET = 4.82V VDD = 14V, VOVSET = 3.43V / VUVSET = 3.18V VDD = 14V, VOVSET = 1.87V / VUVSET = 1.74V 4.750 4.770 4.790 4.810 4.830 4.850 4.870 -40 -20 0 20 40 60 80 100 120 VUVDET/VUVREL[V] Ta [℃] UVREL UVDET 5.140 5.150 5.160 5.170 5.180 5.190 5.200 5.210 5.220 -40 -20 0 20 40 60 80 100 120 VOVDET/VOVREL[V] Ta [℃] OVDET OVREL 3.140 3.150 3.160 3.170 3.180 3.190 3.200 -40 -20 0 20 40 60 80 100 120 VUVDET/VUVREL[V] Ta [℃] UVDET UVREL 3.370 3.380 3.390 3.400 3.410 3.420 3.430 3.440 -40 -20 0 20 40 60 80 100 120 VOVDET/VOVREL[V] Ta [℃] OVDET OVREL 1.725 1.730 1.735 1.740 1.745 1.750 1.755 -40 -20 0 20 40 60 80 100 120 VUVDET/VUVREL[V] Ta [℃] UVDET UVREL 1.845 1.850 1.855 1.860 1.865 1.870 1.875 -40 -20 0 20 40 60 80 100 120 VOVDET/VOVREL[V] Ta [℃] OVDET OVREL

No. EY-521-250725 VDD = 14V, VOVSET = 1.04V / VUVSET = 0.97V 4) UV / OV Detection・Release Voltage vs. Input Voltage VDD = 14V, VOVSET = 5.21V / VUVSET = 4.82V VDD = 14V, VOVSET = 3.43V / VUVSET = 3.18V 0.962 0.964 0.966 0.968 0.970 0.972 0.974 0.976 -40 -20 0 20 40 60 80 100 120 VUVDET/VUVREL[V] Ta [℃] UVDET UVREL 1.026 1.028 1.030 1.032 1.034 1.036 1.038 1.040 1.042 -40 -20 0 20 40 60 80 100 120 VOVDET/VOVREL[V] Ta [℃] OVDET OVREL 4.780 4.790 4.800 4.810 4.820 4.830 4.840 4.850 4.860 0 6 12 18 24 30 36 42 VUVDET/VUVREL[V] Input Voltage VDD [V] 5.140 5.150 5.160 5.170 5.180 5.190 5.200 5.210 5.220 0 6 12 18 24 30 36 42 VOVDET/VOVREL[V] Input Voltage VDD [V] 3.160 3.165 3.170 3.175 3.180 3.185 3.190 3.195 3.200 0 6 12 18 24 30 36 42 VUVDET/VUVREL[V] Input Voltage VDD [V] 3.390 3.395 3.400 3.405 3.410 3.415 3.420 3.425 3.430 3.435 0 6 12 18 24 30 36 42 VOVDET/VOVREL[V] Input Voltage VDD [V]

No. EY-521-250725 VDD = 14V, VOVSET = 1.87V / VUVSET = 1.74V VDD = 14V, VOVSET = 1.04V / VUVSET = 0.97V 5) DOUT Pin Voltage vs. Input Voltage VSENSE = (VOVSET+VUVSET)/2, Pull-up Voltage = 5V 1.725 1.730 1.735 1.740 1.745 1.750 0 6 12 18 24 30 36 42 VUVDET/VUVREL[V] Input Voltage VDD [V] 1.852 1.854 1.856 1.858 1.860 1.862 1.864 1.866 1.868 1.870 1.872 0 6 12 18 24 30 36 42 VOVDET/VOVREL[V] Input Voltage VDD [V] 0.964 0.966 0.968 0.970 0.972 0.974 0.976 0 6 12 18 24 30 36 42 VUVDET/VUVREL[V] Input Voltage VDD [V] 1.026 1.028 1.030 1.032 1.034 1.036 1.038 1.040 1.042 0 6 12 18 24 30 36 42 VOVDET/VOVREL[V] Input Voltage VDD [V] 0 2 4 6 8 10 12 14 VDOUT2 [V] VDD [V]

No. EY-521-250725 6) DOUT Pin Voltage vs. SENSE Pin Voltage VUVSET = 4.82V / VOVSET = 5.21V, VUVSET = 0.97V / VOVSET = 1.04V, Pull-up Voltage = 5V 7) Driver Output Current vs. Input Voltage VSENSE = 0V, VDOUT2 = 0.1V 8) Driver Output Current vs. VDS VSENSE = 0V, VDOUT1/4 = 0V → 14V DOUT1 DOUT4 VDOUT [V] VSENSE [V] VDOUT1 VDOUT4 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 6 12 18 24 30 36 42 Driver Output Current[mA] Input Voltage VDD [V] -40℃ 25℃ 105℃ 125℃ 0 2 4 6 8 10 12 14 Driver Output Current[mA] VDS [V] VDD=2.9V VDD=14V VDD=42V 0 2 4 6 8 10 12 14 Driver Output Current[mA] VDS [V] VDD=2.9V VDD=14V VDD=42V

No. EY-521-250725 9) Release Delay Time vs. Temperature VSENSE = 0V → (VUVSET + VOVSET)/2 (UV) VSENSE = 5.5V → (VUVSET + VOVSET)/2 (OV), CD = 10nF 10) Release Delay Time vs. Input Voltage CD = 10nF UV Release OV Release 11) Release Delay Time vs. External Capacitor for CD Pin VDD = 14V 3.0 3.5 4.0 4.5 5.0 5.5 -40 -20 0 20 40 60 80 100 120 Output delay time for Release[ms] Ta [℃] UV Release OV Release 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 6 12 18 24 30 36 42 Output delay time for Release[ms] Input Voltage VDD [V] -40℃ 25℃ 105℃ 125℃ 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 6 12 18 24 30 36 42 Output Delay time for Release[ms] Input Voltage VDD [V] -40℃ 25℃ 105℃ 125℃ 0.001 0.01 0.1 100 1000 0.001 0.01 0.1 1 10 100 1000 Output Delay time for Release[ms] CD[nF] UV Release OV Release

No. EY-521-250725 12) Detection Delay Time vs. Temperature VDD = 14V, VSENSE = (VUVSET + VOVSET)/2 → 0V (UV), VSENSE = (VUVSET + VOVSET)/2 → 5.5V (OV) VSENSE=(VUVSET +VOVSET)/2→VUVSET×0.97V(UV), VSENSE=(VUVSET + VOVSET)/2→VOVSET×1.03V(OV) 13) SENSE Pulse Width vs. Over Drive Voltage VDD = 14V, VSENSE = (VUVSET+VOVSET)/2 → (VUVSET -Over Drive Voltage) (UV), VSENSE = (VUVSET+VOVSET)/2 → (VOVSET +Over Drive Voltage) (OV) -40 -20 0 20 40 60 80 100 120 Output Delay time for Reset[μs] Ta[℃] OV Detection UV Detection -40 -20 0 20 40 60 80 100 120 Output Delay time for Reset[μs] Ta [℃] OV Detection UV Detection 100 120 140 10 100 1000 Pulse Width [μs] Over Drive Voltage [mV] UV OV Occurrence of reset signal in the area crossing OV and UV thresholds

PD-HSOP-18-(125150)-JE-B i The power dissipation of the package is dependent on PCB material, layout, and environmental conditions. The following measurement conditions are based on JEDEC STD. 51-7. Measurement Conditions Item Measurement Conditions Environment Mounting on Board (Wind Velocity = 0 m/s) Board Material Glass Cloth Epoxy Plastic (Four-Layer Board) Board Dimensions 76.2 mm × 114.3 mm × 0.8 mm Copper Ratio Outer Layer (First Layer): Less than 95% of 50 mm Square Inner Layers (Second and Third Layers): Approx. 100% of 50 mm Square Outer Layer (Fourth Layer): Approx. 100% of 50 mm Square Through-holes  0.3 mm × 21 pcs Measurement Result (Ta = 25°C, Tjmax = 150°C) Item Measurement Result Power Dissipation 3900 mW Thermal Resistance (ja) ja = 32°C/W Thermal Characterization Parameter (ψjt) ψjt = 8°C/W ja: Junction-to-Ambient Thermal Resistance ψjt: Junction-to-Top Thermal Characterization Parameter Power Dissipation vs. Ambient Temperature Measurement Board Pattern 500 1000 1500 2000 2500 3000 3500 4000 0 25 50 75 100 125 150 Power Dissipation PD (mW) Ambient Temperature (°C) 3900

PACKAGE DIMENSIONS HSOP-18 i DM-HSOP-18-JE-B

i : Product Code … Refer to Part Marking List : Lot Number … Alphanumeric Serial Number R3500S (HSOP-18) Part Markings NOTICE There can be variation in the marking when different AOI (Automated Optical Inspection) equipment is used. In the case of recognizing the marking characteristic with AOI, please contact our sales or distributor before attempting to use AOI. R3500S Part Marking List R3500S001A RS13 8 A Lot. No. R3500S002A RS138B Lot. No. R3500S003A RS138 C Lot. No. R3500S004A RS138D Lot. No. R3500S005A RS138E Lot. No. R3500S006A RS138 F Lot. No. R3500S007A RS138 G Lot. No. R3500S008A RS138H Lot. No. R3500S009A RS138 J Lot. No. R3500S010A RS138K Lot. No. R3500S011A RS138L Lot. No. R3500S012A RS13 8 M Lot. No. R3500S013A RS13 8 N Lot. No.

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