R3200X NISSHINBO | Alldatasheet

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Reset Timer IC for Mobile Equipments NO.EA-280-230523 OUTLINE The R3200x is a reset timer IC with two input signals for mobile equipment which require long interval for reset sequence. The long interval prevents unexpected resets caused by accidental key operations. Internally, the R3200x consists of a delay generator circuit and output driver transistors. The R3200x has two active-low input pins (SR0 and SR1) which generate reset signals after output delay time when both active-low input pins are activated at the same time. The R3200x has two versions that are different in output delay time settings and output release method. R3200x001x: Output delay time is selectable from 7.5 s or 11.25 s typ. by connecting the DSR pin to either GND or V DD. A reset signal can be released by making one of the active-low input pins high. R3200xxx2x, R3200L053B or R3200L064A: Output delay time is fixed. A reset signal will be released automatically after output release time. Or, by making one of the active-low input pins high, a reset signal can be released before output release time. The R3200x provides ultra-low supply current while a reset signal is remaining active or after being sent out. The R3200x is offered in a 8-pin DFN(PL)2020-8B package or a 8-pin DFN1216-8 package.

NO.EA-280-230523

FEATURES

*1 Guaranteed by design engineering

APPLICATIONS

  • Mobile phone, Smartphone
  • Tablet devices such as E-book etc.
  • Portable Games
  • Personal Navigation Devices

NO.EA-280-230523 BLOCK DIAGRAMS SR1 RST SR0 VDD Delay Logic DSR Reset Logic Delay Time Selector OSC GND SR1 RST SR0 VDD Delay Logic DSR Reset Logic Delay Time Selector OSC RST2 GND R3200xxxxA R3200xxxxB *1 The parts surrounded by red dotted lines are for the R3200x001x only. SELECTION GUIDE The package type, the combination of output delay time and output release time, the output type for the device are user-selectable options. Selection Guide Product Name Package Quantity per Reel Pb Free Halogen Free R3200Kxxx∗-TR DFN(PL)2020-8B 5,000 pcs Yes Yes R3200Lxxx∗-E2 DFN1216-8 5,000 pcs Yes Yes xxx: Specify the combination of output delay time and output release method. (001) Select the output delay time from 7.5 s or 11.25 s typ. A reset signal can be released by making one of the active-low input pins high. A reset signal will be released automatically after output release time. A reset signal can be released before output release time by making one of the active- low input pins high. Refer to the table below for the output delay time and the output release time for each device. Output Delay Time Output Release Time 002 7.5 s 0.234 s 052 (R3200L052B only) 10 s 0.313 s 053 (R3200L053B only) 10 s 0.078 s 064 (R3200L064A only) 3.0 s 0.1875 s ∗: Specify the output type. (A) Nch Open Drain (B) Nch Open Drain and CMOS

NO.EA-280-230523 PIN DESCRIPTIONS Top View 8 7 6 1 2 3 4 Bottom View 5 6 7 3 2 1 4 Top View 8 7 6 1 2 3 4 Bottom View 5 6 7 3 2 1 4 DFN(PL)2020-8B DFN1216-8 ∗ The tab on the bottom of the package enhances thermal performance and is electrically connected to GND (substrate level). It is recommended that the tab be connected to the ground plane on the board, or otherwise be left floating. DFN(PL)2020-8B Pin Description/ DFN1216-8 Pin Description Pin No. Symbol Description NC No Connection (R3200xxxxA) RST2 CMOS Output Pin, Active-high (R3200xxxxB)

2 GND Ground Pin

3 SR1

Input Pin2, Active-low*1

4 RST

Nch Open Drain Output Pin, Active-low*2 DSR Output Delay Time Selection Pin (R3200x001x) (GND: 7.5 s, VDD: 11.25 s)*3 TEST2 Test Pin 2*4 (R3200xxx2x/ R3200L053B/ R3200L064A)

6 TEST Test Pin*4

7 SR0

Input Pin1, Active-low*1

8 VDD Power Supply Input Pin

*1 When only one active-low input pin is used, connect the unused one to GND. *2 The RST pin must be connected to GND or left floating if it is not used (Ex.R3200xxxxB). *3 The DSR pin must be connected to GND or VDD. *4 The TEST pin and the TEST2 pin must be connected to GND when they are used.

NO.EA-280-230523 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings Symbol Item Rating Unit VDD Supply Voltage GND −0.3 to 6 V VSR0 Input Voltage (Input Pin1) GND −0.3 to 6 V VSR1 Input Voltage (Input Pin2) GND −0.3 to 6 V VRST Output Voltage (Reset Signal Output Pin1) GND −0.3 to 6 V VRST2 Output Voltage (Reset Signal Output Pin2) GND −0.3 to VDD +0.3 V VDSR Input Voltage (Output Delay Time Selection Pin) (R3200x001x) GND −0.3 to 6 V IOUT Output Current 20 mA PD Power Dissipation (JEDEC STD. 51)*1 DFN(PL)2020-8B 1050 mW DFN1216-8 1700 Ta Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −55 to +125 °C *1 Refer to PACKAGE INFORMATION for detailed information. ABSOLUTE MAXIMUM RATINGS Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause permanent damage and may degrade the life time and safety for both device and system using the device in the field. The functional operation at or over these absolute maximum ratings is not assured. RECOMMENDED OPERATING CONDITIONS (ELECTRICAL CHARACTERISTICS) All of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating conditions. The semiconductor devices cannot operate normally over the recommended operating conditions, even if they are used over such conditions by momentary electronic noise or surge. And the semiconductor devices may receive serious damage when they continue to operate over the recommended operating conditions.

NO.EA-280-230523

ELECTRICAL CHARACTERISTICS

The specifications surrounded by are guaranteed by design engineering at −40°C ≤ Ta ≤ 85°C. R3200x001x Electrical Characteristics (Ta = 25°C) Symbol Item Conditions Min. Typ. Max. Unit VDD Supply Voltage 1.65 5.5 V ISS1 Supply Current 1*1 VDD = 5.5 V (at standby) 0.28 1.35 µA ISS2 Supply Current 2*2 VDD = 5.5 V (at active before reset signal output) 3.0 6.5 µA ISS3 Supply Current 3*3 VDD = 5.5 V (at active after reset signal output) 0.45 1.7 µA VOL "L" Output Voltage VDD ≥ 4.5 V IOL = 8 mA 0.3 V VDD ≥ 3.3 V IOL = 5 mA VDD ≥ 1.65 V IOL = 3 mA VOH "H" Output Voltage*4 VDD ≥ 4.5 V IOH = 5 mA VDD x 0.85 V VDD ≥ 3.3 V IOH = 2.5 mA VDD ≥ 1.65 V IOH = 0.8 mA ILEAKI SR0 , SR1 Input Leakage Current VDD = 5.5 V 0.1 µA ILEAKO Output Leakage Current VDD = 5.5 V 0.1 µA tdelay Output Delay Time DSR = GND 6.75 7.5 8.25 s DSR = VDD 10.125 11.25 12.375 s VIL SR0 , SR1 "L" Input Voltaget 0.3 V VIH SR0 , SR1 "H" Input Voltaget 0.85 V All test items listed under ELECTRICAL CHARACTERISTICS are done under the pulse load condition (Tj ≈ Ta = 25°C) except Supply Current 2. *1 Supply current when the device is active and waiting for the reset input. *2 Supply current when both active-low input pins are low and the timer operation is running. *3 Supply current after the completion of timer operation and the output of reset signal. *4 For the R3200xxxxB only (CMOS output).

NO.EA-280-230523 ELECTRICAL CHARACTERISTICS (continued) The specifications surrounded by are guaranteed by design engineering at −40°C ≤ Ta ≤ 85°C. R3200xxx2x, R3200L053B, R3200L064A Electrical Characteristics (Ta = 25°C) Symbol Item Conditions Min. Typ. Max. Unit VDD Operating Voltage 1.65 5.5 V ISS1 Supply Current 1*1 VDD = 5.5 V (at standby) 0.28 1.35 µA ISS2 Supply Current 2*2 VDD = 5.5 V (at active before reset signal output) 3.0 6.5 µA ISS3 Supply Current 3*3 VDD = 5.5 V (at active after reset signal output) 0.45 1.7 µA VOL "L" Output Voltage VDD ≥ 4.5 V IOL = 8 mA 0.3 V VDD ≥ 3.3 V IOL = 5 mA VDD ≥ 1.65 V IOL = 3 mA VOH "H" Output Voltage*4 VDD ≥ 4.5 V IOH = 5 mA VDD x 0.85 V VDD ≥ 3.3 V IOH = 2.5 mA VDD ≥ 1.65 V IOH = 0.8 mA ILEAKI SR0 , SR1 Input Leakage Current VDD = 5.5 V 0.1 µA ILEAKO Output Leakage Current VDD = 5.5 V 0.1 µA tdelay Output Delay Time*5 tdelay_s x 0.9 tdelay_s tdelay_s x 1.1 sec trec Output Release Time*5 trec_s x 0.9 trec_s trec_s x 1.1 sec VIL SR0 , SR1 "L" Input Voltage 0.3 V VIH SR0 , SR1 "H" Input Voltage 0.85 V All test items listed under ELECTRICAL CHARACTERISTICS are done under the pulse load condition (Tj ≈ Ta = 25°C) except Supply Current 2. *1 Supply current when the device is active and waiting for the reset input. *2 Supply current when both active-low input pins are low and the timer operation is running. *3 Supply current after the automatic cancellation of reset signal following the completion of timer operation and the output of rest signal. *4 For the R3200xxxxB only (CMOS output). *5 Refer to Output Delay Time and Output Release Time of R3200x. Output Delay Time and Output Release Time of R3200x Product Name tdelay_s trec_s R3200x002x 7.5 s 0.234 s R3200L052B 10 s 0.313 s R3200L053B 10 s 0.078 s R3200L064A 3.0 s 0.1875 s

NO.EA-280-230523 TYPICAL APPLICATIONS VDD RESET CPU GND 470kΩ VDD R3200xxxxA RST DSR/TEST2 Power On SR0 TEST SR1 GND C Power Switch Power Supply R3200xxxxA Typical Application VDD RESET CPU GND VDD RST2 R3200xxxxB RST DSR/TEST2 Power On1 SR0 TEST SR1 GND C Power Switch Regulator CE System Power Output Power Supply Power Switch Power On0 R3200xxxxB Typical Application A bypass capacitor between the power supply line and the GND line is not necessarily required. If the device operation is affected by power supply noise, connect an appropriately selected bypass capacitor.

NO.EA-280-230523 TECHNICAL NOTES The performance of power source circuits using th is device largely depends on the peripheral circuits. When selecting the peripheral components, consider the condition s of use. Do not allow each component, PCB pattern and the device to exceed their respected rated values (voltage, current and power) when designing the peripheral circuits.

  • When only one active-low input pins is used (refer to R3200xxxxA Typical Application) connect the unused one to GND.
  • In the case of applying the following circuit configuration to the R3200x, the supply current of the device itself may cause significant voltage drop on the V DD pin if the R1 value is high. As a result, the VDD voltage may fall below the minimum operating voltage. RST2 GND VDD Power Supply RST Circuit Configuration Example

NO.EA-280-230523 THEORY OF OPERATION 1.65V Timer End *1 For R3200xxxxB only. VDD VSR0 VSR1 VRST VRST2*1 Timer Start Timer Start Timer Stop tDELAY Reset off Reset Reset off Reset R3200x001x Timing Chart

  • When both active-low input pins become the low voltage level, the timer operation starts. After the output delay time (tdelay), a reset signal will be sent out. When one of the active- low input pins becomes the high voltage level, the timer operation stops.
  • During tdealy, if one of the active-low input pins becomes the high voltage level, the timer operation stops. If both active-low input pins become the low voltage level again, a reset signal will be sent out after tdelay.
  • A reset signal will be released if one of the active-low input pins becomes the high voltage level. Until one of the active-low input pins becomes the high voltage level, a reset signal will be continually sent out .
  • tdelay can be selected from 7.5 s or 11.25 s typ. by connecting the DSR pin to either GND or VDD. However, if the DSR pin is switched during the operations, the output would become unstable and may cause false operations. Switching of the DSR pin must be done during power-off. Also, the DSR pin must be connected to either GND or VDD, otherwise the output would become unstable and may cause false operations.

NO.EA-280-230523 1.65V Timer End Reset off VDD VSR0 VSR1 VRST VRST2*1 Timer Start Timer Start Timer Stop tDELAY tREC Reset Timer Start tDELAY tREC Reset Reset off Timer End Reset off Reset Reset Reset off *1 For R3200xxxxB only. R3200xxx2x, R3200L053B, R3200L064A Timing Chart

  • When both active-low input pins become the low voltage level, the timer operation starts. After the output delay time ( tdelay), a reset signal will be sent out. If one of the active- low input pins becomes the high voltage level, the timer operation stops.
  • During tdelay, if one of the active-low input pins becomes the high voltage level, the timer operation stops. If both active-low input pins become the low voltage level again, a reset signal will be sent out after tdelay.
  • A reset signal will be released automatically after the reset delay time (trec), or it will be released if one of the active-low input pins becomes the high voltage level.

NO.EA-280-230523 OUTPUT DELAY TIME GAP The threshold voltages of the active-low input pins are between VIL and VIH. Therefore, if the rising or falling slew rate is very slow, the timer will start at the point of crossing the threshold voltage and may cause errors in the output delay time (tdelay) and the output release time (trec). VIH=0.85V VIL=0.3V VDET_L VDET_H Output Delay Time Gap Output Delay Time Released Reset Time Gap VRST VSR0, VSR1 Relation between the Rising and Falling Slew Rate and the Time Gap VDD START-UP DURING LOW INPUT When starting up VDD at slow slew rate of 0.001 V/µs or less while the active-low input pins are the low voltage level, the device may start the operation at lower than the minimum operating voltage, thus tdelay may exceed the guaranteed time.

NO.EA-280-230523

PACKAGE INFORMATION

Power Dissipation (DFN(PL)2020-8B) The power dissipation of the package is dependent on PCB material, layout, and environmental conditions. The following measurement conditions are based on JEDEC STD. 51-7. Measurement Conditions Item Measurement Conditions Environment Mounting on Board (Wind Velocity = 0 m/s) Board Material Glass Cloth Epoxy Plastic (Four-Layer Board) Board Dimensions 76.2 mm × 114.3 mm × 0.8 mm Copper Ratio Outer Layer (First Layer): Less than 95% of 50 mm Square Inner Layers (Second and Third Layers): Approx. 100% of 50 mm Square Outer Layer (Fourth Layer): Approx. 100% of 50 mm Square Through-holes φ 0.3 mm × 23 pcs Measurement Result (Ta = 25°C, Tjmax = 125°C) Item Measurement Result Power Dissipation 1050 mW Thermal Resistance (θja) θja = 92°C/W Thermal Characterization Parameter (ψjt) ψjt = 60°C/W θja: Junction-to-Ambient Thermal Resistance ψjt: Junction-to-Top Thermal Characterization Parameter Power Dissipation vs. Ambient Temperature Measurement Board Pattern 200 400 600 800 1000 1200 0 25 50 75 100 125 Power Dissipation (mW) Ambient Temperature (°C) 1050

NO.EA-280-230523 PACKAGE DIMENSIONS (DFN(PL)2020-8B) DFN(PL)2020-8B Package Dimensions MARK SPECIFICATION (DFN(PL)2020-8B) : Product Code … Refer to MARK SPECIFICATION TABLE (DFN(PL)2020-8B). : Lot Number … Alphanumeric Serial Number DFN(PL)2020-8B Mark Specification 2.00 2.00 A B 0.05 INDEX 0.6max

0.05 S S

0.05min 0.55±0.05 0.5 1.3±0.05 0.20±0.05 0.35±0.05 C0.05 (Unit: mm) Bottom View ∗ The tab on the bottom of the package enhances thermal performance and is electrically connected to GND (substrate level). It is recommended that the tab be connected to the ground plane on the board, or otherwise be left floating.

0.05 M AB

 

NO.EA-280-230523 MARK SPECIFICATION TABLE (DFN(PL)2020-8B) R3200K Mark Specification Table Product Name  R3200K001A D 0 0 1 R3200K001B D D 0 2 R3200K002A D D 0 3 R3200K002B D D 0 4

NO.EA-280-230523 Power Dissipation (DFN1216-8) The power dissipation of the package is dependent on PCB material, layout, and environmental conditions. The following conditions are based on JEDEC STD. 51-7. Measurement Conditions Item Measurement Conditions Environment Mounting on Board (Wind Velocity = 0 m/s) Board Material Glass Cloth Epoxy Plastic (Four-Layer Board) Board Dimensions 76.2 mm × 114.3 mm × 0.8 mm Copper Ratio Outer Layer (First Layer): Less than 95% of 50 mm Square Inner Layers (Second and Third Layers): Approx. 100% of 50 mm Square Outer Layer (Fourth Layer): Approx. 100% of 50 mm Square Through-holes φ 0.2 mm × 25 pcs Measurement Result (Ta = 25°C, Tjmax = 125°C) Item Measurement Result Power Dissipation 1700 mW Thermal Resistance (θja) θja = 56°C/W Thermal Characterization Parameter (ψjt) ψjt = 18°C/W θja: Junction-to-Ambient Thermal Resistance ψjt: Junction-to-Top Thermal Characterization Parameter Power Dissipation vs. Ambient Temperature Measurement Board Pattern 200 400 600 800 1000 1200 1400 1600 1800 2000 0 25 50 75 100 125 Power Dissipation (mW) Ambient Temperature (°C) 1700

NO.EA-280-230523 PACKAGE DIMENSIONS (DFN1216-8) MARK SPECIFICATION (DFN1216-8) : Product Code … Refer to MARK SPECIFICATION TABLE (DFN1216-8). : Lot Number … Alphanumeric Serial Number DFN1216-8 Mark Specification 8 5 0.20±0.05 C0.15 1.30±0.05 0.40 0.18±0.05 0.05 M AB 0.05 1.20 1.60 A B 0.05 INDEX S 0.05 S 0.4max (Unit: mm) Bottom View ∗ The tab on the bottom of the package enhances thermal performance and is electrically connected to GND (substrate level). It is recommended that the tab be connected to the ground plane on the board, or otherwise be left floating.  

NO.EA-280-230523 MARK SPECIFICATION TABLE (DFN1216-8) R3200L Mark Specification Table Product Name  R3200L001A D E 0 1 R3200L001B D F 0 2 R3200L002A D E 0 3 R3200L002B D E 0 4 R3200L052B D E 0 5 R3200L053B D E 0 6 R3200L064A D E 0 7

NO.EA-280-230523 TEST CIRCUITS RST2 GND DSR/TEST2 TEST VDD ISS1 SR1 RST SR0 470kΩ RST2 GND DSR/TEST2 TEST VDD SR0 SR1 RST Supply Current Test Circuit Output Delay Time Test Circuit IOUT VOL RST2 GND DSR/TEST2 TEST VDD SR1 RST SR0 VOH IOUT RST2 GND DSR/TEST2 TEST VDD SR1 RST SR0 Nch Driver Output Voltage Test Circuit CMOS Driver Output Voltage Test Circuit (For the R3200xxxxB only.)

NO.EA-280-230523 TYPICAL CHARACTERISTICS Note: Typical Characteristics are intended to be used as reference data; they are not guaranteed. 1) Supply Current 1 vs. Temperature 2 ) Supply Current 2 vs. Temperature R3200x (at standby) R3200x ( before the reset signal output) 3) Supply Current 3 vs. Temperature 4 ) Supply Current 1 vs. Supply Voltage R3200x (after the reset signal output) R3200x (at standby) 5) Supply Current 2 vs. Supply Voltage 6 ) Supply Current 2 vs. Supply Voltage R3200x (before the reset signal output) R3200x (after the reset signal output) 0.2 0.4 -50 -25 0 25 50 75 100 Temperature Topt (゜C) Supply Current ISS1 (uA) VDD=5.5V VDD=3.3V VDD=1.65V -50 -25 0 25 50 75 100 Temperature Topt (゜C) Supply Current ISS2 (uA) VDD=5.5V VDD=3.3V VDD=1.65V 0.2 0.4 0.6 0.8 -50 -25 0 25 50 75 100 Temperature Topt (゜C) Supply Current ISS3 (uA) VDD=5.5V VDD=3.3V VDD=1.65V 0.2 0.4 0.6 1 2 3 4 5 6 Supply Voltage VDD (V) Supply Current ISS1 (uA) Topt = 85℃ Topr = 25℃ Topt = -40℃ 1 2 3 4 5 6 Supply Voltage VDD (V) Supply Current ISS2 (uA) Topt = 85℃ Topr = 25℃ Topt = -40℃ 0.3 0.6 1 2 3 4 5 6 Supply Voltage VDD (V) Supply Current ISS3 (uA) Topt = 85℃ Topr = 25℃ Topt = -40℃

NO.EA-280-230523 7) Output Delay Time vs. Temperature R3200x001x R3200x001x 8) Output Release Time vs. Temperature R3200x002x R3200x002x 9) Output Delay Time vs. Supply Voltage R3200x001x R3200x001x 7.3 7.4 7.5 7.6 7.7 -50 -25 0 25 50 75 100 Temperature Ta (゜C) Reset Delay Time tDELAY (s) VDD=5.5V VDD=3.3V VDD=1.65V 10.90 11.05 11.20 11.35 11.50 -50 -25 0 25 50 75 100 Temperature Ta (゜C) Reset Delay Time tDELAY (s) VDD=5.5V VDD=3.3V VDD=1.65V 7.3 7.4 7.5 7.6 7.7 -50 -25 0 25 50 75 100 Temperature Topt (゜C) Reset Delay Time tDELAY (s) VDD=5.5V VDD=3.3V VDD=1.65V 0.225 0.230 0.235 0.240 0.245 -50 -25 0 25 50 75 100 Temperature Topt (゜C) Reset Release Time t REC (s) VDD=5.5V VDD=3.3V VDD=1.65V 7.3 7.4 7.5 7.6 7.7 1 2 3 4 5 6 Supply Voltage VDD (V) Reset Delay Time tDELAY (s) Topt = -40℃ Topt = 25℃ Topt = 85℃ 10.90 11.05 11.20 11.35 11.50 1 2 3 4 5 6 Supply Voltage VDD (V) Reset Delay time tDELAY (s) Topt = -40℃ Topt = 25℃ Topt = 85℃ DSR = GND (tdelay: Typ. 7.5 s) DSR = VDD (tdelay: Typ. 11.25 s) DSR = GND (tdelay: Typ. 7. 0 DSR = VDD (tdelay: Typ. 11.25 s)

NO.EA-280-230523 10) Output Release Time vs. Supply Voltage R3200x002x R3200x002x 11) Nch Driver Output Current vs. Supply Voltage 12) Nch Driver Output Current vs. V DS VDS = 0.3 V 1 2 3 4 5 6 Output Current IOUT (m A) Supply Voltage VDD (V) Topt = -40℃ Topt = 25℃ Topt = 85℃ VDS (V) Output Current IOUT (mA) VDD=5.5V VDD=4.5V VDD=3.5V VDD=2.5V VDD=1.65V 13) Pch Driver Output Current vs. Supply Voltage 14) Pch Driver Output Current vs. V DS V DS = 0.9 V 1 2 3 4 5 6 Output Current IOUT (m A) Supply Voltage VDD (V) Topt = -40℃ Topt = 25℃ Topt = 85℃ Output Current IOUT (m A) VDS (V) VDD=5.5V VDD=4.5V VDD=3.5V VDD=2.5V VDD=1.65V 7.3 7.4 7.5 7.6 7.7 1 2 3 4 5 6 Supply Voltage VDD (V) Reset Delay Time tDELAY (s) Topt = 85℃ Topt = 25℃ Topt = -40℃ 0.220 0.225 0.230 0.235 0.240 1 2 3 4 5 6 Supply Voltage VDD (V) Reset Release Time t REC (s) Topt = 85℃ Topt = 25℃ Topt = -40℃

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