PEB2023 SIEMENS | Alldatasheet
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PEB 2023 Version 1.1 PEF 2023 Version 1.1 Data Sheet 08.97 DS 2
Edition 08.97 This edition was realized using the software system FrameMaker . Published by Siemens AG, HL TS, Balanstraße 73,
81541 München
© Siemens AG 08.1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components 1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu- man life. If they fail, it is reasonable to assume that the health of the user may be endangered. PEB 2023 PEF 2023 Revision History: Original Version: Data Sheet 08.97 Previous Releases: Data Sheet 02.97 Page Subjects (changes since last revision) all Pages Additional to the normal temperature range devices PEB 2023 also the extended temperature range devices PEF 2023 are specified in this Data Sheet.
21 The ambient temperature under bias is separately defined for PEB 2023 and PEF
2023.
22 The maximum limit values for line regulation VREF Line and load regulation VREF Load
are reduced. The typical values are adapted. 22 The maximum limit value for voltage stability of fOSC is reduced. The typical value is adapted.
22 The test condition ambient temperature range TA is extended for temperature
stability of VREF and fOSC .
23 The sense voltage VSense of the current limit comperator is separately defined for
PEB 2023 and PEF 2023.
Semiconductor Group 3 08.97
Semiconductor Group 4 08.97 PEB 2023 PEF 2023 Overview
1 Overview
The PEB/F 2023 is a pulse width modulator circuit designed for fixed-frequency switching regulators with very low power consumption. In telephone and ISDN-systems a high conversion yield is crucial to maintain functionality in all supply conditions via S- or U-interfaces. The PEB/F 2023 design and technology realizes high conversion efficiency and low power dissipation. The PEB/F 2023 is fully compatible with the ITU-power recommendations of the S-interface. For these reasons the PEB/F 2023 is especially suited for telephone and ISDN- environments. Coupled with a few external components it can provide a stable 5V DC-supply for subscriber terminals (TE’s) or network terminators (NT’s). It can additionally be programmed for higher output voltages, e.g. to supply the S-lines. It should be recognized that the PEB/F 2023 can also be used in numerous DC/DC- conversion systems other than ISDN-power supplies. For example, in a special supply voltage range the PEB/F 2023 can be supplied from a 12V battery. For detailed technical information about "Processing Guidelines" and "Quality Assurance" for ICs, see our "Product Overview".
Semiconductor Group 5 08.97 ISDN DC Converter Circuit IDCC PEB 2023 PEF 2023 Data Sheet SPT 75 R Type Ordering Code Package PEB 2023 Q67100-H6830 P-DSO-14 PEF 2023 Q67220-H1059 P-DSO-14
1.1 Features
- Switched Mode DC/DC Converter
- ITU ISDN Compatible
- Low Power Dissipation
- Supply Voltage Range 0: 8V to 16V Supply Voltage Range 1: 12V to 80V Supply Voltage Range 2: 22V to 90V (pin striping selects between range 1 and range 2) Supply Voltage Range 3, with shifting by an external zener diode: U ZD +8V to UZD +90V (minimum zener voltage UZD = 14V)
- Programmable Overcurrent Protection
- Soft Start
- Power Housekeeping Input
- Input Undervoltage Detection
- High Input Impedance (<10µA) During Undervoltage Condition
- Oscillator Synchronization Input/Output
- High Voltage Smart Power Technology 75V
- P-DSO-14/1 Package
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1.2 Pin Configuration
(top view) P-DSO-14 GND VEXT IP VREF VS SYNC RC COMP GA VP VN UVx CSS UV IDCC PEB 2023 PEF 2023
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1.3 Pin Definitions and Functions
Pin No. Symbol Input (I) Output (O) Function 1 V REF O Output of the 4V reference voltage.
2 IP I When the voltage difference between IP and GND
exceeds 100mV, the digital current limiting becomes active and turns off the external FET for the rest of this oscillator period. 3 GND I All analog and digital signals are referred to this pin. 4 GA O Output of the FET-driver. 5 V EXT I/O Output of the internal supply. Via VEXT the internal low-voltage-circuits can be supplied from an external DC-supply in order to reduce chip power dissipation. In supply voltage range 0 the positive supply voltage must be connected via a resistor to this pin. C SS I The capacitor at this pin determines the soft-start characteristic.
7 V S I VS is the positive input voltage for supply voltage
range 1, 2 and 3. Must be connected to GND via a resistor when using supply voltage range 0.
8 COMP O Error amplifier output and Pulse W idth M odulator
(PWM) input for loop stabilization network. V P I Non-inverting input of the error amplifier. 10 V N I Inverting input of the error amplifier. 11 UV I Input undervoltage lockout. The input undervoltage lockout level depends on the used supply voltage range. Must be connected to pin V S when using supply voltage range 0.
12 UVx I If this pin is connected to UV, then supply range 1 is
selected. If this pin is not connected (floating), then supply range 2 or supply range 3 can be used. Must be connected to pin VEXT when using supply voltage range 0.
13 SYNC I/O Input for synchronization of the oscillator to an
external frequency, or output to synchronize multiple devices.
14 RC I The external timing components of the ramp
generator are attached to this pin.
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1.4 Functional Block Diagram
VOLTAGEREFERENCEUNDER-VOLTAGEDETECTION CONTROL LOGIC PWM 9.4 V S VEXT COMP SYNC RCSAWTOOTHOSCILLATOR ERRORAMPL. IP CURRENT LIMITING 100 mV GA VP VN UVxUV VREF OUTPUT DRIVER SOFTSTART C SS SUPPLY AND BIASING
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1.5 System Integration
Figure 2 and 3 showing examples out of the wide application field of the PEB/F 2023. In network termination applications, the PEB/F 2023 supplies the internal IC’s directly from the U–interface. If the local main supply of the NT is out of order, then the PEB/F 2023 will also supplies the S-interface (restricted power mode). In the subscriber terminal the PEB/F 2023 is used for feeding the internal circuits. The PEB/F 2023 accommodates both galvanically isolated and non-isolated configurations. Considering the diversity of DC/DC-converter applications, this part of the specification only shows how to use the special ISDN-features of the PEB/F 2023. Figure 2 PEB/F 2023 in ISDN-Concept U Transceiver S Transceiver HDLC Controller DC/DC Converter PEB 2023 PEF 2023 AC/DC Converter CODEC Interface AC 230V40VNPM 40VRPM µ.C. reverse Polarity Current Limiter Current Limiter S U
Semiconductor Group 10 08.97 In figure 3 the S-transformers are replaced by the PEB/F 3023 which is called S-Feeder. When using the S-Feeder a capacitive coupling between S-receive-path and the S- Transceiver is necessary. For the S-transmit-path the S-Feeder need an extra 2.4V transmitter supply voltage. Because of the DC-voltage-drop on the S-Feeder (about 2V and 4V) the input voltages V RPM and VNPM must be increased (to about 42V and 44V). Figure 3 PEB/F 2023 in ISDN-Concept U Transceiver S Transceiver HDLC Controller DC/DC Converter PEB 2023 PEF 2023 AC/DC Converter CODEC Interface AC 230V44VNPM 40VRPM µ.C. S Feeder PEB 3023 2.4V reverse Polarity Current Limiter Current Limiter Reset Generator S U
Semiconductor Group 13 08.97 For calculation of resistor R7: VIN, input voltage : VINmin = 8V, V INmax = 16V VEXT :V EXTmin = 6V, V EXTmax = 9V IR7 , input current : IR7min = 1mA, I R7max = 6mA To get lower power dissipation the value of resistor R7 should also be as high as possibile. For this reason we use R7max . If in the calculation above R7min is higher than R 7max , then the input voltage range is not correct; VINmax -VINmin is too large. Note: If VINmin = 6V and VINmax = 9V then the resistor R7 is not necessary. The input voltage VIN can directly be connected to VEXT . Figure 6 PEB/F 2023 in a non-isolated Flyback Configuration R 7min V INmax V EXTmax– IR7max V INmin V EXTmin– IR7min 8 ... 16 V PEB 2023 PEF 2023 4567 GND VEXT VREF 81 0 V SYNCRC COMP GA P VN UV I P VS 0 V N2a 220µF 20% + 5 V 0 V BYS 21-45 BSP 295 CSS UVx N2b - 42 V BAS 21 N2c BYS 21-45 2.2 V RLoad1 82Ω/1% RLoad2 3.9ΚΩ/1% RLoad3 130Ω/1% AA AA 68µF 20% 100µF 20% 0.1Ω/5%0.47µF 20% CL1 CL2 CL3 2ΚΩ/1% 39ΚΩ 1nF 1µF 20% 47ΚΩ/5% 100nF 10% 72ΚΩ/1% 100µF 20% 4.7µF 20% 18ΚΩ/1% 1ΜΩ/10%
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1.6 Surge Protection
In telephone and ISDN-systems the topic “surge protection“ or “lightning overvoltage protection“ is very important. For the PEB/F 2023 overvoltage protection is necessary when the DC/DC converter input supply voltage VIN is connected to the U- or S-interface- lines. Figure 7 shows how to protect the PEB/F 2023 when using supply voltage range 3 (see also figure 4). For supply voltage ranges 1 and 2 the principle is the same. Figure 7 PEB/F 2023 Surge Protection The DC/DC converter begins operating when the input voltage exceeds VZD1 +8V+V RVs . In the start-up phase the PEB/F 2023 is supplied through VS. After this start-up phase, the PEB/F 2023 is supplied via VEXT (power housekeeping input, see figure 4) and the DC/DC-converter will operate until the input voltage falls below 20V (input undervoltage detection). The current i LVR needed in the start-up phase is less than 500µA. With this current and the value of resistor RVs the voltage VRVs can be calculated. For static and transient currents iUV and iUVx , respectively, absulote maximum ratings are valid. Because of the high value of R6 (for power saving reasons), iUV and iUVx normally are sufficiently low. Limits for voltage and current on pin VS are also defined in the maximum ratings. PEB 2023 PEF 2023 GND 11 12 UV V S 0 V BZV55C30 UVx R 6 C 6 100µF 20% ZD1 10ΜΩ/10% R Vs iVsiUV iUVx 9.4V 9.4V UV1.2V 100V ZDp LVR iLVR V EXT V IN Overvoltage protection UV ... Undervoltage detection circuit LVR ... Linear voltage regulator ZD ... parasitic zener diodep
Semiconductor Group 15 08.97 Calculation example: figure 7 with RVs = 4,7kΩ for t ≤ 100msec: for t ≤ 10msec: In this example the DC/DC converter begins operating when the input voltage exceeds 40,35V. The maximum transient input voltage is 177V / 271V for a duration of 100msec / 10msec. The maximum static input voltage is given by VZD1 + 90V = 120V, see absolute maximum ratings.
1.7 Fast Input Undervoltage Detection
With three extra devices (D5, D6 and R8, see figure 8) an undervoltage state on the input can be detected faster than the voltage on capacitor C6 decreases. See also chapter „undervoltage lockout“ on page 17. Figure 8 PEB/F 2023, Fast Input Undervoltage Detection V INstart V ZD1 8R Vs iLVR⋅()+ + 30V 8V 4 7 ,k Ω 500µ A⋅()+ + 40 35V ,== = V INmax V ZD1 100 R Vs iVsmax⋅()+ + 30V 100V 4 7 ,k Ω 10mA⋅()++ 1 7 7 V== = V INmax V ZD1 100 R Vs iVsmax⋅()+ + 30V 100V 4 7 ,k Ω 30mA⋅()++ 2 7 1 V== = PEB 2023 PEF 2023 GND V S 0 V BZV55C30 C 6 100µF 20% ZD UV R 6 10ΜΩ/10% R 8 10ΜΩ/10% D 5 D 6
Semiconductor Group 16 08.97
2 Functional Description
The PEB/F 2023 contains the following functional blocks:
- Supply and Biasing
- Undervoltage Detection
- Temperature Compensated Voltage Reference
- Sawtooth Oscillator
- Error Amplifier
- Pulse Width Modulator
- Digital Current Limiting
- S o f t S t a r t
- Control Logic (double pulse inhibit)
- Output Driver The reference voltage provides 4V for the regulation loop. A high gain error amplifier compares the reference voltage to the output voltage. The output of the error amplifier is then compared to a periodic ramp, which is generated by the sawtooth-oscillator circuit. The comparator output is a fixed-frequency, variable pulse width logic signal, which passes through logic circuits and the output driver and out to the external high voltage power-switching-FET. A digital current limiting device suppresses the PWM logic signal when the voltage difference between current limit sense input I P and GND reaches 100 mV to protect the external power-switching-FET. Non-isolated and isolated SMPS-configurations are possible. Logic and analog circuits are implemented in BICMOS in order to achieve low power dissipation. Start-Up Procedure Before the switched-mode DC/DC converter starts, a sequence of several conditions has to be passed in order to avoid any system malfunction. An integrated 6V linear voltage regulator supplies the internal low-voltage BICMOS- circuits from the input voltage VS. The generated supply voltage is connected to pin VEXT and has to be buffered by an external capacitor (Cmin = 1µF). Power dissipation of the linear voltage regulator can be reduced, if an external supply is used for that purpose by connecting it to pin V EXT . If the input voltage at VEXT is greater than 6.2V, the internal linear voltage regulator turns off and the internal BICMOS-circuits are then fed from the external voltage source (power housekeeping input V EXT ). In this case, the input current at VEXT is approximately 0.6mA.
Semiconductor Group 17 08.97 Note: An internal 9.4V zener diode protects the VEXT input against overvoltages. The maximum zener current is 6mA! If the external supply isn’t stabilized, the input current must be limited (e.g. by a resistor, see also supply voltage range 0)! Supply Voltage Ranges Supply Voltage Range 0: 8V to 16V In this supply voltage range the PEB/F 2023 can be supplied from a 12V battery. Connect the positive supply voltage via a resistor (R7 in figure 6) to pin VEXT and pin VS via a resistor (R6 in figure 6) to GND. Pin UV must be connected to pin VS. Pin UVx must be connected to pin VEXT . For calculating the values of the two resistors R 6 and R7, see the description of figure 6. Supply Voltage Range 1: 12V to 80V Connect the input voltage to pin VS and via a resistor (R6 in figure 5) to pins UV and UVx. For calculating the value of this resistor see the description of figure 5. Supply Voltage Range 2: 22V to 90V Connect the input voltage to pin VS and via a resistor to pin UV. Pin UVx is not connected (floating). Supply Voltage Range 3: UZD +8V to UZD +90V Connect the input voltage via a zener diode (minimum zener voltage UZD = 14V) to pin VS and via a resistor (R6 in figure 4) to pin UV. Pin UVx is not connected (floating). Undervoltage Lockout At the undervoltage detection pin UV, a resistor with a value of about 100kΩ ..10MΩ is required to protect this pin against high currents (see absolute maximum ratings). The level of undervoltage detection when using supply voltage range 1 is 8V..12V, using supply voltage range 2 or 3, it is 18V..22V. To get a higher undervoltage detection level a zener diode in series with the resistor is required. When the PEB/F 2023 detects an undervoltage condition, the gate output driver will be turned off. The DC/DC conversion is disabled and the PEB/F 2023 shows a high input impedance seen from the undervoltage detection pins (UV, UVx) and from pin V S to GND. Also the voltage on VEXT will decrease. When the undervoltage condition is removed, the DC/DC converter will be enabled once again with a soft start. Note: When using supply voltage range 0 the undervoltage detection circuit is not working. The resistor connected between VS and GND bypasses this undervoltage detection circuit (R6 in figure 6).
Semiconductor Group 18 08.97 Voltage Reference The reference regulator of the PEB/F 2023 is based on a temperature compensated bandgap. This circuitry is fully active at supply voltages (pin VEXT ) above 6 volts and provides up to 0.5mA of load current to external circuitry at 4 volts. This reference has to be buffered by an external capacitor (Cmin = 1µF). Sawtooth Oscillator The oscilator frequency is programmed by the two components R1 and C1 (see figure 4, 5 or 6). The oscillator timing capacitor C1 is charged by VREF through R1 and discharged by an internal 10kΩ discharge-resistor. The rise-time of the sawtooth oscillator can be programmed with R1 and C1. The internal discharge-resistor and C1 define the fall-time. At the beginning of the discharge period a positive synchronization pulse is generated at pin SYNC. Otherwise the PEB/F 2023 can be synchronized via pin SYNC to an external logic clock by programming the oscillator to free run at a frequency 10% lower than the synchronization frequency. The PEB/F 2023 is synchronized by the rising edge of the sync. signal. So multiple devices can be synchronized together by programming one master unit for the desired frequency (only one possible interfering frequency). Note that the frequency of the output driver is half the oscillator frequency. The switching frequency as a function of R 1 and C1 is shown in figure 9. Figure 9 Switching Frequency 100 150 200 250 300 350 10 20 30 40 50 60 70 80 90 100 R [ kOHM ] f [ kHz ] 10 pF 22 pF 68 pF 100 pF 220 pF 470 pF 1 nF
Semiconductor Group 19 08.97 Error Amplifier Conventional operational amplifier for closed-loop gain and phase compensation. Low output impedance: unity-gain stable. Pulse Width Modulator The pulse width modulator compares the sawtooth-voltage of the oscillator output with the output of the error amplifier and with the voltage of the external soft start capacitor at pin C SS . Current Limiting When the sense voltage reaches a threshold voltage of 100mV a shutdown signal is sent to the control logic. Sense voltage is the voltage between pin IP and pin GND. Because of the small value of the current-sensing-resistor (R5 in figure 4, 5 or 6) the board layout has to be done carefully. Soft Start The soft start circuit protects the power transistors and rectifier diodes from high current surges during power supply turn-on. When the supply voltage is connected to the PEB/ F 2023 the undervoltage lockout circuit holds the soft start capacitor voltage at zero. When the supply voltage reaches the normal operating range, an internal 1.5µA current source will charge the external soft start capacitor. As the soft start voltage ramps up to +5 volts, the duty cycle of the PWM linearly increases to whatever value the regulation loop requires. Control Logic The control logic inhibits double pulses during one duty cycle and limits the maximum duty cycle to 50%. Disable Input Realization One way to disable the function of the PEB/F 2023 is to connect an external n-channel MOS-transistor between the pins UV(drain) and GND(source). By switching on this external transistor the PEB/F 2023 detects an ’undervoltage’ and turns off. After switching off this external transistor the PEB/F 2023 turns on and starts the DC/DC conversion with a soft start. A second posibility is to connect an external n-channel MOS-transistor between the pins C SS (drain) and GND(source). By switching on this external transistor the PEB/F 2023 disables the gate output driver because of the soft start circutry. After switching off this external transistor the PEB/F 2023 turns on and starts the DC/DC conversion with a soft start.
Electrical Characteristics
Semiconductor Group 20 08.97
3 Electrical Characteristics
3.1 Absolute Maximum Ratings
Note: Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Note: If not otherwise stated than this absolute maximum values are static values. For overvoltage protection (pin VS respectively UV and UVx) see chapter 1.6 Surge Protection. Parameter Symbol Limit Values Unit Test Condition min. max. Supply voltage (pin VS) for sup. voltage range 1 VS1 -0.3 80 V Referred to GND Supply voltage (pin VS) for sup. voltage range 2 or 3 VS2,3 -0.3 90 V Referred to GND Transient input current on pin VS (sup. voltage range 1, 2 or 3) iVs -10 -30 mA mA t ≤ 100 msec t ≤ 10 msec Analog input voltage (pins IP, COMP, VP, VN , SYNC, RC) VI A -0.3 VEXT +0.3 V Referred to GND Reference output current (pin VREF ) IO REF 5m A SYNC-output current (pin SYNC) IO SYNC 5m A Error amplifier output current (pin COMP) IO COMP 5m A Z-current (pin VEXT ) IZ EXT 6m A Output current (pin VEXT ) IO EXT 6m A Driver output current (pin GA) IO DR 25 mA Undervoltage detection input currents (pins UV, UVx) IUV , IUVx iUV , iUVx -10 mA mA t ≤ 10 msec Junction temperature Tj 01 5 0 ° C Storage temperature Tstg -40 150 °C ESD-voltage, all pins 1 k V Human body model
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3.2 Operating Range
Note: In the operating range the functions given in the circuit description are fulfilled.
3.3 Static Thermal Resistance
Parameter Symbol Limit Values Unit Test Condition min. max. Ambient temperature under bias PEB 2023 PEF 2023 TA TA -40 Supply voltage (pin VS) for sup. voltage range 1 VS1 12 80 V Referred to GND Supply voltage (pin VS) for sup. voltage range 2 or 3 VS2,3 8 90 V Referred to GND Parameter Symbol Limit Values Unit Test Condition min. max. Junction to ambient Rth, jA 112 K/W P-DSO-14
Semiconductor Group 22 08.97
3.4 DC Characteristics
Parameter Symbol Limit Values Unit Test Condition min. typ. max. Supply current (pin VS to GND) IS 61 2 µA VEXT = 6.2V, VS = 40V Reference V REF Output voltage VREF O 3.96 4.0 4.04 V TA = 25°C , IL = 0mA, VS = 40V Line regulation VREF Line 0.1 5 mV TA = 25°C , VS = 25 to 65V, IL = 0mA, Load regulation VREF Load 25m V TA = 25°C , IL = 0.1 to 0.3mA, VS = 40V Temperature stability VREF TS 10 20 mV TA = -40 to 85°C , IL = 0mA, VS = 40V Oscillator SYNC, RC fOSC = 20kHz, R T = 39kΩ ± 1 %, C T = 1nF ± 1 % Initial accuracy ΔfO ± 5 ± 10 % TA = 25°C , VS = 40V Voltage stability of fOSC ΔfO Line ±0.1 ±1% TA = 25°C , VS = 25 to 65V Temperature stability of fOSC ΔfO TS ±5% TA = -40 to 85°C , VS = 40V Max. frequency fmax 550 kHz R T =20kΩ , C T=10pF H-sawtooth voltage VH 3.0 3.2 3.4 V L-sawtooth voltage VL 1.6 1.8 2.0 V H-sync output level VSYNC H 2.4 3.5 5.25 V IL = 0.5mA, VEXT = 6.2V L-sync output level VSYNC L 0.2 0.8 V IL = 20µA Pulse Width Modulator Duty cycle td 05 0 % Soft Start C SS Charging current IC 11 . 5 2µ A VCSS = 0V
Semiconductor Group 23 08.97 DC Characteristics (cont’d) Parameter Symbol Limit Values Unit Test Condition min. typ. max. Error Amplifier COMP , V P, V N Input offset voltage VIO -10 10 mV VCM = 3.0V Input current II 25 50 nA Common mode range VCMR 1.8 4.5 V DC open loop gain G VO 60 70 dB Common mode rejection kCMR 60 70 dB f ≤ 10kHz Unity gain bandwidth f 0.5 1 MHz C L (pin) = 10pF Supply voltage rejection V EXT / VCOMP kSVR 60 70 dB f ≤ 10kHz H-output voltage VOH 4.5 V IL = 100µA L-output voltage VOL 0.02 0.1 V IL = 10µA Current Limit Comparator IP TA = 25°C Sense voltage PEB 2023 PEF 2323 VSense VSense 100 100 110 115 mV mV VS = 40V VS = 40V Input bias current II -25 -40 µA VIP = 0V Input voltage range VI 01 V Response time (signal at GA)tRes 250 500 ns IP = 0 → 200mV Output Driver GA TA = 25°C, H-output voltage VOH 4.5 V EXT V ISource = 20mA, V EXT = 6.2V L-output voltage VOL 0.3 0.4 V ISink = 20mA Rise time (10% to 90%) tr 50 200 ns C L = 800pF, V EXT = 6.2V Fall time (90% to 10%) tf 50 200 ns C L = 800pF, V EXT = 6.2V
Semiconductor Group 24 08.97 DC Characteristics (cont’d) Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25°C and the given supply voltage. Parameter Symbol Limit Values Unit Test Condition min. typ. max. Undervoltage Detection UV, UVx Start-up threshold 1 VUV St1 8 10 12 V supply voltage range 1 Start-up threshold 2,3 VUV St2,3 18 20 22 V supply voltage range 2 or 3 External Supply V EXT Output voltage VO 5.8 6.0 6.2 V Output current IO 2m A Input voltage VI 6.2 9 V Z-current IZ 6m A General Parameters, TA = 25°C Power consumption Ptot 56m W VS = 40V, fOSC = 20kHz, C L GATE = 470pF, V EXT = 6.2 to 6.7V High impedance input currentIHI 10 µA „undervoltage“
Semiconductor Group 25 08.97
4 Package Outlines
Plastic Package, P-DSO-14 (Plastic Dual Small Outline