Q67100-Q1049

HYB5116400BJ-50- SIEMENS | Alldatasheet

Document overview

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Technical content

Semiconductor Group 1 1.96

• 4 194 304 words by 4-bit organization
• 0 to 70 °C operating temperature
• Performance:
• Single + 5 V (– 10 %) supply
• Low power dissipation max. 550 active mW (-50 version) max. 495 active mW (-60 version) max. 440 active mW (-70 version) 11 mW standby (TTL) 5.5. mW standby (MOS)
• Output unlatched at cycle end allows two-dimensional chip selection
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh and test mode
• Fast page mode capability
• All inputs, outputs and clocks fully TTL-compatible
• 4096 refresh cycles / 64 ms
• Plastic Package: P-SOJ-26/24 300 mil P TSOPII-26/24 300 mil -50 -60 -70 tRAC RAS access time 50 60 70 ns tCAC CAS access time 13 15 20 ns tAA Access time from address 25 30 35 ns tRC Read/Write cycle time 90 110 130 ns tPC Fast page mode cycle time 35 40 45 ns 4M x 4-Bit Dynamic RAM Advanced Information HYB5116400BJ -50/-60/-70 HYB5116400BT -50/-60/-70

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM The HYB 5116400BJ/BT is a 16MBit dynamic RAM organized as 4194304 words by 4-bits. The HYB 5116400BJ/BT utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5116400BJ/BT to be packaged in a standard SOJ 26/24 or TSOPII-26/24 plastic package, both with 300 mil width. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 5 V (– 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL.

Ordering Information

Type Ordering Code Package Descriptions HYB 5116400BJ-50 Q67100-Q1049 P-SOJ-26/24 300 mil DRAM (access time 50 ns) HYB 5116400BJ-60 Q67100-Q1050 P-SOJ-26/24 300 mil DRAM (access time 60 ns) HYB 5116400BJ-70 Q67100-Q1051 P-SOJ-26/24 300 mil DRAM (access time 70 ns) HYB 5116400BT-50 on request P-TSOPII-26/24 300milDRAM (access time 50 ns) HYB 5116400BT-60 on request P-TSOPII-26/24 300milDRAM (access time 60 ns) HYB 5116400BT-70 on request P-TSOPII-26/24 300milDRAM (access time 70 ns) A0-A11 Row Address Inputs A0-A9 Column Address Inputs RAS Row Address Strobe OE Output Enable I/O1-I/O4 Data Input/Output CAS Column Address Strobe WE Read/Write Input VCC Power Supply (+ 5 V) VSS Ground (0 V) N.C. not connected

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Pin Configuration P-SOJ-26/24 300 mil P-TSOPII-26/24 300 mil Vcc I/O1 I/O2 WE RAS A11 A10 VCC Vss I/O4 I/O3 CAS OE Vss

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Block Diagram No. 2 Clock Generator Column Address Buffer(10) Refresh Controller Refresh Counter (12) Address Buffers(12) Row No. 1 Clock Generator Data in Buffer Data out Buffer Column Decoder Sense Amplifier I/O Gating Memory Array 4096x1024x4 Row Decoder WE CAS 4096 1024 RAS I/O1 I/O2 I/O3 I/O4 OE 12 12 A10 A11 Voltage Down Generator VCC VCC (internal)

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Absolute Maximum Ratings Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V – 10 %; tT = 5 ns Parameter Symbol Limit Values Unit Test Conditionmin. max. Input high voltage VIH 2.4 Vcc+0.5 V 1) Input low voltage VIL – 0.5 0.8 V 1) Output high voltage (IOUT = – 5 mA) VOH 2.4 – V 1) Output low voltage (IOUT = 4.2 mA) VOL –0 . 4 V 1) Input leakage current (0 V £ VIH £ Vcc + 0.3V, all other pins = 0 V) II(L) – 10 10 mA 1) Output leakage current (DO is disabled, 0 V £ VOUT £ Vcc + 0.3V) IO(L) – 10 10 mA 1) Average VCC supply current: -50 ns version -60 ns version -70 ns version (RAS , CAS, address cycling: tRC = tRC min.) ICC1 100 mA mA mA 2) 3) 4) 2) 3) 4) 2) 3) 4) Standby VCC supply current (RAS=C A S= VIH) ICC2 –2m A – Average VCC supply current, during RAS-only refresh cycles: -50 ns version -60 ns version -70 ns version (RAS cycling, CAS = VIH, tRC = tRC min.) ICC3 100 mA mA mA 2) 4) 2) 4) 2) 4)

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Average VCC supply current, during fast page mode: -50 ns version -60 ns version -70 ns version (RAS = VIL, CAS, address cycling:tPC = tPC min.) ICC4 mA mA mA 2) 3) 4) 2) 3) 4) 2) 3) 4) Standby VCC supply current (RAS = CAS = VCC – 0.2 V) ICC5 –1m A 1) Average VCC supply current, during CAS- before-RAS refresh mode: -50 ns version -60 ns version -70 ns version (RAS , CAS cycling: tRC = tRC min.) ICC6 100 mA mA mA 2) 4) 2) 4) 2) 4) Average Self Refresh Current (CBR cycle with tRAS>TRASSmin., CAS held low, WE =Vcc-0.2V, Address and Din=Vcc--0.2V or 0.2V) ICC7 _1m A Capacitance TA = 0 to 70 °C,VCC = 5 V – 10 %, f = 1 MHz Parameter Symbol Limit Values Unit min. max. Input capacitance (A0 to A11) C I1 –5p F Input capacitance (RAS, CAS, WE, OE) C I2 –7p F I/O capacitance (I/O1-I/O4) C IO –7p F DC Characteristics (cont’d) TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V – 10 %; tT = 5 ns Parameter Symbol Limit Values Unit Test Conditionmin. max.

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM AC Characteristics 5)6) 16F TA = 0 to 70 °C,VCC = 5 V – 10 %, tT = 5 ns Parameter Symbol Limit Values Unit Note -50 -60 -70 common parameters Random read or write cycle timetRC 90 – 110 – 130 – ns RAS precharge time tRP 30 – 40 – 50 – ns RAS pulse width tRAS 50 10k 60 10k 70 10k ns CAS pulse width tCAS 13 10k 15 10k 20 10k ns Row address setup time tASR 0–0–0–n s Row address hold time tRAH 8–1 0 –1 0 –n s Column address setup time tASC 0–0–0–n s Column address hold time tCAH 10 – 15 – 15 – ns RAS to CAS delay time tRCD 18 37 20 45 20 50 RAS to column address delay time tRAD 13 25 15 30 15 35 ns RAS hold time tRSH 13 15 – 20 – ns CAS hold time tCSH 50 60 – 70 – ns CAS to RAS precharge time tCRP 5–5–5–n s Transition time (rise and fall)tT 35 0 35 0 35 0 n s 7 Refresh period tREF –6 4 –6 4 –6 4 m s Read Cycle Access time from RAS tRAC –5 0 –6 0 –7 0 n s 8 , 9 Access time from CAS tCAC –1 3 –1 5 –2 0 n s 8 , 9 Access time from column addresstAA –2 5 –3 0 –3 5 n s 8 , 1 0 OE access time tOEA –1 3 –1 5 –2 0 n s Column address to RAS lead timetRAL 25 – 30 – 35 – ns Read command setup time tRCS 0–0–0–n s Read command hold time tRCH 0–0–0–n s 1 1 Read command hold time referenced to RAS tRRH 0–0–0–n s 1 1 CAS to output in low-Z tCLZ 0–0–0–n s 8 Output buffer turn-off delaytOFF 01 3 01 5 02 0 n s 1 2

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Output buffer turn-off delay from OE tOEZ 01 3 01 5 02 0 n s 1 2 Data to OE low delay tDZO 0–0–0–n s 1 3 CAS high to data delay tCDD 13 – 15 – 20 – ns 14 OE high to data delay tODD 13 – 15 – 20 – ns 14 Write Cycle Write command hold time tWCH 8–1 0 –1 0 –n s Write command pulse width tWP 8–1 0 –1 0 –n s Write command setup time tWCS 0–0–0–n s 1 5 Write command to RAS lead timetRWL 13 – 15 – 20 – ns Write command to CAS lead timetCWL 13 – 15 – 20 – ns Data setup time tDS 0–0–0–n s 1 6 Data hold time tDH 10 – 10 – 15 – ns 16 Data to CAS low delay tDZC 0–0–0–n s 1 3 Read-Modify-Write Cycle Read-write cycle time tRWC 126 – 150 – 180 – ns RAS to WE delay time tRWD 68 – 80 – 95 – ns 15 CAS to WE delay time tCWD 31 – 35 – 45 – ns 15 Column address to WE delay timetAWD 43 – 50 – 60 – ns 15 OE command hold time tOEH 13 – 15 – 20 – ns Fast Page Mode Cycle Fast page mode cycle time tPC 35 – 40 – 45 – ns CAS precharge time tCP 10 – 10 – 10 – ns Access time from CAS precharge tCPA –3 0 –3 5 –4 0 n s 7 RAS pulse width tRAS 50 200k 60 200k 70 200k ns CAS precharge to RAS Delay tRHPC 30 – 35 – 40 – ns AC Characteristics (cont’d) 5)6) 16F TA = 0 to 70 °C,VCC = 5 V – 10 %, tT = 5 ns Parameter Symbol Limit Values Unit Note -50 -60 -70

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Fast Page Mode Read-Modify-Write Cycle Fast page mode read-write cycle time tPRWC 71 – 80 – 95 – ns CAS precharge to WE tCPWD 48 – 55 – 65 – ns CAS -before-RAS Refresh Cycle CAS setup time tCSR 10 – 10 – 10 – ns CAS hold time tCHR 10 – 10 – 10 – ns RAS to CAS precharge time tRPC 5–5–5–n s Write to RAS precharge time tWRP 10 – 10 – 10 – ns Write hold time referenced to RAS tWRH 10 – 10 – 10 – ns CAS -before-RAS Counter Test Cycle CAS precharge time tCPT 35 – 40 – 40 – ns Test Mode CAS hold time tCHRT 30 – 30 – 30 – ns Write command setup time tWTS 10 – 10 – 10 – ns Write command hold time tWTH 10 – 10 – 10 – ns Self Refresh Cycle RAS pulse width tRASS 100k – 100k – 100k – ns 17 RAS precharge time tRPS 95 – 110 – 130 – ns 17 CAS hold time tCHS -50 – -50 – -50 – ns 17 AC Characteristics (cont’d) 5)6) 16F TA = 0 to 70 °C,VCC = 5 V – 10 %, tT = 5 ns Parameter Symbol Limit Values Unit Note -50 -60 -70

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Notes: 1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5) An initial pause of 200 ms is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS -before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 2 TTL loads and 100 pF. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11)Either tRCH or tRRH must be satisfied for a read cycle. 12)tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13)Either tDZC or tDZO must be satisfied. 14)Either tCDD or tODD must be satisfied. 15)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh.

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Read Cycle RowColumnRow Valid Data Out RAS CAS Address WE OE I/O (Inputs) I/O (Outputs) VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tRAS tRC tCSH tRAD tCAS tRP tRAH tCRPtRSHtRCD tRAL tASR tCAHtASC tASR tRCH tRRHtRCS tAA tOEA tCLZ tCAC tOEZ tODD tCDD tOFF tDZC tDZO tRAC Hi ZHi Z “H” or “L” WL1

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Write Cycle (Early Write) RAS CAS Address WE OE I/O (Inputs) I/O (Outputs) VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tRAS tRC tCSH tRAD tCAS tRP tCRPtRSHtRCD tRAL tASR tCAH tASR tCWL tRWL tWP tASC tWCH Valid Data In tDS tDH Hi Z Column RowRow tRAH tWCS “H” or “L” WL2

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Write Cycle (OE Controlled Write) Valid Data tRWL tWP tOEH tODD tCWL tDZO tOEA tCLZ tDS tOEZ tDH tRC VIH VIL Row tDZC “H” or “L” Hi-ZHi-Z ColumnRow tASC tRAD tRAL tCAH tRAH RAS CAS Address WE OE I/O (Inputs) I/O (Outputs) VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tRAS tCSH tCAS tRP tCRPtRSHtRCD tASR tASR WL3

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Read-Write (Read-Modify-Write) Cycle RowRow tCSH tCAS tCRP tRWC tAWD tASR tRPtRAS tRAH tCAH I/O (Outputs) VOH VOL VIH VIL VIH VIL I/O (Inputs) OE WE VIH VIL tASR Column tRCD tDH tRSH tRAD tCWD tOEH tRWD tRWL tCWL tCLZ tWP tRCS tAA tOEA tDS tDZC tDZO tODD tCAC tOEZ Valid Data in Data Out tRAC “H” or “L” tASC VIH VIL VIH VIL RAS CAS Address VIH VIL WL4

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Fast Page Mode Read Cycle tRASP tCAStCAS tPC tCPtRCD tCSH tCAH tCAH tASCtASCtASR tRAH tRAD tRCS tRCS tRCS tASC tCAH tCAS tRSH tCRP tRP tASR tRCH tCPA tOEAtOEA tAAtAA tDZC tDZC tCDD tRRHtCPA tOEA tAA tDZC tDZO tODD tODD tDZO tODD tDZO tOFF tOEZtOEZ tOFF tOEZ tCAC tCAC tCLZtCLZtCLZ tOFF tRAC tCAC Valid Data Out Data Out Data Out Valid Valid ColumnColumnRow Row RAS I/O (Outputs) I/O (Inputs) OE WE Address CAS VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL “H” or “L” tRHCP tRCH VOH VOL Column FPM1

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Fast Page Mode Early Write Cycle tRAS tRP tRSH tCAStCAStCP tCRP tRAL tCAH tASR tCWL tRWL tCAH tASC tASC tCWLtCWL tWCS tWCS tWCS tWCH tWPtWP tWCH tWP tWCH tRAD tCAStRCD tPC tCAH tRAH tASR tASC tDH tDS tDS tDH tDH tDS Column Column ColumnRow Valid Data In ValidValid Data InData In Column HI-Z RAS I/O (Outputs) I/O (Inputs) OE WE Address CAS VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL “H” or “L” VOH VOL FPM2

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Fast Page Mode Read-Modify-Write Cycle tCAH tCP tDZC tDZO tRAC tCAC tCLZ tRCS tAA tOEA tRCD tRAD tRAH tASR tASC tCAS tCAStPRWC tCWD tCAH tASC tCAStRSH tRP tCRP tASR tCAH tASC tRAL tCWD tRWD tCWL tCWL tCWD tAWD tAWD tWP tWP tCWLtRWL tAWD tWP tODD tOEH tDH tDS tCPA tOEZ tCLZ tDZC tAA tCAC tOEA tDS tOEZ tDHtOEH tAA tODD tDZC tCPA tOEA tCLZ tDS tDHtOEH tODD RAS V IH V IL CAS V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL VOH VOL WE OE Address I/O (Inputs) I/O (Outputs) Data In Data In Data In Data Out Out DataDataOut RowColumnAddress ColumnRow tRAS tCSH Column tCPWD tCPWD “H” or “L” tOEZ

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM RAS -Only Refresh Cycle tCRP tRAH tRPtRAS tRC tASR tASR tRPC VIH VIL VIH VIL VIH VIL VOH VOL RowRow HI-Z Address RAS CAS I/O (Outputs) “H” or “L” WL9

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM CAS -Before-RAS Refresh Cycle tRPtRAStRP tRC tCRP tCP tRPC tCHR tWRH tWRP tCSR tRPC tOFF tOEZ tCDD tODD VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL HI-Z “H” or “L” RAS I/O (Outputs) I/O (Inputs) OE WE CAS VOH VOL WL10

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM CAS -before-RAS Self Refresh tRPStRASStRP tCRP tCP tRPC tWRH tWRP tCSR tOFF tOEZ tCDD tODD VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL HI-Z “H” or “L” RAS I/O (Outputs) I/O (Inputs) OE WE CAS VOH VOL tCHS WL13

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Hidden Refresh Cycle (Read) RAS I/O (Outputs) I/O (Inputs) OE WE Address CAS tRC tRC tRAStRAS tRP tRP tCRPtCHR tRAD tCAH tASC tRAH tASR tASR tRCS tRRH tAA tDZC tDZO tCAC tRAC tCLZ tOEZ tOFF tODD tCDD tRCD tRSH tOEA VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tWRP tWRH “H” or “L” Valid Data Out RowColumnRow HI-Z VOH VOL WL11

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Hidden Refresh Cycle (Early Write) RAS I/O (Output) I/O (Input) WE Address VIH VIL VIH VIL V IH VIL CAS VIH VIL VIH VIL “H” or “L” tRC tRAS tRCD tRSH tRAD tCAH tWCS tWCH tWP tASR tRAH tDS tDH tASR tCRPtCHR tRP tRAS tRC tRP tASC Row Row Valid Data HI-Z Column V OH VOL tWRP tWRH WL12

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM CAS -Before-RAS Refresh Counter Test Cycle tCSR tASRtASC tCHR tCP tWRP tRAL tCAH tRSH tRPtRAS tCAS tRCS tCDD tCAC tAA tWRH tOEA tODD tCLZ tDZC tDZO tOEZ tOFF tRWL tCWL tWCH tWCS tWRH tWRP tDS tDH V IHV IL V IH V IL V IH V IL VOH VOL V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL RAS I/O (Inputs) OE WE Address CAS I/O (Outputs) I/O (Outputs) I/O (Inputs) WE OE Column Row Data Out Data In HI-Z Read Cycle: Write Cycle: tRRH tRCH

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Test Mode Entry tRC tRAS tRP tRPC tCRPtCHR tWTH tRPC tRP tCP tCSR tWTS tCDD tOFF tOEZ tODD I/O (Outputs) VOH VOL VIH VIL VIH VIL I/O (Inputs) OE WE VIH VIL CAS RAS VIH VIL VIH VIL “H” or “L” HI-Z Address tRAHtASR VIH VIL Row WL15 HI-Z

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Test Mode As the HYB 5116400BJ/BT is organized internally as 1M x 16-bits, a test mode cycle using 4:1 compression can be used to improve test time. Note that in the 4M x 4 version the test time is reduced by 1/4 for a N test pattern. In a test mode “write” the data from each I/O pin is written into four 1M blocks simultaneously (all “1” s or all “0” s). In test mode “read” each I/O output is used for indicating the test mode result. If the internal four bits are equal, the I/O would indicate a “1”. If they were not equal, the I/O would indicate a “0”. The WCBR cycle (WE , CAS before RAS) puts the device into test mode. To exit from test mode, a “CAS before RAS refresh”, “RAS only refresh” or “Hidden refresh” can be used.Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. Row addresses A0 through A9 have to kept high to perform a testmode entry cycle. All other addresses are don’t care. Block Diagram in Test Mode Normal Test Vcc Vss I/O 3 Normal Test Vcc Vss I/O 2 Normal Test Vcc Vss I/O 1

1 M Block

A0C,A1C A0C,A1C A0C,A1C A0C,A1C A0C,A1C A0C,A1C A0C,A1C A0C,A1C Normal Test Vcc Vss I/O 4

HYB 5116400BJ/BT-50/-60/-70 4M x 4-DRAM Package Outlines Plastic Package P-SOJ-26/24 (300 mil) (Small Outline J-leads, SMD) /G31/G29 /G44/G6F/G65/G73 /G6E/G6F/G74 /G69/G6E/G63/G6C/G75/G64/G65 /G70/G6C/G61/G73/G74/G69/G63 /G6F/G72 /G6D/G65/G74/G61/G6C /G70/G72/G6F/G74/G72/G75/G73/G69/G6F/G6E /G6F/G66 /G30/G2E/G31/G35 /G6D/G61/G78 /G70/G65/G72 /G73/G69/G64/G65 /G49/G6E/G64/G65/G78 /G4D/G61/G72/G6B/G69/G6E/G67 /G47/G50/G4A/G30/G35/G36/G32/G38 /G32/G34/G78/G30/G2E/G32 /G4D/G2D/G30/G2E/G31 /G2D/G30/G2E/G32/G30/G2E/G36 /G30/G2E/G31 /G31/G29 /G49/G6E/G64/G65/G78 /G4D/G61/G72/G6B/G69/G6E/G67 /G39/G2E/G32/G32 /G31/G33/G31 /G31/G34/G32/G36 /G37/G2E/G36/G32 /G2B/G30/G2E/G31/G32/G30/G2E/G34 /G31/G2E/G32/G37 /G31/G37/G2E/G32/G37 /G30/G2E/G32/G2D/G2B /G30/G2E/G31/G33/G2D/G2B /G2D/G30/G2E/G32/G35 /G47/G50/G58/G30/G35/G38/G35/G37