Q67100-3033

HYB514265BJ-400 SIEMENS | Alldatasheet

Document overview

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Technical content

The HYB 5(3)14265BJ(L) is the new generation dynamic RAM organized as 262 144 words by 16-bit. The HYB 5(3)14265BJ(L) utilizes the SIEMENS 16M-CMOS submicron silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)14265BJ(L) to be packed in a standard plastic 400mil wide P-SOJ-40-3 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. The HYB314265BJL parts have a very low power “sleep mode“ supported by Self Refresh. 256K x 16-Bit EDO-Dynamic RAM Preliminary Information

• 262 144 words by 16-bit organization
• 0 to 70°C operating temperature
• EDO - Hyper Page Mode
• Performance:
• Low Power dissipation - Active(max.): 120mA / 120mA / 105mA / 95 mA - Standby : TTL Inputs (max.) 2.0 mA - Standby: CMOS Inputs (max.) 1.0 mA - Standby (L-version) 200µA -400 -40 -45 -50 trc 69 69 79 89 ns trac 40 40 45 50 ns tcac 10 10 12 13 ns taa 20 20 22 25 ns thpc 12,5 15 18 20 ns thpc 80 66 55 50 MHz
• Power Supply:
• Read, write, read-modify-write,CAS -before RAS refresh,RAS only refresh, hidden refresh mode
• Low Power Version (L) with Self Refresh and 250µA self refresh current
• 2 CAS / 1WE control
• All inputs and outputs TTL-compatible
• 512 refresh cycles / 16 ms 512 refresh cycles / 128 ms (L-version)
• Plastic Packages: P-SOJ-40-3 400 mil width HYB 514265BJ-400 +5 V ±5% HYB 514265BJ-40 +5 V ±10% HYB 514265BJ-45 +5 V ±10% HYB 514265BJ-50 +5 V ±10% HYB 314265BJ(L)-45 +3.3 V ±0.3 V HYB 314265BJ(L)-50 +3.3 V ±0.3 V 6.96 HYB 514265BJ-400/40/-45/-50 HYB 314265BJ(L)-45/-50

Ordering Information

5 V versions:

HYB 514265BJ-400 Q67100-3033 P-SOJ-40-3 5 V 40 ns 256 K x 16 EDO-DRAM HYB 514265BJ-40 Q67100-3039 P-SOJ-40-3 5 V 40 ns 256 K x 16 EDO-DRAM HYB 514265BJ-45 Q67100-3035 P-SOJ-40-3 5 V 45 ns 256 K x 16 EDO-DRAM HYB 514265BJ-50 Q67100-3036 P-SOJ-40-3 5 V 50 ns 256 K x 16 EDO-DRAM

3.3 V versions:

HYB 314265BJ-45 on request P-SOJ-40-3 3.3 V 45 ns 256 K x 16 EDO- DRAM HYB 314265BJ-50 on request P-SOJ-40-3 3.3 V 50 ns 256 K x 16 EDO- DRAM HYB 314265BJL-45 on request P-SOJ-40-3 3.3 V Low Power 45 ns 256 K x 16 EDO- DRAM HYB 314265BJL-50 on request P-SOJ-40-3 3.3 V Low Power 50 ns 256 K x 16 EDO-DRAM RAS LCAS UCAS WE OE I/O1-I/O8 I/O9-I/O16 Operation H L L L L L L L L H H L H L L H L L H H H L L H L L L H H H H H L L L H H H L L L H H H H High-Z High-Z Dout High-Z Dout Din Don't care Din High-Z High-Z High-Z High-Z Dout Dout Don't care Din Din High-Z Standby Refresh Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write A0-A8 Address Inputs RAS Row Address Strobe UCAS, LCAS Column Address Strobe WE Read/Write Input OE Output Enable I/O1 – I/O16 Data Input/Output VCC Power Supply: + 5 V for HYB 514265, + 3.3 V for HYB 314265 VSS Ground (0 V) N.C. No Connection

(top view) P-SOJ-40-3

VCC + 0.5, 4.6) V Note: Stresses above those listed under“Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics for HYB514265 TA = 0 to 70°C; VSS = 0 V;VCC = 5 V± 10 % (± 5 % for -400 version) ,tT = 2 ns Parameter Symbol Limit Values Unit Notes min. max. Input high voltage VIH 2.4 VCC + 0.5 V 1 Input low voltage VIL – 0.5 0.8 V 1 Output high voltage (IOUT = – 5.0 mA) VOH 2.4 – V 1 Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V 1 Input leakage current, any input (0 V < VIN < 7 V, all other inputs = 0 V) II(L) – 10 10 µA 1 Output leakage current (DO is disabled, 0 V <VOUT < VCC ) IO(L) – 10 10 µA 1 AverageVCC supply current: -400 version -40 version -45 version -50 version ICC1 – 120 120 105 mA 2, 3, 4 StandbyVCC supply current (RAS = LCAS = UCAS = WE = VIH) ICC2 – 2 mA – AverageVCC supply current duringRAS-only refresh cycles: -400 version -40 version -45 version -50 version ICC3 – 120 120 105 mA 2, 4

DC Characteristics for 314265 TA = 0 to 70°C; VSS = 0 V;VCC = 3.3 V± 0.3 V,tT = 2 ns AverageVCC supply current during hyper page mode (EDO) operation: -400 version -40 version -45 version -50 version ICC4 – 110 mA 2, 3, 4 StandbyVCC supply current (RAS = LCAS = UCAS = WE = VCC – 0.2 V) ICC5 –1 m A 1 StandbyVCC supply current (L-version only) (RAS = LCAS = UCAS = WE = VCC – 0.2 V) ICC5 – 200 µA 1 AverageVCC supply current during CAS-before-RAS refresh mode: -400 version -40 version -45 version -50 version ICC6 – 120 120 105 mA 2, 4 Parameter Symbol Limit Values Unit Test Conditionmin. max. Input high voltage VIH 2.0 VCC + 0.5 V 1 Input low voltage VIL – 0.5 0.8 V 1 TTL Output high voltage (IOUT = – 2.0 mA) VOH 2.4 – V 1 TTL Output low voltage (IOUT = 2 mA) VOL – 0.4 V 1 CMOS Output high voltage (IOUT = – 100µA) VOH 2.4 – V 1 CMOS Output low voltage (IOUT = 100µA) VOL – 0.4 V 1 Input leakage current, any input (0 V < VIN < VCC + 0.3 V, all other inputs = 0 V) II(L) – 10 10 µA 1 Output leakage current (DO is disabled, 0 V <VOUT < VCC + 0.3 V) IO(L) – 10 10 µA 1 AverageVCC supply current: -45 version -50 version ICC1 – 105 mA 2, 3, 4 StandbyVCC supply current (RAS = LCAS = UCAS = WE = VIH) ICC2 – 2 mA – Parameter Symbol Limit Values Unit Notes min. max.

TA = 0 to 70°C; f = 1 MHz AverageVCC supply current during RAS-only refresh cycles: -45 version -50 version ICC3 – 105 mA 2, 4 AverageVCC supply current during hyper page mode (EDO) operation: -45 version -50 version ICC4 – mA 2, 3, 4 StandbyVCC supply current (RAS = LCAS = UCAS = WE = VCC – 0.2 V) ICC5 –1m A 1 StandbyVCC supply current (L-version only) (RAS = LCAS = UCAS = WE = VCC – 0.2 V) ICC5 – 200 µA 1 AverageVCC supply current duringCAS- before-RAS refresh mode: -45 version -50 version ICC6 105 mA 2, 4 Self Refresh Current (L-version only) CBR cycle withRAS >trasss(min), CAS held low; WE = VCC – 0.2 V, Addresses and Din =VCC – 0.2 V or 0.2 V ICC7 – 250 µA Parameter Symbol Limit Values Unit min. max. Input capacitance (A0 to A8) C I1 –5p F Input capacitance (RAS, UCAS, LCAS, WE, OE) C I2 –7p F Output capacitance (l/O1 to l/O16) C IO –7p F Parameter Symbol Limit Values Unit Test Conditionmin. max.

AC Characteristics5) 6) TA = 0 to 70°C, tT = 2 ns Parameter Symbol Limit Values Unit Note -400 -40 min. max. min. max. Common Parameters Random read or write cycle time tRC 69 – 69 – ns RAS precharge time tRP 25 – 25 – ns RAS pulse width tRAS 40 10k 40 10k ns CAS pulse width tCAS 4.5 10k 6 10k ns CAS precharge time tCP 4–5–n s Row address setup time tASR 0–0–n s Row address hold time tRAH 5–5–n s Column address setup time tASC 0–0–n s Column address hold time tCAH 5–5–n s RAS toCAS delaytime tRCD 9 30 9 30 ns RAS to column address delay time tRAD 7 20 7 20 ns RAS hold time tRSH 6–6–n s CAS hold time tCSH 32 – 32 – ns CAS toRAS precharge time tCRP 5–5–n s Transition time(rise and fall) tT 1 50 1 50 ns 7 Refresh period tREF 16 – 16 – ms Read Cycle Access time fromRAS tRAC – 40 – 40 ns 8, 9 Access time fromCAS tCAC – 10 – 10 ns 8, 9 Access time from column address tAA – 17 – 20 ns 8,10 OE access time tOEA – 10 – 10 ns Column address toRAS lead time tRAL 20 – 20 – ns Read command setup time tRCS 0–0–n s Read command hold time tRCH 0–0–n s 11 Read command hold time ref. toRAS tRRH 0–0–n s 11 CAS to output inlow-Z tCLZ 0–0–n s 8 Output buffer turn-off delay fromCAS tOFF 0–01 0 n s 12

Output buffer turn-off delay fromOE tOEZ 0 10 0 10 ns 12 Data toOE low delay tDZO 0–0 n s 13 CAS high to data delay tCDD 8–8–n s 14 OE high to data delay tODD 8–8–n s 14 Data toCAS low delay tDZC 0–0–n s 13 Write Cycle Write command hold time tWCH 5–5–n s Write command pulse width tWP 5–5–n s Write command setup time tWCS 0–0–n s 15 Write command toRAS lead time tRWL 10 – 10 – ns Write command toCAS lead time tCWL 10 – 10 – ns Data setup time tDS 0–0–n s 16 Data hold time tDH 5–5–n s 16 Data toCAS low delay tDZC 0–0–n s 13 Read-modify-Write Cycle Read-write cycle time tRWC 93 – 93 – ns RAS toWE delay time tRWD 52 – 52 – ns 15 CAS toWE delay time tCWD 22 – 22 – ns 15 Column address toWE delay time tAWD 32 – 32 – ns 15 OE command hold time tOEH 5–5–n s Hyper Page Mode (EDO) Cycle Hyper page mode cycle time tHPC 12.5 – 15 – ns Access time fromCAS precharge tCPA – 17 – 21 ns 7 Output data hold time tCOH 3–3–n s RAS pulse width in hyper page mode tRAS 40 200k 40 200k ns RAS hold time fromCAS precharge tRHCP 17 – 21 – ns Parameter Symbol Limit Values Unit Note -400 -40 min. max. min. max.

Hyper Page Mode (EDO) Read-Modify-Write Cycle Hyper page mode read/write cycle time tPRWC 55 – 55 – ns CAS precharge toWE delay time tCPWD 35 – 35 – ns CAS before RAS Refresh Cycle CAS setup time tCSR 5–5–n s CAS hold time tCHR 5–5–n s RAS toCAS precharge time tRPC 5–5–n s Write toRAS precharge time tWRP 10 – 10 – ns Write toRAS hold time tWRH 10 – 10 – ns CAS-before-RAS Counter Test Cycle CAS precharge time tCPT 25 – 25 – ns Parameter Symbol Limit Values Unit Note -400 -40 min. max. min. max.

AC Characteristics 5)6) 16E TA = 0 to 70 ˚C,tT = 2 ns Parameter Symbol Limit Values Unit Note -45 -50 min. max. min. max. Common Parameters Random read or write cycle time tRC 79 – 89 – ns RAS precharge time tRP 30 – 35 – ns RAS pulse width tRAS 45 10k 50 10k ns CAS pulse width tCAS 7 10k 8 10k ns CAS precharge time tCP 7–8–n s Row address setup time tASR 0–0–n s Row address hold time tRAH 7–8–n s Column address setup time tASC 0–0–n s Column address hold time tCAH 7–8–n s RAS toCAS delay time tRCD 11 33 12 37 ns RAS to column address delay tRAD 9 2 31 02 5n s RAS hold time tRSH 12 13 – ns CAS hold time tCSH 36 40 – ns CAS toRAS precharge time tCRP 5–5–n s Transition time (rise and fall) tT 1 50 1 50 ns 7 Refresh period tREF – 16 – 16 ms Refresh period (L-version only) tREF – 128 – 128 ms Read Cycle Access time fromRAS tRAC – 45 – 50 ns 8, 9 Access time fromCAS tCAC – 12 – 13 ns 8, 9 Access time from column address tAA – 22 – 25 ns 8,10 OE access time tOEA – 12 – 13 ns Column address toRAS lead time tRAL 23 – 25 – ns Read command setup time tRCS 0–0–n s Read command hold time tRCH 0–0–n s 1 1 Read command hold time referenced toRAS tRRH 0–0–n s 1 1 CAS to output in low-Z tCLZ 0–0–n s 8

Output buffer turn-off delay tOFF 0 12 0 13 ns 12 Output turn-off delay fromOE tOEZ 0 12 0 13 ns 12 Data toCAS low delay tDZC 0–0–n s 1 3 Data toOE low delay tDZO 0–0–n s 1 3 CAS high to data delay tCDD 10 – 10 – ns 14 OE high to data delay tODD 10 – 10 – ns 14 Write Cycle Write command hold time tWCH 7–8–n s Write command pulse width tWP 7–8–n s Write command setup time tWCS 0–0–n s 1 5 Write command toRAS lead time tRWL 12 – 13 – ns Write command toCAS lead time tCWL 12 – 13 – ns Data setup time tDS 0–0–n s 1 6 Data hold time tDH 7–8–n s 1 6 Read-modify-Write Cycle Read-write cycle time tRWC 107 – 118 – ns RAS to WE delay time tRWD 59 – 64 – ns 15 CAS toWE delay time tCWD 26 – 27 – ns 15 Column address toWE delay time tAWD 36 – 39 – ns 15 OE command hold time tOEH 7–1 0 –n s Hyper Page Mode (EDO) Cycle Hyper page mode (EDO) cycle time tHPC 18 – 20 – ns Access time fromCAS precharge tCPA – 25 – 27 ns 7 Output data hold time tCOH 5–5–n s RAS pulse width in EDO mode tRAS 45 200k 50 200k ns CAS precharge toRAS Delay tRHPC 25 – 27 – ns AC Characteristics (cont’d) 5)6) 16E TA = 0 to 70 ˚C,tT = 2 ns Parameter Symbol Limit Values Unit Note -45 -50 min. max. min. max.

Notes: 1) All voltages are referenced toVSS . 2) ICC1 ,ICC3 ,ICC4 andICC6 depend on cycle rate. 3) ICC1 andICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS =VIL. In case ofICC4 it can be changed once or less during a hyper page mode (EDO) cycle 5) An initial pause of 200µs is required after power-up followed by 8RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8RAS cycles are required. 6) AC measurements assume tT = 2 ns. Hyper Page Mode (EDO) Read-modify-Write Cycle Hyper page mode (EDO) read-write cycle timetPRWC 51 – 58 – ns CAS precharge toWE tCPWD 41 – 41 – ns CAS-before-RAS Refresh Cycle CAS setup time tCSR 5–1 0 –n s CAS hold time tCHR 10 – 10 – ns RAS toCAS precharge time tRPC 5–5–n s Write toRAS precharge time tWRP 10 – 10 – ns Write hold time referenced toRAS tWRH 10 – 10 – ns CAS-before-RAS Counter Test Cycle CAS precharge time tCPT 30 – 35 – ns Self Refresh Cycle (L-version) RAS pulse width tRASS 100k – 100k – ns 17 RAS precharge tRPS 110 – 95 – ns 17 CAS hold time tCHS – 50 – – 50 – ns 17 AC Characteristics (cont’d) 5)6) 16E TA = 0 to 70 ˚C,tT = 2 ns Parameter Symbol Limit Values Unit Note -45 -50 min. max. min. max.

7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured betweenVIH andVIL. 8) Measured with the specified current load and 50 pF atVOL = 0.8 V andVOH = 2.0 V. Access time is determined by the latter oftRAC ,tCAC ,tAA ,tCPA ,tOEA . tCAC is measured from tristate 9) Operation within thetRCD (max.) limit ensures thattRAC (max.) can be met.tRCD (max.) is specified as a reference point only. IftRCD is greater than the specifiedtRCD (max.) limit, then access time is controlled bytCAC . 10) Operation within thetRAD (max.) limit ensures thattRAC (max.) can be met.tRAD (max.) is specified as a reference point only. IftRAD is greater than the specifiedtRAD (max.) limit, then access time is controlled bytAA . 11) EithertRCH ortRRH must be satisfied for a read cycle. 12)tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels.tOFF is referenced from the rising edge ofRAS or CAS, whichever occurs last. 13) EithertDZC ortDZO must be satisfied. 14) EithertCDD ortODD must be satisfied. 15)tWCS ,tRWD ,tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. IftWCS >tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; iftRWD >tRWD (min.),tCWD >tCWD (min.) andtAWD >tAWD (min.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to theWE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh. 50 pF I/O Z=50 Ohm + 1.5 V

50 Ohm

fig.2

Write Cycle (Early Write)

Write Cycle (OE Controlled Write)

Read-Write (Read-Modify-Write) Cycle

Hyper Page Mode (EDO) Read Cycle

Hyper Page Mode (EDO) Early Write Cycle

Hyper Page Mode (EDO) Late Write and Read-Modify-Write Cycles

CAS-Before-RAS Refresh Cycle

CAS before RAS Self Refresh Cycle

Hidden Refresh Cycle (Read)

Hidden Refresh Cycle (Early Write)

CAS-Before-RAS Refresh Counter Test Cycle

(Small Outline J-Leaded Package) GPJ09018 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device