TLE4290 INFINEON | Alldatasheet
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Technical content
Features
- Output voltage 5 V ± 2% Very low current consumption 450 mA current capability Power Good Feature Very low-drop voltage Short-circuit-proof Reverse polarity proof Suitable for use in automotive electronics
- New type Functional Description The TLE 4290 is a monolithic integrated low-drop voltage regulator which can supply loads up to 450 mA with power good feature. An input voltage up to 42 V is regulated to VQ,nom = 5.0 V. The device is designed to supply µ-controllers in the severe environment of automotive applications. Therefore it is protected against overload, short circuit and over temperature conditions. Of course the TLE 4290 can been used also in all other applications, where a stabilized 5 V voltage is required. Type Ordering Code Package
- TLE 4290 D Q67006-A9408 P-TO252-5-1 (SMD)
- TLE 4290 G Q67006-A9405 P-TO263-5-1 (SMD)
- TLE 4290 Q67000-A9407 P-TO220-5-11
Data Sheet Rev. 1.4 2 2001-10-18 Power Good The Power Good PG pin informs e.g. the microcontroller in case the output voltage has fallen below the lower threshold VQ,pgt-d of typ. 3.65 V. Connecting the regulator to a battery voltage at first the power good signal remains LOW. When the output voltage has reached the higher threshold VQ,pgt-i the power good output remains still LOW for the power good delay time trd. Afterwards the power good output turns HIGH. The delay time can be set by the user with an external capacitor at pin D according to the requirements of the application. The Power Good circuitry supervises the output voltage. In case VQ falls below the lower Power Good switching threshold VQ,pgt-d the PG output is set LOW after the Power Good reaction time. The Power Good LOW signal is generated down to an output voltage VQ to 1 V. A LOW signal at the Power Good pin informs that the battery was lost and memory is no longer valid. The feature should be used in combination with a microcontroller with internal reset. Figure 1 Block Diagram AEB02823 Current and Saturation Control Band- Gap- Reference TLE 4290 Power Good Control PG QI DGND
Data Sheet Rev. 1.4 3 2001-10-18 TLE 4290 Figure 2 Pin Configuration (top view) Pin Definitions and Functions Pin No. Symbol Function 1I Input; block to ground directly at the IC with a ceramic capacitor. 2P G Power Good; open collector output. Add a pull up resistor of > 5 kΩ to pin Q. 3G N D Ground; Pin 3 internally connected to heatsink. 4D Delay; connect a capacitor to GND for setting power good delay time. 5Q Output; block to ground with a capacitor, C ≥ 22 µF ESR < 5 Ω at 10 kHz. AEP02827 I PG Q DGND AEP02826 GND PG I Q D AEP02825 PG D QI GND P-TO252-5-1 (D-PAK) P-TO263-5-1 (SMD) P-TO220-5-11
Data Sheet Rev. 1.4 4 2001-10-18 Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings Parameter Symbol Limit Values Unit Test Condition min. max. Input I Voltage VI – 42 45 V – Current II ––– Internally limited Output Q Voltage VQ – 1.0 16 V – Current IQ ––– Internally limited Power Good Output PG Voltage VPG – 0.3 25 V – Current IPG – 55 m A – Delay D Voltage VD – 0.3 7 V – Current ID – 22 m A – Temperature Junction temperature Tj – 40 150 °C – Storage temperature Tstg – 50 150 °C –
Data Sheet Rev. 1.4 5 2001-10-18 TLE 4290 Note: In the operating range, the functions given in the circuit description are fulfilled. Operating Range Parameter Symbol Limit Values Unit Remarks min. max. Input voltage VI 5.5 42 V – Junction temperature Tj – 40 150 °C – Thermal Resistance Junction case Rthj-c – 4K / W – Junction ambient Rthj-a – 53 K/W TO263 1) Junction ambient Rthj-a – 78 K/W TO252 1) Junction ambient Rthj-a – 65 K/W TO220 1) Worst case, regarding peak temperature; zero airflow; mounted on a PCB FR4, 80 × 80 × 1.5 mm3, heat sink area 300 mm2
Data Sheet Rev. 1.4 6 2001-10-18 Characteristics VI = 13.5 V; – 40 °C< Tj <1 5 0°C (unless otherwise specified) Parameter Symbol Limit Values Unit Measuring Conditionmin. typ. max. Output Output voltage VQ 4.9 5.0 5.1 V 5m A< IQ <4 0 0m A ; 6V< VI <2 8V Output voltage VQ 4.9 5.0 5.1 V 5m A< IQ <2 0 0m A ; 6V< VI <4 0V Output current limitation IQ 450 700 – mA 1) Current consumption; Iq = II – IQ Iq – 200 230 µA IQ =1m A ; Tj =2 5 °C Current consumption; Iq = II – IQ Iq – 200 255 µA IQ =1m A ; Tj ≤ 85 °C Current consumption; Iq = II – IQ Iq – 51 2 m A IQ =2 5 0m A Current consumption; Iq = II – IQ Iq – 12 25 mA IQ =4 0 0m A Drop voltage Vdr – 250 500 mV IQ =3 0 0m A Vdr = VI – VQ Load regulation ∆VQ, lo – 30 15 30 mV VI =6V ; IQ = 5 mA to 400 mA Line regulation ∆VQ, li – 15 5 15 mV Vl = 8 V to 32 V; IQ =5m A Power supply ripple rejection PSRR – 60 – dB fr =1 0 0H z ; Vr =0 . 5V p p Temperature output voltage drift – 0.5 – mV/K – Output Capacitor CQ 22 –– µFE S R < 5 Ω in the operation range Power Good Output PG and Delay Timing D Power Good switching threshold VQ,pgt-i 4.45 4.65 4.80 V VQ increasing dVQ
Data Sheet Rev. 1.4 7 2001-10-18 TLE 4290 Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at Ta = 25 °C and the given supply voltage. Figure 3 Test Circuit Power Good switching threshold VQ,pgt-d 3.50 3.65 3.80 V VQ decreasing Power Good output low voltage VPGL – 0.2 0.4 V RPG ≥ 5k Ω; VQ > 1 V Power Good output leakage current IPGH – 02 µA VPG > 4.5 V Power Good charging current ID,c 369 µA VD = 1 V Upper timing threshold VDU 1.5 1.8 2.2 V – Lower timing threshold VDL 0.60 0.85 1.10 V – Power Good delay time trd 10 16 22 ms CD = 47 nF Power Good reaction time trr 0.2 0.5 2.0 µs CD = 47 nF 1) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5 V. Characteristics (cont’d) VI = 13.5 V; – 40 °C< Tj <1 5 0°C (unless otherwise specified) Parameter Symbol Limit Values Unit Measuring Conditionmin. typ. max. AES02824 TLE 4290 GND ID CI2 100 nF CI1 1000 µF CD 47 nF ID,C II VI IQ RPG 5 k VQ IGND VPG CQ 22 µF Q PG I D 4
Data Sheet Rev. 1.4 8 2001-10-18
Application Information
Figure 4 Application Diagram Input, Output An input capacitor is necessary for damping line influences. A resistor of approx. 1 Ω in series with CI, can damp the LC of the input inductivity and the input capacitor. The TLE 4290 requires an output capacitor of at least 22 µF with an ESR below 5 Ω for stability. Power Good The Power Good pin informs e.g. the micro-controller in case the output voltage has fallen below a threshold of typ. 3.65 V. When the battery voltage is supplied the Power Good signal indicates a loss of memory due to missing power. After the Memory Good switching threshold is reached the Power Good output remains low for the Power Good delay time. This time can be set by the user with an external capacitor at pin D according to the requirements of the application, e.g. the time until the microcontroller is initialized and ready to receive any information. AES02822 Current and Saturation Control Band- Gap- Reference TLE 4290 Power Good Control CI1 CI2 VBAT CD 47 nF GND RPG 5 k µF µ-Controller VCC NMI / PORT Internal Reset D PG Q 100 nF CQ2CQ1
Data Sheet Rev. 1.4 9 2001-10-18 TLE 4290 The power good circuit supervises the output voltage. In case VQ falls below the Power Good switching threshold the Power Good output PG is set LOW after the power good reaction time. The power good LOW signal is generated down to an output voltage VQ to 1 V. A LOW signal at the power good pin informs that the battery was lost and memory is no longer valid. The feature should only be used in combination to a microcontroller with internal reset. For the power good delay time after the output voltage of the regulator is above the reset threshold, the reset signal is set High again. The reset delay time is defined by the reset delay capacitor CD at pin D. The Power Good delay time is defined by the charging time of an external delay capacitor CD. CD= (trd × ID,c) / ∆V With CD Power Good delay capacitor trd Power Good delay time ∆V = VDU, typical 1.8 V ID,c Charge current typical 6 µA Figure 5 Power Good Timing AED03074 Thermal t rd Power-on Voltage Dip Secondary Overload at OutputSpike VDL VΙ VD VPG D, cΙ Vd dt VQ t rr< rrt VDU at Input Undervoltage Shutdown CD Power Good Signal Q,pgt_dV Q,pgt_iV
Data Sheet Rev. 1.4 10 2001-10-18 The power good reaction time trr is the time it takes the voltage regulator to set power good output PG LOW after the output voltage has dropped below the power good switching threshold. It is typically 0.5 µs for delay capacitor of 47 nF. For other values for CD the reaction time can be estimated using the following equation: trr = 10 ns/nF × CD The Power Good output is an open collector output. It requires externally a pull up resistor of at least 5 kΩ to Q. Typical Performance Characteristics Output Voltage VQ versus Temperature Tj Output Voltage VQ versus Input Voltage VI AED03033 -40 04 0 8 04.6 jT QV VI = 13.5 V 4.7 4.8 4.9 5.0 5.1 V 5.2 ˚C 160120 R 40 2 QV V 10V68 V Ι AED01929 = 25L Ω
Data Sheet Rev. 1.4 11 2001-10-18 TLE 4290 Output Current IQ versus Temperature Tj Current Consumption Iq versus Output Current IQ; Tj =2 5 °C Output Current IQ versus Input Voltage VI Current Consumption Iq versus Output Current IQ AED03034 -40 04 0 8 0 120 ˚C 1600 jT 200 400 600 800 1000 mA 1200 QI AED03112 Ι q 0.8 1.6 mA 2.4 = 13.5 V mA ΙV 20 40 60 80 120 QΙ 2.0 0.4 1.2 AED03046 0 10 20 30 40 V5 00 0.4 0.8 1.2 A 1.0 0.6 0.2 IV IQ = 125 ˚CTj 25 ˚C AED03035 Ι q mA = 13.5 V mA ΙV 100 200 300 400 600 QΙ
Data Sheet Rev. 1.4 12 2001-10-18 TLE 4290 Drop Voltage Vdr versus Output Current IQ Upper Timing Threshold VDU versus Temperature Tj Charge Current ID,c versus Temperature Tj AED01935 QI 100 200 300 400 500 600 700 800 mVVdr jT = 125 ˚C 25 ˚C 200 400 600 1000mA -40 AED03037 VDU mA = 13.5 V ΙV jT 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 04 0 80 120 160 AED03036 -400 IV = 13.5 V µA 04 0 8 0 120 160˚C I Tj = 1 VDV D, c
Data Sheet Rev. 1.4 13 2001-10-18 TLE 4290 Package Outlines P-TO252-5-1 (D-PAK) (Plastic Transistor Single Outline) GPT09161 5.4 ±0.1 -0.106.5+0.15 A ±0.59.9 6.22-0.2 1±0.1 ±0.150.8 0.15 max ±0.1per side 5x0.6 1.14 4.56 +0.08 -0.040.9 2.3 -0.10 +0.05 B 0.51 min ±0.11 +0.08 -0.040.5 0...0.15 BA0.25 M 0.1 All metal surfaces tin plated, except area of cut. (4.17) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mmSMD = Surface Mounted Device
Data Sheet Rev. 1.4 14 2001-10-18 A 8˚ max. BA0.25 M 0.1 Typical 9.8±0.15 ±0.210 8.5 1) 7.55 1) (15) ±0.29.25 ±0.31 0...0.15 5x0.8±0.1 ±0.11.27 4.4 B 0.5±0.1 ±0.32.7 4.7±0.5 0.05 0.1 All metal surfaces tin plated, except area of cut. 2.4 4x1.7 P-TO263-5-1-1 (SMD) (Plastic Transistor Single Outline) gpt09113_malac Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mmSMD = Surface Mounted Device
Data Sheet Rev. 1.4 15 2001-10-18 TLE 4290 gpt09064_ma A A0.25 M Typical 9.8±0.15 2.8 15.65±0.3 12.95 0...0.15 1.7 0.8±0.1 ±0.11.27 4.4 9.25±0.20.05 All metal surfaces tin plated, except area of cut. C ±0.2 17±0.3 8.51) 10±0.2 3.7-0.15 C 2.4 0.5±0.1 ±0.38.6 10.2 ±0.3 ±0.43.9 ±0.48.4 3.7±0.3 P-TO220-5-11 (Plastic Transistor Single Outline) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mm
Data Sheet Rev. 1.4 16 2001-10-18
Data Sheet Rev. 1.4 17 2001-10-18 TLE 4290
Data Sheet Rev. 1.4 18 2001-10-18 TLE 4290 Edition 2001-10-18 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be consid- ered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descrip- tions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, deliv- ery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technolo- gies Representatives worldwide (see ad- dress list). Warnings Due to technical requirements components may contain dangerous substances. For in- formation on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the fail- ure of that life-support device or system, or to affect the safety or effectiveness of that de- vice or system. Life support devices or sys- tems are intended to be implanted in the hu- man body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.