Q67000-A9284-X201-K5

TDA16888 SIEMENS | Alldatasheet

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High Performance Power Combi Controller TDA 16888 Semiconductor Group 1 Data Sheet 1998-05-06 1O v e r v i e w

1.1 Features

– IEC 1000-3 compliant – Additional operation mode as auxiliary power supply – Fast, soft switching totem pole gate drive (1 A) – Dual loop control (average current and voltage sensing) – Leading edge triggered pulse width modulation – Peak current limitation – Topologies of PFC preconverter are boost or flyback – Continuous/discontinuous mode possible – 94% maximum duty cycle PWM Section – Improved current mode control – Fast, soft switching totem pole gate drive (1 A) – Soft-start management – Trailing edge triggered pulse width modulation – Topologies of PWM converter are feed forward or flyback – 50% maximum duty cycle to prevent transformer saturation fPWM = fPFC t New type Type Ordering Code Package t TDA 16888 Q67000-A9284-X201-K5 P-DIP-20-5 t TDA 16888G Q67000-A9310-A702 P-DSO-20-1

Semiconductor Group 2 Data Sheet 1998-05-06 Special Features – High power factor –T y p i c a l 5 0mA start-up supply current – Low quiescent current (15 mA) – Undervoltage lockout with internal stand-by operation – Internally synchronized fixed operating frequency ranging from 15 kHz to 200 kHz – External synchronization possible – Shutdown of both outputs externally triggerable – Peak current limitation – Overvoltage protection – Average current sensing by noise filtering

1.2 General Remarks

The TDA 16888 comprises the complete control for power factor controlled switched mode power supplies. With its PFC and PWM section being internally synchronized, it applies for off-line converters with input voltages ranging from 90 V to 270 V. While the preferred topologies of the PFC preconverter are boost or flyback, the PWM section can be designed as forward or flyback converter. In order to achieve minimal line current gaps the maximum duty cycle of the PFC is about 94%. The maximum duty cycle of the PWM, however, is limited to 50% to prevent transformer saturation.

Semiconductor Group 3 Data Sheet 1998-05-06 Figure 1 Pin Configuration (top view) PFC CL GND PFC OUT SYNC PWM SS PWM IN V ROSC PFC VC PFC VS AUX VS REF PWM RMP 201 192 183 174 165 156 147 138 129 AEP02461 PFC CC PFC CS PWM OUT PWM CS PFC IAC 1110 GND S CCV PFC FB AEP02486 VCC GND S PFC IAC PWM OUT PFC CS PFC CC REFV PFC OUT GND PFC CL PFC FB PWM CS PWM RMP AUX VS PFC VS PFC VC ROSC PWM IN PWM SS SYNC P-DSO-20-1P-DIP-20-5

Semiconductor Group 4 Data Sheet 1998-05-06

1.3 Pin Definitions and Functions

Pin No. Symbol Function

1 PFC IAC AC line voltage sensing input

2 VREF 7.5 V reference

3 PFC CC PFC current loop compensation

4 PFC CS PFC current sense

5 GND S Ground sensing input

6 PFC CL Sensing input for PFC current limitation

7 GND Ground

8 PFC OUT PFC driver output

10 PWM OUT PWM driver output

11 PWM CS PWM current sense

12 SYNC Oscillator synchronization input

13 PWM SS PWM soft-start

14 PWM IN PWM output voltage sensing input

15 PWM RMP PWM voltage ramp

16 ROSC Oscillator frequency set-up

17 PFC FB PFC voltage loop feedback

18 PFC VC PFC voltage loop compensation

19 PFC VS PFC output voltage sensing input

20 AUX VS Auxiliary power supply voltage sense

Semiconductor Group 5 Data Sheet 1998-05-06

1.4 Block Diagram

1.2 V D1 D2 5 V D3 D4

5.5 V 1 V

5.5 V 0.4 V C10 10 k 1.5 V Osc 0.45 V 6 V 7.4 V Undervoltage Lockout

11 V-14 V

7.5 V (Output Disable)

17.5 V PWM Bias Control OTA3 OTA1 R S R S PFC 18 4 VS AUX S GND CC PFC VS PFC CL PFC OUT PFC V SYNC ROSC PWM SS IN PWM RMP PWM CS PWM GND OUT PWM FB VC PFC PFC CSIAC PFC 1 8 REF CC V R 2 10 kW OP1 M 2 Q M OP2 C1 OTA2 1 V FF1 Z1V S V S SV 30 mA C50.4 V C9OP3 W R 1 R 3 100 kW V S FF2C7 1 V + _ + _ _ _

Semiconductor Group 6 Data Sheet 1998-05-06

2 Functional Description

The TDA 16888 is protected against overvoltages typically above 17.5 V by an internal Zener diode Z3 at pin 9 (VCC ) and against electrostatic discharging at any pin by special ESD circuitry. By means of its power management the TDA 16888 will switch from internal stand-by, which is characterized by negligible current consumption, to operation mode as soon as a supply voltage threshold of 14 V at pin 9 (VCC ) is exceeded. To avoid uncontrolled ringing at switch-over an undervoltage lockout is implemented, which will cause the power management to switch from operation mode to internal stand-by as soon as the supply voltage falls below a threshold of 11 V. Therefore, even if the supply voltage will fall below 14 V, operation mode will be maintained as long as the supply voltage is well above 11 V. As soon as the supply voltage has stabilized, which is determined by the TDA 16888’s power management and its soft-start feature at pin 13 (PWM SS), the PWM section will be enabled by means of its internal bias control. Protection Circuitry Both PFC and PWM section are equipped with a fast overvoltage protection (C6) sensing at pin 19 (PFC VS), which when being activated will immediately shut down both gate drives. In addition to improve the PFC section’s load regulation it uses a fast but soft overvoltage protection (OTA2) prior to the one described above, which when being activated will cause a well controlled throttling of the multiplier output Q M . In case an undervoltage of the PFC output voltage is detected at pin 19 (PFC VS) by comparator C4 the gate drive of the PWM section will be shut down in order to reduce the load current and to increase the PFC output voltage. This undervoltage shutdown has to be prior to the undervoltage lockout of the internal power management and therefore has to be bound to a threshold voltage at pin 9 ( VCC ) well above 11 V. In order to prevent the external circuitry from destruction the PFC output PFC OUT (pin 8) will immediately be switched off by comparator C2, if the voltage at pin 19 (PFC VS) drops to ground caused by a broken wire. In a similar way measures are taken to handle a broken wire at any other pin in order to ensure a safe operation of the IC and its adjoining circuitry. If necessary both outputs, PFC OUT (pin 8) and PWM OUT (pin 10), can be shutdown on external request. This is accomplished by shorting the external reference voltage at pin 2 ( VREF ) to ground. To protect the external reference, it is equipped with a foldback characteristic, which will cut down the output current when VREF (pin 2) is shorted (see Figure 4).

Semiconductor Group 7 Data Sheet 1998-05-06 Both PFC and PWM section are equipped with a peak current limitation, which is realized by the comparators C3 and C9 sensing at pin 6 (PFC CL) and pin 11 (PWM CS) respectively. When being activated this current limitation will immediately shut down the respective gate drive PFC OUT (pin 8) or PWM OUT (pin 10). Finally each pin is protected against electrostatic discharge. Oscillator/Synchronization The PFC and PWM clock signals as well as the PFC voltage ramp are synchronized by the internal oscillator (see Figure 18). The oscillator’s frequency is set by an external resistor connected to pin 16 (ROSC) and ground (see Figure 5). The corresponding capacitor, however, is integrated to guarantee a low current consumption and a high resistance against electromagnetic interferences. In order to ensure superior precision of the clock frequency, the clock signal CLK OSC is derived from a triangular instead of a saw-tooth signal. Furthermore to provide a clock reference CLK OUT with exactly 50% duty cycle, the frequency of the oscillator’s clock signal CLK OSC is halved by a D-latch before being fed into the PFC and PWM section respectively (see Figure 18). The ramp signal of the PFC section VPFC RMP is composed of a slowly falling and a steeply rising edge. This ramp has been reversed in contrast to the common practice, in order to simultaneously allow for current measurement at pin 5 (GND S) and for external compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC CC). The oscillator can be synchronized with an external clock signal supplied at pin 12 (SYNC). However, since the oscillator’s frequency is halved before being fed into the PFC and PWM section, a synchronization frequency being twice the operating frequency is recommended. As long as the synchronization signal is H the oscillator’s triangular signal VOSC is interrupted and its clock signal CLK OSC is H (see Figure 19 and Figure 20). However, as soon as the external clock changes from H to L the oscillator is released. Correspondingly, by means of an external clock signal supplied at pin 12 (SYNC) the oscillator frequency fOSC set by an external resistor at pin 16 (ROSC) can be varied on principle only within the range from 0.66fOSC to 2fOSC . If the oscillator has to be synchronized over a wider frequency range, a synchronization by means of the sink current at pin 16 (ROSC) has to be preferred to a synchronization by means of pin 12 (SYNC). Anyhow, please note, that pin 12 (SYNC) is not meant to permanently shutdown both PFC and PWM section. It can be used to halt the oscillator freezing the prevailing state of both drivers but does not allow to automatically shut them down. A shutdown can be achieved by shorting pin 2 ( VREF ) to ground, instead. Finally, In order to reduce the overall current consumption under low load conditions, the oscillator frequency itself is halved as long as the voltage at pin 13 (PWM SS) is less than 0.4 V (disabled PWM section).

Semiconductor Group 8 Data Sheet 1998-05-06 PFC Section At normal operation the PFC section operates with dual loop control. An inner loop, which includes OP2, C1, FF1 and the PFC’s driver, controls the shape of the line current by average current control enabling either continuous or discontinuous operation. By the outer loop, which is supported by OP1, the multiplier, OP2, C1, FF1 and the PFC's driver, the PFC output voltage is controlled. Furthermore there is a third control loop composed of OTA1, OP2, C1, FF1 and the PFC’s driver, which allows the PFC section to be operated as an auxiliary power supply even when the PWM section is disabled. With disabled PWM section, however, the PFC section is operated with half of its nominal operating frequency in order to reduce the overall current consumption. Based on a pulse-width-modulation, which is leading edge triggered with respect to the internal clock reference CLK OUT and which is trailing edge modulated according to the PFC ramp signal VPFC RMP and the output voltage of OP2 VPFC CC (see Figure 18), the PFC section is designed for a maximum duty cycle of ca. 94% to achieve minimal line current gaps. PWM Section The PWM section is equipped with improved current mode control containing effective slope compensation as well as enhanced spike suppression in contrast to the commonly used leading edge current blanking. This is achieved by the chain of operational amplifier OP3, voltage source V1 and the 1st order low pass filter composed of R1 and an external capacitor, which is connected to pin 15 (PWM RMP). For crosstalk suppression between PFC and PWM section a signal-to-noise ratio comparable to voltage mode controlled PWM’s is set by operational amplifier OP3 performing a fivefold amplification of the PWM load current, which is sensed by an external shunt resistor. In order to simultaneously perform effective slope compensation and to suppress leading spikes, which are due to parasitic capacitances being discharged whenever the power transistor is switched on, the resulting signal is subsequently increased by the constant voltage of V1 and finally fed into the 1st order low pass filter. The peak ramp voltage, that in this way can be reached, amounts to ca. 6.5 V. By combination of voltage source V1 and the following low pass filter a basic ramp (step response) with a leading notch is created, which will fully compensate a leading spike (see Figure 12) provided, the external capacitor at pin 15 (PWM RMP) and the external current sensing shunt resistor are scaled properly.

Semiconductor Group 9 Data Sheet 1998-05-06 The pulse-width-modulation of the PWM section is trailing edge modulated according to the PWM ramp signal VPWM RMP at pin 15 (PWM RMP) and the input voltage VPWM IN at pin 14 (PWM IN) (see Figure 18). In contrast to the PFC section, however, the pulse- width-modulation of the PWM section is trailing edge triggered with respect to the internal clock reference CLK OUT in order to avoid undesirable electromagnetic interference of both sections. Moreover the maximum duty cycle of the PWM is limited to 50% to prevent transformer saturation. By means of the above mentioned improved current mode control a stable pulse-width- modulation from maximum load down to no load is achieved. Finally, in case of no load conditions the PWM section may as well be disabled by shorting pin 13 (PWM SS) to ground.

Semiconductor Group 10 Data Sheet 1998-05-06

3 Functional Block Description

Both PFC and PWM section use fast totem pole gate drives at pin 8 (PFC OUT) and pin 10 (PWM OUT) respectively, which are designed to avoid cross conduction currents and which are equipped with Zener diodes (Z1, Z2) in order to improve the control of the attached power transistors as well as to protect them against undesirable gate overvoltages. At voltages below the undervoltage lockout threshold these gate drives are active low. In order to keep the switching losses of the involved power diodes low and to minimize electromagnetic emissions, both gate drives are optimized for soft switching operation. This is achieved by a novel slope control of the rising edge at each driver's output (see Figure 13). Oscillator The TDA 16888’s clock signals as well as the PFC voltage ramp are provided by the internal oscillator. The oscillator’s frequency is set by an external resistor connected to pin 16 (ROSC) and ground (see Figure 5). The corresponding capacitor, however, is integrated to guarantee a low current consumption and a high resistance against electromagnetic interferences. In order to ensure superior precision of the clock frequency, the clock signal CLK OSC is derived from the minima and maxima of a triangular instead of a saw-tooth signal (see Figure 18). Furthermore, to provide a clock reference CLK OUT with exactly 50% duty cycle, the frequency of the oscillator’s clock signal CLK OSC is halved by a D-latch before being fed into the PFC and PWM section respectively. The ramp signal of the PFC section VPFC RMP is composed of a slowly falling and a steeply rising edge, the latter of which is triggered by the rising edge of the clock reference CLK OUT. This ramp has been reversed in contrast to the common practice, in order to simultaneously allow for current measurement at pin 5 (GND S) and for external compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC CC). The slope of the falling edge, which in conjunction with the output of OP2 controls the pulse- width-modulation of the PFC output signal VPFC OUT , is derived from the current set by the external resistor at pin 16 (ROSC). In this way a constant amplitude of the ramp signal (ca. 4.5 V) is ensured. In contrast, the slope of the rising edge, which marks the minimum blanking interval and therefore limits the maximum duty cycle ton,max of the PFC output signal, is determined by an internal current source. In contrast to the PFC section the ramp signal of the PWM section is trailing edge triggered with respect to the internal clock reference CLK OUT to avoid undesirable electromagnetic interference of both sections. Moreover, the maximum duty cycle of the PWM is limited by the rising edge of the clock reference CLK OUT to 50% to prevent transformer saturation.

Semiconductor Group 11 Data Sheet 1998-05-06 The oscillator can be synchronized with an external clock signal supplied at pin 12 (SYNC). As long as this clock signal is H the oscillator’s triangular signal VOSC is interrupted and its clock signal CLK OSC is H (see Figure 19 and Figure 20). However, as soon as the external clock changes from H to L the oscillator is released. Correspondingly, by means of an external clock signal supplied at pin 12 (SYNC) the oscillator frequency fOSC set by an external resistor at pin 16 (ROSC) can be varied on principle only within the range from 0.66fOSC to 2fOSC . Please note, that the slope of the falling edge of the PFC ramp is not influenced by the synchronization frequency. Instead the lower voltage peak is modulated. Consequently, on the one hand at high synchronization frequencies fSYNC > fOSC the amplitude of the ramp signal and correspondingly its signal-to-noise ratio is decreased (see Figure 19). On the other hand at low synchronization frequencies fSYNC < fOSC the lower voltage peak is clamped to the minimum ramp voltage (typ. 1.1 V), that at least can be achieved (see Figure 20), which may cause undefined PFC duty cycles as the voltage VPFC CC at pin 3 (PFC CC) drops below this threshold. However, if the oscillator has to be synchronized over a wide frequency range, a synchronization by means of the sink current at pin 16 (ROSC) has to be preferred to a synchronization by means of pin 12 (SYNC). In order to reduce the overall current consumption under low load conditions, the oscillator frequency itself is halved as long as the voltage at pin 13 (PWM SS) is less than 0.4 V (disabled PWM section). Multiplier The multiplier serves to provide the controlled current IQM by combination of the shape of the sinusoidal input current IM1 derived from the voltage at pin 1 (PFC IAC) by means of the 10 kW resistor R2, the magnitude of the PFC output voltage VM2 given at pin 18 (PFC VC) and the possibility for soft overvoltage protection VM3 (see Chapter Protection Circuitry). By means of this current the required power factor as well as the magnitude of the PFC output voltage is ensured. To achieve an excellent performance over a wide range of output power and input voltage, the input voltage VM2 is amplified by an exponential function before being fed into the multiplier (see Figure 8). Voltage Amplifier OP1 Being part of the outer loop the error amplifier OP1 controls the magnitude of the PFC output voltage by comparison of the PFC output voltage measured at pin 17 (PFC FB) with an internal reference voltage. The latter is fixed to 5 V in order to achieve immunity from external noise. To allow for individual feedback the output of OP1 is connected to pin 18 (PFC VC).

Semiconductor Group 12 Data Sheet 1998-05-06 Current Amplifier OP2 Being part of the inner loop the error amplifier OP2 controls the shape of the line current by comparison of the controlled current IQM with the measured average line current. This is achieved by setting the pulse width of the PFC gate drive in conjunction with the comparator C1. In order to limit the voltage range supplied at pin 4 (PFC CS) and at pin 5 (GND S), clamping diodes D1, D2 and D3 are connected with these pins and ground. To allow for individual feedback the output of OP2 is connected to pin 3 (PFC CC). Ramp Amplifier OP3 For crosstalk suppression between PFC and PWM section a signal-to-noise ratio comparable to voltage mode controlled PWMs is set by operational amplifier OP3 performing a fivefold amplification of the PWM load current, which is sensed by an external shunt resistor. In order to suppress leading spikes, which are due to parasitic capacitances being discharged whenever the power transistor is switched on, the resulting signal is subsequently increased by the constant voltage of V1 and finally fed into a 1st order low pass filter. By combination of voltage source V1 and the following low pass filter a step response with a leading notch is created, which will fully compensate a leading spike (see Figure 12) provided, the external capacitor at pin 15 (PWM RMP) and the external current sensing shunt resistor are scaled properly. Operational Transconductance Amplifier OTA1 The TDA 16888’s auxiliary power supply mode is controlled by the fast operational transconductance amplifier OTA1. When under low load or no load conditions a voltage below 5 V is sensed at pin 20 (AUX VS), it will start to superimpose its output on the output Q M of the multiplier and in this way will replace the error amplifier OP1 and the multiplier. At normal operation, however, when the voltage at pin 20 (AUX VS) is well above 5 V, this operational transconductance amplifier is disabled. Operational Transconductance Amplifier OTA2 By means of the operational transconductance amplifier OTA2 sensing at pin 19 (PFC VS) a fast but soft overvoltage protection of the PFC output voltage is achieved, which when being activated (VPFC VS > 5.5 V) will cause a well controlled throttling of the multiplier output QM (see Figure 9). Operational Transconductance Amplifier OTA3 In order to achieve offset compensation of error amplifier OP2 under low load conditions, that will not suffice to start OTA1, the operational transconductance amplifier OTA3 is introduced. It will start operation as soon as these conditions are reached, i.e. the voltage at pin 18 (PFC VC) falls below 1.2 V.

Semiconductor Group 13 Data Sheet 1998-05-06 Comparator C1 The comparator C1 serves to adjust the duty cycle of the PFC gate drive. This is achieved by comparison of the output voltage of OP2 given at pin 3 (PFC CC) and the voltage ramp of the oscillator. Comparator C2 The comparator C2 serves to prevent the external circuitry from destruction by immediately switching the PFC output PFC OUT (pin 8) off, if the voltage at pin 19 (PFC VS) drops below 1 V due to a broken wire. Comparator C3 By means of this extremely fast comparator sensing at pin 6 (PFC CL) peak current limitation is realized. When being activated ( VPFC CL < 1 V) it will immediately shut down the gate drive of the PFC section (pin 8, PFC OUT). In order to protect C3 against undervoltages at pin 6 (PFC CL) due to large inrush currents, this pin is equipped with an additional clamping diode D4. Comparator C4 This comparator along with the TDA 16888’s power management serves to reset the PWM section’s soft start at pin 13 (PWM SS). C4 becomes active as soon as an undervoltage (VPFC VS < 4 V) of the PFC output voltage is sensed at pin 19 (PFC VS). Comparator C5 Based on the status of the PWM section’s soft start at pin 13 (PWM SS), the comparator C5 controls the bias of the entire PWM section. In this way the PWM section is switched off giving a very low quiescent current, until its soft start is released. Comparator C6 Overvoltage protection of the PWM section’s input voltage sensed at pin 19 (PFC VS) is realized by comparator C6, which when being activated will immediately shut down both gate drives PFC OUT (pin 8) and PWM OUT (pin 10). Comparator C7 This comparator sensing at pin 13 (PWM SS) and at pin 15 (PWM RMP) controls the pulse width modulation of the PWM section during the soft start. This is done right after the PWM section is biased by comparator C5.

Semiconductor Group 14 Data Sheet 1998-05-06 Comparator C8 The control of the pulse width modulation of the PWM section is taken over by comparator C8 as soon as the soft start is finished. This is achieved by comparison of the PWM output voltage at pin 14 (PWM IN) and the PWM voltage ramp at pin 15 (PWM RMP). Comparator C9 By means of this extremely fast comparator sensing at pin 11 (PWM CS) peak current limitation is realized. When being activated ( VPWM CS > 1 V) it will immediately shut down the gate drive of the PWM section (PWM OUT). Comparator C10 By means of the threshold of 0.4 V the comparator C10 allows the PWM duty cycle to be continuously controlled from 0 to 50%. As long as the ramp voltage at pin 15 (PWM RMP) is below this threshold the gate drive of the PWM section (pin 10, PWM OUT) is turned off.

Semiconductor Group 15 Data Sheet 1998-05-06

4 Electrical Characteristics

4.1 Absolute Maximum Ratings

TA = – 25 to 85°C Parameter# Symbol Limit Values Unit Remarks min. max. VCC supply voltage VS –0 . 3VZ3 V VZ3 = Zener voltage of Z3 Zener current of Z3 IZ3 –5 0 m A – VREF voltage VVREF – 0.3 8 V VVREF < VS ROSC voltage VROSC – 0.3 8 V VROSC < VS SYNC voltage VSYNC – 0.3 8 V – PFC FB voltage VPFC FB – 0.3 8 V – PFC IAC voltage VPFC IAC – 0.3 15 V – AUX VS voltage VAUX VS – 0.3 8 V – PFC VS voltage VPFC VS – 0.3 8 V | IPFC VS |<1m A PFC CL voltage VPFC CL – 0.3 3 V – PWM SS voltage VPWM SS – 0.3 8 V VPWM SS < VVREF PWM IN voltage VPWM IN – 0.3 8 V – PWM RMP voltage VPWM RMP – 0.3 8 V VPWM RMP < VVREF PWM CS voltage VPWM CS – 0.3 3 V – PFC VC voltage VPFC VC – 0.3 8 V – PFC VC current IPFC VC – 20 20 mA – PFC CS current IPFC CS – 5 5 mA – GND S current IGND S – 5 5 mA – PFC CC voltage VPFC CC – 0.3 8 V – PFC CC current IPFC CC – 20 20 mA – PFC/PWM OUT DC current IOUT – 100 100 mA – PFC/PWM OUT peak clamping current IOUT –2 0 0 m A VOUT =H i g h PFC/PWM OUT peak clamping current IOUT –5 0 0 – m A VOUT = Low Junction temperature TJ –4 0 1 5 0 °C–

Semiconductor Group 16 Data Sheet 1998-05-06 Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. To avoid destruction make sure, that for any pin except for pins PFC OUT and PWM OUT the currents caused by transient processes stay well below 100 mA. For the same reason make sure, that any capacitor that will be connected to pin 9 (VCC ) is discharged before assembling the application circuit. In order to characterize the gate driver’s output performance Figure 14, Figure 15, Figure 16 and Figure 17 are provided, instead of referring just to a single parameter like the maximum gate charge or the maximum output energy. Note: Within the operating range the IC operates as described in the functional description. In order to characterize the gate driver’s output performance Figure 14, Figure 15, Figure 16 and Figure 17 are provided, instead of referring just to a single parameter like the maximum gate charge or the maximum output energy. Storage temperature TS –6 5 1 5 0 °C– Thermal resistance RthJA – 60 K/W P-DIP-20-5 Thermal resistance RthJA –7 0 K / W P - D S O - 2 0 - 1

4.2 Operating Range

Parameter Symbol Limit Values Unit Remarks min. max. VCC supply voltage VS 0 VZ3 V VZ3 = Zener voltage of Z3 Zener current IZ3 0 50 mA Limited by TJ,max PFC/PWM OUT current IOUT –1 1 . 5 A – PFC IAC input currentIPFC IAC 01m A – PFC/PWM frequency fOUT 15 200 kHz – Junction temperature TJ –2 5 1 2 5 °C–

4.1 Absolute Maximum Ratings (cont’d)

TA = – 25 to 85°C Parameter# Symbol Limit Values Unit Remarks min. max.

Semiconductor Group 17 Data Sheet 1998-05-06

4.3 Characteristics

Note: The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range TA from – 25°C to 85°C Typical values represent the median values, which are related to production processes. If not otherwise stated, a supply voltage of VS =1 5V i s a s s u m e d . 1) See Figure 3 2) Design characteristics (not meant for production testing) Supply Section Parameter Symbol Limit Values Unit Test Condition min. typ. max. Zener voltage1) VZ3 16.0 17.5 19.0 V IZ3 =3 0m A Zener current IZ3 ––5 0 0 mA VS £ 15.5 V2) Quiescent supply current IS ––1 2 m A VPWM SS =0V RROSC =5 1kW C L =0V PFC enabled PWM disabled ––1 5 m A VPWM SS =6V RROSC =5 1kW C L =0F PFC enabled PWM enabled Supply current IS ––4 0 m A VPWM SS =6V RROSC =5 1kW C L =4 . 7n F PFC enabled PWM enabled

Semiconductor Group 18 Data Sheet 1998-05-06 1) See Figure 3 2) To ensure the voltage fallback of pin PFC CL is disabled. Undervoltage Lockout Parameter Symbol Limit Values Unit Test Condition min. typ. max. Power up, rising voltage threshold1) VS,UP 13.0 14.0 14.5 V – Power down, falling voltage threshold VS,DWN 10.5 11.0 11.5 V – Power up, threshold current IS,UP – 23 100 mA VS = VS,UP –0 . 1V VPFC CL <0 . 3V2) Stand-by mode Internal Voltage Reference Parameter Symbol Limit Values Unit Test Condition min. typ. max. Trimmed reference voltage VREF 4.9 5.0 5.1 V Measured at pin PFC VC Line regulation DVREF ––4 0 m V DVS =3V

Semiconductor Group 19 Data Sheet 1998-05-06 1) See Figure 4 2) Design characteristics (not meant for production testing) 3) Transient reference value 1) See Figure 5 External Voltage Reference Parameter Symbol Limit Values Unit Test Condition min. typ. max. Buffered output voltageVVREF 7.2 7.5 7.8 V –3m A £ IVREF £ 0 Line regulation DVVREF ––5 0 m V DVS =3V Load regulation DVVREF 04 0 1 0 0 m V DIVREF =2m A Maximum output current1) IVREF – 1 0 – 6– 4m A VVREF =6 . 5V Short circuit current1) IVREF –– 2 –m A VVREF =0V Shutdown hysteresis, rising voltage threshold VVREF –6 . 6 –V– Shutdown hysteresis, falling voltage threshold VVREF –6 . 2 –V – Shutdown delay td,VREF –5 0 0 –n s VVREF =5V 2)3) VPFC OUT =3V 2)3) VPWM OUT =3V 2)3) Oscillator Parameter Symbol Limit Values Unit Test Condition min. typ. max. PFC/PWM frequency1) fOUT50 43 50 57 kHz RROSC =1 1 0kW PFC/PWM frequency1) fOUT100 87 100 113 kHz RROSC =5 1kW PFC/PWM frequency, line regulation DfOUT ––1% DVS =3V RROSC =5 1kW Maximum ramp voltage VPFC RMP 5.0 5.4 5.6 V – Minimum ramp voltage VPFC RMP 0.8 1.1 1.4 V – SYNC, low level voltageVSYNC ––0 . 4 V – SYNC, high level voltageVSYNC 3.5 – VVREF V– SYNC, input current ISYNC ––2 0 mA VSYNC <0 . 4V – – 150 mA VSYNC =3 . 5V

Semiconductor Group 20 Data Sheet 1998-05-06 1) See Figure 6 2) See Figure 9 3) Transient reference value 4) Design characteristics (not meant for production testing) PFC Section Parameter Symbol Limit Values Unit Test Condition min. typ. max. Max duty cycle1) D on,PFC 91 94 98 % VPFC OUT =2V 3) RROSC =5 1kW C L =4 . 7n F Multiplier throttling (OTA2), threshold voltage2) VPFC VS 5 . 25 . 55 . 8V 0 . 9 IPFC CS IPFC IAC = 100mA VPFC VC =6V OTA1 disabled Overvoltage protection (C6), rising voltage threshold VPFC VS 5 . 86 6 . 2V – Overvoltage protection (C6), falling voltage threshold VPFC VS 5 . 35 . 55 . 7V – Overvoltage protection (C6), turn-off delay td,OV –2– ms VPFC VS =6 . 5V3)4) VPFC OUT =3V 3)4) Broken wire detection (C2), threshold voltage VPFC VS 0.93 1 1.07 V – Voltage sense, input current IPFC VS 0.2 0.45 0.7 mA VPFC VS =1V Current limitation (C3), threshold voltage VPFC CL 0.93 1 1.07 V – Current limitation (C3), input current IPFC CL 1–1 0 mA VPFC CL =1V Current limitation (C3, D4), clamping voltage VPFC CL – 0.9 – – 0.1 V IPFC CL =–5 0 0mA Current limitation (C3), turn-off delay td,CL 30 – 150 ns VPFC CL =0 . 7 5V3) VPFC OUT =3V 3) C L =4 . 7n F

Semiconductor Group 21 Data Sheet 1998-05-06 1) Design characteristics (not meant for production testing) 2) For input voltages below this threshold the multiplier output current remains constant. For input voltages above this threshold the output rises exponentially (see Figure 8). 3) See Figure 7 Multiplier Parameter Symbol Limit Values Unit Test Condition min. typ. max. Input current IPFC IAC 0 –1m A – Input voltage VPFC VC 0–6 . 7 V– Exponential function, threshold voltage VPFC VC –1 . 1 –V 1)2) Maximum output currentIPFC CS – 320 – 420 – 550 mA OTA1 disabled Output current3) IPFC CS – – 100 – 500 nA IPFC IAC =0A VPFC VC =2V OTA1 disabled –– 1 . 2 – mA IPFC IAC =2 5mA VPFC VC =2V OTA1 disabled –– 1 0 – mA IPFC IAC =2 5mA VPFC VC =4V OTA1 disabled –– 4 0 – mA IPFC IAC =1 0 0mA VPFC VC = 4 V OTA1 disabled –– 1 5 0 – mA IPFC IAC =4 0 0mA VPFC VC =4V OTA1 disabled –– 1 7 0 – mA IPFC IAC =1 0 0mA VPFC VC =6V OTA1 disabled

Semiconductor Group 22 Data Sheet 1998-05-06 1) For input voltages below this threshold the output current is linearly increasing until at ca. 4.8 V the maximum output current is reached. 1) Design characteristics (not meant for production testing) Operational Transconductance Amplifier (OTA1) Parameter Symbol Limit Values Unit Test Condition min. typ. max. Auxiliary power supply, threshold voltage1) VAUX VS 4.8 5.0 5.2 V IPFC CS =–1 mA Multiplier disabled Input current IAUX VS – –1 5 mA VAUX VS >5 . 2V –2 0 – – mA VAUX VS <4 . 8V Output current IPFC CS –0– mA VAUX VS >5 . 2V1) –– 3 0 – mA VAUX VS <4 . 8V Operational Transconductance Amplifier (OTA3) Parameter Symbol Limit Values Unit Test Condition min. typ. max. Offset compensation, threshold voltage VPFC VC 1.1 1.2 – V – Input current IPFC VC – 1 – – mA 1) Output current IGND S –0– mA VPFC VC >1 . 2V –– 1 0 – mA VPFC VC <1 . 1V

Semiconductor Group 23 Data Sheet 1998-05-06 1) Guaranteed by wafer test 2) Design characteristics (not meant for production testing) Voltage Amplifier (OP1) Parameter Symbol Limit Values Unit Test Condition min. typ. max. Offset voltage VOff –4 – 4 m V 1) Input current IPFC FB –1 – 1 mA VPFC FB =4V Open loop gain APFC VC –8 5 –d B 2) Input voltage range VPFC FB 0–6V– Voltage sense, threshold voltage VPFC FB 4.9 5 5.1 V – Output, maximum voltage VPFC VC 6.3 – VVREF V IPFC VC =–5 0 0mA Output, minimum voltage VPFC VC 0.5 – 1.1 V IPFC VC =5 0 0mA Output, short circuit source current IPFC VC –– 1 0 –m A VPFC VC =0V VPFC FB =4 . 9V Output, short circuit sink current IPFC VC –1 0 –m A VPFC VC =6 . 4V VPFC FB =5 . 1V

Semiconductor Group 24 Data Sheet 1998-05-06 1) Design characteristics (not meant for production testing) Current Amplifier (OP2) Parameter Symbol Limit Values Unit Test Condition min. typ. max. Offset voltage VOff –5 –1 3 m V – Input current IPFC CS IGND S – 500 – 500 nA – Open loop gain APFC CC –1 1 0 –d B – Gain bandwidth productfT –2 . 5 –M H z 1) Phase margin j –6 0 –° 1) Common mode voltage range VCMVR –0 . 2 – 0 . 5 V 1) Clamped input voltage, upper threshold (D2, D3) VPFC CS VGND S 0.4 – 1.0 V IPFC CS =5 0 0mA IGND S = 500mA Multiplier, OTA1 and OTA3 disabled Clamped input voltage, lower threshold (D1) VPFC CS –0 . 9 – –0 . 1 V IPFC CS =–5 0 0mA Multiplier and OTA1 disabled Output, maximum voltage VPFC CC 6.3 – VVREF V IPFC CC = – 500mA Output, minimum voltage VPFC CC 0.5 – 1.1 V IPFC CC =5 0 0mA Output, short circuit source current IPFC CC –– 1 0 –m A VPFC CC =0V VPFC CS =0V VGND S =0 . 5V Output, short circuit sink current IPFC CC –1 0 –m A VPFC CC =6 . 5V VPFC CS =0 . 5V VGND S =0V

Semiconductor Group 25 Data Sheet 1998-05-06 1) Transient reference value PWM Section Parameter Symbol Limit Values Unit Test Condition min. typ. max. Undervoltage protection (C4), threshold voltage VPFC VS 3.8 4.0 4.2 V – Bias control (C5), rising voltage threshold VBC,Th –0 . 4 5 –V – Bias control (C5), falling voltage threshold VBC,Th –0 . 4 –V – Softstart (I1), charging current II1 20 30 40 mA– Softstart, maximum voltageVPWM SS –6 . 7 –V – Input voltage VPWM IN 0.4 – 7.4 V – PWM IN – GND resistance R3 75 100 150 k W – Ramp (OP3), voltage gain AOP3 –5–V / V – Ramp (C10), pulse start threshold voltage VRMP 0.36 0.4 0.5 V – Ramp, maximum voltage VRMP –6 . 5 –V – Ramp (V1), voltage offsetVV1 –1 . 5 –V – Ramp (R1), output impedance ZRMP –1 0 –k W – Maximum duty cycle D on,PWM 41 – 50 % VPWM OUT =2V 1) RROSC =5 1kW C L =4 . 7n F Current sense (C9), voltage threshold VCS,Th 0.9 1.0 1.1 V – Current sense (C9), overload turn-off delay td,CS 30 – 250 ns VPWM CS =1 . 2 5V1) VPWM OUT =3V 1) C L =4 . 7n F

Semiconductor Group 26 Data Sheet 1998-05-06 1) See Figure 13 2) Transient reference value 3) The gate driver’s output performance is characterized in Figure 14, Figure 15, Figure 16 and Figure 17. 4) Design characteristics (not meant for production testing) Gate Drive (PWM and PFC Section) Parameter Symbol Limit Values Unit Test Condition min. typ. max. Output, minimum voltage VOUT ––1 . 2 VV S =5V IOUT =5m A ––1 . 5 V VS =5V IOUT =2 0m A –0 . 8 –V IOUT =0A –1 . 6 2 . 0 V IOUT =5 0m A –0 . 2 0 . 2 – V IOUT =–5 0m A Output, maximum voltage VOUT 10 11 12 V VS =1 6V tH =1 0ms C L =4 . 7n F 10.0 10.5 – V VS =1 2V tH =1 0ms C L =4 . 7n F 8.8 – – V VS = VS,DWN +0 . 2V tH =1 0ms C L =4 . 7n F Rise time1) tr –1 5 0 –n s VOUT =2V…8V 2) C L =4 . 7n F –1 0 0 –n s VOUT =3V…6V 2) C L =4 . 7n F Fall time tf –3 0 –n s VOUT =9V…3V 2) C L =4 . 7n F –4 0 –n s VOUT =9V…2V 2) C L =4 . 7n F Output current, rising edge3) IOUT –1 – – A C L =4 . 7n F4) Output current, falling edge IOUT ––1 . 5 A C L =4 . 7n F4)

Semiconductor Group 29 Data Sheet 1998-05-06 Figure 7 Multiplier Linearity Figure 8 Multiplier Dynamic AED02466 IPFC IAC PFC CCSI 0.2 0.4 0.6 0.8 1 100 200 300 400 500 mA mA 2 V 3 V

4 V5 V6 V

= 7 VVPFC VC VPFC VC PFC CCSI 100 200 300 400 500 mA 12 3 4 5 6 7V PFC IACI mA= 800 A400 m A200 m A100 m A50 m A25 m AED02356

Semiconductor Group 34 Data Sheet 1998-05-06 Figure 17 Power Dissipation of Single Gate Driver at fOUT =2 0 0k H z AED02545 DP 10 20 30 40 50nF 0.5 1.0 1.5 mW C L R L = 0 W R L = 1W R L = 2 W R L = 5 W R L = 10 W = 200 kHzfOUT = 0.212 WP D0

Semiconductor Group 35 Data Sheet 1998-05-06 Figure 18 Timing Diagram without Synchronization AET02546 OSCV CLK OSC PFC RMPV PFC OUTV PWM RMPV PWM OUTV CLK OUT Time on, maxt on, maxt VPWM IN BC, ThV VPFC CC

Semiconductor Group 36 Data Sheet 1998-05-06 Figure 19 Timing Diagram with Synchronization (fSYNC > fOSC ) AET02547 OSCV CLK OSC PFC RMPV PFC OUTV PWM RMPV PWM OUTV CLK OUT Time on, maxt on, maxt VBC, Th PWM INV VPFC CC SYNCV

Semiconductor Group 37 Data Sheet 1998-05-06 Figure 20 Timing Diagram with Synchronization (fSYNC < fOSC ) AET02548 OSCV CLK OSC PFC RMPV PFC OUTV PWM RMPV PWM OUTV CLK OUT Time on, maxt on, maxt BC, ThV VPWM IN PFC CCV SYNCV

Semiconductor Group 38 Data Sheet 1998-05-06

5 Package Outlines

(Plastic Dual In-line Package) GPD05587 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mm

Semiconductor Group 39 Data Sheet 1998-05-06 11 0 1120 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side GPS05094 2.65 max 0.1 0.2-0.1 2.45-0.2 +0.150.35 1.27 0.2 24x -0.27.6 1) 0.35 x 45˚ 0.238˚ max +0.09 +0.8 ±0.310.3 0.4 12.8-0.2 P-DSO-20-1 (Plastic Dual Small Outline) GPS 05094 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device