Q67000-A9283

TLE5205-2 INFINEON | Alldatasheet

Document overview

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Technical content

built using the Infineon multi-technology process SPT® which allows bipolar and CMOS control circuitry plus DMOS power devices to exist on the same monolithic structure. Operation modes forward (cw), reverse (ccw), brake and high impedance are invoked from just two control pins with TTL/CMOS compatible levels. The combination of an extremely low RDS ON and the use of a power IC package with low thermal resistance and high thermal capacity helps to minimize system power dissipation. A blocking capacitor at the supply voltage is the only external circuitry due to the integrated freewheeling diodes. 1O v e r v i e w

1.1 Features

 Delivers up to 5 A continuous 6 A peak current  Optimized for DC motor management applications  Operates at supply voltages up to 40 V V e r y l o w RDS ON ; typ. 200 mΩ @2 5 °C per switch  Output full short circuit protected  Overtemperature protection with hysteresis and diagnosis  Short circuit and open load diagnosis with open drain error flag  Undervoltage lockout  CMOS/TTL compatible inputs with hysteresis  No crossover current  Internal freewheeling diodes  Wide temperature range;

Description

The TLE 5205-2 is an integrated power H-bridge with DMOS output stages for driving DC-Motors. The part is Type Ordering Code Package TLE 5205-2 Q67000-A9283 P-TO220-7-11 TLE 5205-2GP Q67006-A9237 P-DSO-20-12 TLE 5205-2G Q67006-A9325 P-TO263-7-1 TLE 5205-2S Q67000-A9324 P-TO220-7-12 5-A H-Bridge for DC-Motor Applications TLE 5205-2 P-TO220-7-11 P-DSO-20-12 P-TO263-7-1 P-TO220-7-12

1.2 Pin Configuration (top view)

N.C. V S N.C. GND EF Q1 Q2 GND GND N.C. N.C. N.C. N.C. N.C. N.C. N.C. AEP01990 OUT1 EF IN1 GND IN2 OUT2 SV 1234567 TLE 5205-2 TLE 5205-2GP

1.3 Pin Definitions and Functions

Pin No. P-TO220 Pin No. P-DSO Symbol Function 17O U T 1 Output of Channel 1; Short-circuit protected; integrated freewheeling diodes for inductive loads. 28E F Error Flag; TTL/CMOS compatible output for error detection; (open drain) 39I N 1 Control Input 1; TTL/CMOS compatible 4 1, 10, 11, 20 GND Ground; internally connected to tab 51 2 I N 2 Control Input 2; TTL/CMOS compatible 66 , 1 5 VS Supply Voltage; block to GND 71 4 O U T 2 Output of Channel 2; Short-circuit protected; integrated freewheeling diodes for inductive loads. – 2, 3, 4, 5, 16, 17, 18, N.C. Not Connected

1.4 Functional Block Diagram

Z Z IN OUT Error Flag EF IN1 IN2 OUT1 OUT2 GND V S AEB02394 Diagnosis and Protection Circuit 1 Diagnosis and Protection Circuit 2

1.5 Circuit Description

The control inputs consist of TTL/CMOS-compatible schmitt-triggers with hysteresis. Buffer amplifiers are driven by this stages. Output Stages The output stages consist of a DMOS H-bridge. Integrated circuits protect the outputs against short-circuit to ground and to the supply voltage. Positive and negative voltage spikes, which occur when switching inductive loads, are limited by integrated freewheeling diodes. A monitoring circuit for each output transistor detects whether the particular transitor is active and in this case prevents the corresponding source transistor (sink transistor) from conducting in sink operation (source operation). Therefore no crossover currents can occur.

1.6 Input Logic Truth Table

IN1 IN2 OUT1 OUT2 Comments L L H L Motor turns clockwise L H L H Motor turns counterclockwise H L L L Brake; both low side transistors turned-ON H H Z Z Open circuit detection Notes for Output Stage Symbol Value L Low side transistor is turned-ON High side transistor is turned-OFF H High side transistor is turned-ON Low side transistor is turned-OFF Z High side transistor is turned-OFF Low side transistor is turned-OFF

1.7 Monitoring Functions

Undervoltage lockout (UVLO): When VS reaches the switch on voltage VSO N the IC becomes active with a hysteresis. All output transistors are switched off if the supply voltage VS drops below the switch off value VSO F F .

1.8 Protective Function

Various errors like short-circuit to +VS, ground or across the load are detected. All faults result in turn-OFF of the output stages after a delay of 50µs and setting of the error flag EF to ground. Changing the inputs resets the error flag. a. Output Shorted to Ground Detection If a high side transistor is switched on and its output is shorted to ground, the output current is internally limited. After a delay of 50 µs all outputs will be switched-OFF and the error flag is set. b. Output Shorted to + VS Detection If a low side transistor is switched on and its output is shorted to the supply voltage, the output current is internally limited. After a delay of 50 µs all outputs will be switched-OFF and the error flag is set. c. Overload Detection An internal circuit detects if the current through the low side transistor exceeds the trippoint ISDL . In this case all outputs are turned off after 50 µs and the error flag is set. d. Overtemperature Protection At a junction temperature higher than 150 °C the thermal shutdown turns-OFF, all four output stages commonly and the error flag is set with a delay. e. Open Load Detection The output Q1 has a 10 kΩ pull-up resistor and the output Q2 has a 10 kΩ pull-down resistor. If E1 and E2 are high, all output power stages are turned-OFF. In case of no load between Q1 and Q2 the output voltage Q1 is VS and Q2 is ground. This state will be detected by two comparators and an error flag will be set after a delay time of 50 µs. Changing the inputs resets the error flip flop.

Figure 3 Simplified Schematic for Open Load Detection = & 50 sµ RS FF EF AES02395 V EL EHV Pull UP 10 k Ω 10 k Down Ω Pull

2 Diagnosis

Various errors as listed in the table “Diagnosis” are detected. Short circuits and overload result in turning off the output stages after a delay tdSD and setting the error flag simultaneously [EF = L]. Changing the inputs to a state where the fault is not detectable resets the error flag (input toggling) with the exception of short circuit from OUT1 to OUT2 (load short circuit). Flag IN1 IN2 OUT1 OUT2 EF Remarks Nr. Open circuit between OUT1 and OUT2 H L L Z L H L Z Not detectable Not detectable Not detectable Short circuit from OUT1 to OUT2 VS/2 VS/2 L Z VS/2 VS/2 L Z Not detectable Not detectable Short circuit from OUT1 to GND GND GND GND GND L H L L Not detectable Not detectable Not detectable Short circuit from OUT2 to GND H L L L GND GND GND GND Not detectable Not detectable Not detectable Short circuit from OUT1 to VS VS VS VS VS L H H H Not detectable Not detectable Short circuit from OUT2 to VS H L H H VS VS VS VS Not detectable Not detectable Overtemperature or undervoltage 0 Z Z Z Z Z Z Z Z IN: 0 = Logic LOW 1 = Logic HIGH OUT: Z = Output in tristate condition VS /2 due to internal Pull-up/down resistors EF: 1 = No error 0 = Error L = Output in sink condition H = Output in source condition

Electrical Characteristics

3 Electrical Characteristics

Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.

3.1 Absolute Maximum Ratings

– 40 °C < Tj < 150 °C Parameter Symbol Limit Values Unit Remarks min. max. Voltages Supply voltage VS – 0.3 40 V – – 14 0 V t < 0.5 s; IS > – 5 A Logic input voltage VIN1, 2 – 0.3 7 V 0 V < VS < 40 V Diagnostics output voltageVEF – 0.3 7 V – Currents of DMOS-Transistors and Freewheeling Diodes Output current (cont.) IOUT1, 2 – 55 A – Output current (peak) IOUT1, 2 – 66 A tp < 100 ms; T =1s Output current (peak) IOUT1, 2 – – A tp < 50µs; T =1s ; internally limitted; see overcurrent Temperatures Junction temperature Tj – 40 150 °C – Storage temperature Tstg – 50 150 °C – Thermal Resistances Junction case RthjC – 3 K/W P-TO220-7-11/12, P-TO263-7-1 Junction ambient RthjA – 65 K/W P-TO220-7-11/12 – 75 K/W P-TO263-7-1 Junction case RthjC – 5 K/W P-DSO-20-12 Junction ambient RthjA – 50 K/W P-DSO-20-12

3.2 Operating Range

Parameter Symbol Limit Values Unit Remarks min. max. Supply voltage VS VUV ON 40 V After VS rising above VUV ON Supply voltage increasing – 0.3 VUV ON V Outputs in tristate conditionSupply voltage decreasing – 0.3 VUV OFF V Logic input voltage VIN1, 2 – 0.3 7 V – Junction temperature Tj – 40 150 °C –

3.3 Electrical Characteristics

6 V < VS < 18 V; IN1 = IN2 = HIGH

IOUT1, 2 = 0 A (No load); – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. Current Consumption Quiescent current IS –– 10 mA IN1 = IN2 = LOW; VS = 13.2 V Under Voltage Lockout UV-Switch-ON voltage VUV ON – 5.3 6 V VS increasing UV-Switch-OFF voltage VUV OFF 3.5 4.7 5.6 V VS decreasing UV-ON/OFF-Hysteresis VUV HY 0.2 0.6 – V VUV ON – VUV OFF

Outputs OUT1, 2 Static Drain-Source-On Resistance Source IOUT = – 3A RDS ON H – 220 350 m Ω 6V < VS < 18 V Tj = 25 °C – 500 m Ω 6V < VS < 18 V 350 500 m Ω VSO N < VS ≤ 6V Tj = 25 °C – 800 m Ω VSO N < VS ≤ 6V Sink IOUT = 3 A RDS ON L – 230 350 m Ω 6V < VS < 18 V Tj = 25 °C – 500 m Ω 6V < VS < 18 V 400 600 m Ω VSO N < VS ≤ 6V Tj = 25 °C – 1000 m Ω VSO N < VS ≤ 6V Note: Values of RDS ON for VS ON < VS ≤ 6 V are guaranteed by design. Overcurrent Source shutdown trippoint– ISDH –– 10 A Tj = – 40 °C – 8 – A Tj = 25 °C 6 –– A Tj = 150 °C Sink shutdown trippoint ISDL –– 10 A Tj = – 40 °C – 8 – A Tj = 25 °C 6 –– A Tj = 150 °C Shutdown delay time tdSD 25 50 80 µs –

3.3 Electrical Characteristics (cont’d)

IOUT1, 2 = 0 A (No load); – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Short Circuit Current Limitation Source current – ISCH –– 20 A t < tdSD Sink current ISCL –– 15 A t < tdSD Open Circuit Pull up resistor RUP 51 0 2 0 k Ω – Pull down resistor RDOWN 51 0 2 0 k Ω – Switching threshold H VEH 22 . 5 3V – Switching threshold L VEH 22 . 4 3V – Detection delay time tdSD 25 50 80 µs – Output Delay Times (Device Active for t > 1 ms) Source ON tdO N H – 10 20 µs IOUT = – 3A resistive load Sink ON tdO N L – 10 20 µs IOUT = 3 A resistive load Source OFF tdO F F H – 25 µs IOUT = – 3A resistive load Sink OFF tdO F F L – 25 µs IOUT = 3 A resistive load IOUT1, 2 = 0 A (No load); – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Output Switching Times (Device Active for t > 1 ms) Source ON tON H – 15 30 µs IOUT = – 3A resistive load Sink ON tON L – 51 0 µs IOUT = 3 A resistive load Source OFF tOFF H – 25 µs IOUT = – 3A resistive load Sink OFF tOFF L – 25 µs IOUT = 3 A resistive load Clamp Diodes Forward Voltage High-side VFH – 11 . 5 V IF = 3 A Low-side VFL – 1.1 1.5 V IF = 3 A Leakage Current Source ILKH – 100 – 50 – µAO U T 1 = VS Sink ILKL – 50 100 µA OUT2 = GND Logic Control Inputs IN 1, 2 H-input voltage thresholdVINH 2.8 2.5 – V – L-input voltage VINL – 1.7 1.2 V – Hysteresis of input voltageVINHY 0.4 0.8 1.2 V – H-input current IINH – 20 2 µA VIN = 5 V L-input current IINL – 10 – 40 µA VIN = 0 V IOUT1, 2 = 0 A (No load); – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Low output voltage VEFL – 0.25 0.5 V IEF = 3 mA Leakage current IEFL –– 10 µA VEF = 7 V Thermal Shutdown Thermal shutdown junction temperature TjSD 150 175 200 °C – Thermal switch-on junction temperature TjSO 120 – 170 °C – Temperature hysteresis ∆T – 30 – K – Shutdown delay time tdSD 25 50 80 µs – Note: Values of thermal shutdown are guaranteed by design. IOUT1, 2 = 0 A (No load); – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Overcurrent Short Circuit Open Circuit IOUT ISD ISC IOC EF IN1 IN2 OUT1 OUT2 TLE 5205-2 5 7 4700 Fµ V S GND AES02396 Ι EF IN1Ι IN2Ι FLΙ V EF V IN1 IN2V V OUT1 OUT2V R Load OUT1Ι OUT2Ι 470 nF FUΙ ; SΙ V S 63 V

Quiescent Current IS (Active) versus Junction Temperature Tj Input Switching Thresholds VINH, L versus Junction Temperature Tj Static Drain-Source ON-Resistance versus Junction Temperature Tj Clamp Diode Forward Voltage V F versus Junction Temperature Tj -50 0 150 50 S AED02398 100 C = 18 VSV jT Ι mA V = 6 VS AED02400 0.5 1.0 1.5 2.0 2.5 3.0 V INH INLV INH, LV 500-50 C100 150 T j AED02399 0.1 0.2 0.3 0.4 0.5 0.6 jT Low Side Transistor High Side Transistor R ON 500-50 C100 150 0.7 AED02401 0.8 0.9 1.0 1.1 1.2 1.3 High Side Transistor Low Side Transistor V F 500-50 C100 150 T j

Overcurrent Shutdown Threshold ISD versus Junction Temperature Tj Error-Flag Saturation Output Voltage V EF versus Junction Temperature Tj Switching Threshold V EH , V EH versus Junction Temperature Tj SD AED02402 Ι Low Side Transistor High Side Transistor 500-50 C100 150 T j -50 0 150 50 AED02403 100 C 0.1 0.2 0.3 0.4 0.5 0.6 jT V EF -50 1.8 0 150 50 AED02404 100 C 2.0 2.2 2.4 2.6 2.8 3.0 jT V EH V EL V EH ,V EL

4 Package Outlines

(Plastic Transistor Single Outline Package) ±0.11.27 4.4 9.25±0.20.05 2.4 0.5±0.1 ±0.38.6 10.2±0.3 ±0.43.9 ±0.48.4 3.7±0.3 A A0.25 M 2.8 15.65±0.3 12.95 0...0.15 1.27 0.6±0.1 C ±0.2 17 ±0.3 8.51) 9.9±0.2 -0.153.7 10±0.2 C 1.6±0.3 All metal surfaces tin plated, except area of cut. Metal surface min. X=7.25, Y=12.3 Typical1) 0...0.3 GPT09083 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mm

+0.07-0.02 -0.31.2 2.8 1.3 0.25 1) Does not include plastic or metal protrusion of 0.15 max. per side 20x0.25M Heatsink 0.95 14.2 +0.15 Index Marking 15.9 101 0.1 +0.130.4 1.27 3.5 max. 6.3 3.25 20 11 ±0.15 ±0.1 ±0.15 1 x 45˚ ±0.3 5˚±3˚ ±0.15 15.74±0.1 A A B 0.25M B GPS05791 P-DSO-20-12 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device

A 8˚ max.BA0.25 M 0.1 Typical ±0.210 8.51) 7.551) (15) ±0.29.25 ±0.31 0...0.15 7x0.6±0.1 ±0.11.27 4.4 B 0.5±0.1 ±0.32.7 4.7±0.5 0.05 0.1 Metal surface min. X=7.25, Y=6.9 2.4 1.27 All metal surfaces tin plated, except area of cut. 0...0.3 B P-TO263-7-1 Option E3180 (Plastic Transistor Single Outline Package) GPT09114 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device

A BA0.25 M 9.9±0.2 15.65±0.3 12.95 0...0.15 1.27 0.6±0.1 ±0.11.27 4.4 B 9.25±0.2 0.05 C 17±0.3 8.51) 10±0.2 C 2.4 0.5±0.1 13 ±0.5 ±0.511 0...0.3 All metal surfaces tin plated, except area of cut. Metal surface min. X=7.25, Y=12.3 1) Typical 2.4 3.7-0.15 ±0.22.8 P-TO220-7-12 (Plastic Transistor Single Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mm