Q67000-A9230

TDA4916GG SIEMENS | Alldatasheet

Document overview

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Technical content

Features

• High clock frequency
• Low current drain
• High reference accuracy
• All monitoring functions Functional Description and Application The general-purpose single-ended switch-mode power supply device for the direct control of SIPMOS power transistors incorporates both digital and analog functions. These are required for the construction of high-quality flyback, forward and choke converters. The device can be likewise used for transformer-less voltage multipliers and variable-speed motors. Faults occurring during operation of the switch-mode power supply are detected by comparators integrated in the device which initiate protective functions. In addition, pairs of power supplies can be synchronized in antiphase. In-phase or antiphase synchronization is possible when more than two power supplies are involved. Type Ordering Code Package TDA 4916 GG Q67000-A9230 P-DSO-24-1

Semiconductor Group 2 05.96 Pin Configuration (top view) Figure 1 P-DSO-24-1

Semiconductor Group 3 05.96 Pin Definitions and Functions Pin No. Symbol Function 1 0V GND GND VS Supply voltage 3 0V QSIP Ground QSIP

4 Q SIP SIPMOS driver

VS QSIP Supply voltage driver

6 SF Series feed

7 – I K5/– I K6 Current sensor negative input 8 + I K5 Current sensor K5 9 + I K6 Current turn-OFF K6

10 Q K6 Output K6

11 PO Pulse omission

13 I SYN Input synchronization

14 Q SYN Output synchronization

16 C T Frequency generator

17 C R Ramp generator

18 I K4 Input undervoltage

19 I K3 Input overvoltage

20 I K1 Input K1

21 Q OP Output operational amplifier

22 – I OP Input operational amplifier 23 + I OP Input operational amplifier VREF Reference voltage

Semiconductor Group 4 05.96 Figure 2 Block Diagram

Semiconductor Group 5 05.96 Circuit Description The individual functional sections of the device and their interactions are described below. Power Supply atV S The device does not enable the output until the turn-ON threshold ofVS is exceeded. The duty factor (active time/period) can then rise from zero to the value set with K1 in the time determined by the soft start. The turn-OFF threshold lies below the turn-ON threshold. Below the turn-OFF threshold the output Q SIP is reliably low. Frequency Generator The frequency is mainly determined by close-tolerance external components and the calibrated reference voltage. The switching frequency at the output can be set by suitable choice of Rt andC t. The maximum possible duty factor can be reduced by a defined amount by means of a resistor fromC T to 0V GND. The maximum possible duty factor can be increased by a defined amount by means of a resistor fromC T toVS. Ramp Generator The ramp generator is controlled by the frequency generator and operates with the same frequency. CapacitorC r on the ramp generator is discharged by an internally-set current and charged via a current set externally. The duration of the falling edge of the ramp generator output must be shorter than its rise time. Only then do the upper and lower switching levels of the ramp generator signal have their nominal values. In “voltage mode control” operation, the rising edge of the ramp generator signal is compared with an externally set dc voltage in comparator K1 for pulse-width control at the output. The slope of the rising edge is set by the current through Rr. The voltage source connected toRr can be the SMPS input voltage. This makes it possible to control the duty factor for a constant volt-second product at the output. This control option (precontrol) permits equalization of known disturbances (e.g. input voltage ripple). Superimposed load current control (current mode control) can also be implemented. For this purpose the actual current at the source of the SIPMOS transistor is sensed and compared with the specified value in comparator K5.

Semiconductor Group 6 05.96 Comparator K1 (duty factor setting for voltage mode control) The two plus inputs of the comparator are so connected that the lower plus level is always compared with the minus input level. As soon as the voltage of the rising edge of the sawtooth (minus input) exceeds the lower of the two plus input levels, the output is inhibited via the turn-OFF Flip-Flop, that is to say the High time of the output can be continuously varied. Since the frequency remains constant, this corresponds to a duty factor change. Comparator K2 The comparator has a switching threshold at 1.5 V. Its output sets the fault Flip-Flop when the voltage on capacitor C a lies below 1.5 V. However, the fault Flip-Flop accepts the setting pulse only if no reset pulse (fault) is applied. This prevents resetting of the output as long as a fault signal is present. Comparators K3 (overvoltage), K4 (undervoltage), V S Undervoltage,V REF Overcurrent These are fault detectors which cause the output to be inhibited immediately by the fault Flip-Flop when faults occur. When faults are no longer present, the duty factor is reestablished via the soft start C SS . In the event of undervoltage, a current is injected at the input of K4 with the aid of which an adjustable hysteresis or latching is made possible. The value of the hysteresis is determined by the internal resistance of the external drive source and the current injected internally at the input of K4. In the event of undervoltage at K4, the injected current flows into the device. Comparator K5 (duty factor setting for current mode control) K5 is used to sense the source current at the switching transistor. The plus input of the comparator is fed out. Enabling of output Q SIP after cessation of the fault is effected with an H signal at the turn-OFF Flip-Flop output. Comparator K6 (overcurrent turn-OFF) The turn-OFF Flip-Flop is reset when overcurrent is detected by K6. In combination with the pulse-omission facility, individual pulses can then be omitted. This then results in a limited rise in the output current with a rising overload at the output.

Semiconductor Group 7 05.96 Operational Amplifier OP Opamp OP is a high-quality operational amplifier. It can be used in the control circuit to transfer the variations in the voltage to be regulated in amplified form to the free plus input of comparator K1. As a result, a voltage change is converted into a duty factor change. The output of OP is an open collector. The frequency response of OP is already corrected. The plus input is connected internally via a capacitor to ground. This gives the inverting amplifier a more favorable phase response. Turn-OFF Flip-Flop AFF A pulse is fed to the set input of the turn-OFF Flip-Flop with the falling edge of the frequency generator signal. However, it can only really be set if no reset signal is applied. With a set turn-OFF Flip-Flop, the output is enabled and can be active. The Flip-Flop inhibits the output in the event of a turn-OFF signal from K1, K5, K6 or K7. Fault Flip-Flop Fault signals fed to the reset input of the fault Flip-Flop cause the output to be immediately disabled (Low), and to be turned on again via the soft start C SS after removing fault-condition. Soft StartC SS The smaller of the two voltages at the plus inputs of K1 - compared with the ramp generator voltage - is a measure of the duty factor at the output. At the instant the device is turned-ON, the voltage on capacitor C SS equals zero. Provided no fault exists, the capacitor is charged up to its maximum value. C SS is discharged in the event of a fault. However, the fault Flip-Flop inhibits the output immediately. Below a charging voltage of approx. 1.5 V, a set signal is applied to the fault Flip-Flop and the output is enabled, provided a reset signal is not applied simultaneously. However, since the minimum ramp generator voltage is about 1.8 V, the duty factor at the output is not actually slowly and continuously increased until the voltage on C SS exceeds a value of 1.8 V. The Z-diode limits the voltage on capacitorC SS . The voltage at the ramp generator can reach a higher level than the Zener voltage. With a suitable ramp generator rising edge slope, the duty factor can be limited to a wanted maximum value. Pulse Omission PO In the event of overcurrent in the SIPMOS transistors it is frequently necessary to omit pulses even with minimum duty factor. Only this measure ensures that the SIPMOS transistors cannot be overloaded. This wanted function can be achieved with Pulse Omission PO and Overcurrent Comparator K7 by means of a suitable external circuit.

Semiconductor Group 8 05.96 Reference VoltageV REF The reference voltage source makes available a source with a high-stability temperature characteristic which can be used for external connection to the operational amplifier, the fault comparators, the frequency generator, or to other external units. The voltage source is short-circuit-proof to ground. Synchronization I SYN, Q SYN The device has an input and an output for synchronization. In the case of a synchronized device (slave), its output Q SIP is in phase opposition to the output Q SIP of the synchronizing device (master). In the case of an unconnected input I SYN, or with connection to VREF , or also when a series capacitor (without switching transitions) is connected, the device receives its clock from the internal frequency generator in accordance with the circuit connected to it. As soon as switching transitions appear at I SYN, switchover to external synchronization and vice versa takes place after a delay. After a switchover process, a few clock cycles must elapse in addition to the delay before the frequency and phase achieve their steady states. Series Feed SF The Series Feed circuit section is used to turn-OFF the external series-feed transistor when energy recovery commences. As a result there is minimum power loss in the supply to the device. With the series-feed transistor turned-OFF, its drive current flows via VS to VS. SIPMOS Driver Output Q SIP The output is High active. The time during which the output is active can be continuously varied. The duration of the rising edge of the frequency generator signal is the minimum time during which the output can be Low. The duration of the falling edge of the frequency generator signal is the maximum time during which the output can be High. The output driver is designed as a push-pull stage. The output current is limited internally to the specified values. Output Q SIP is connected via diodes to the supplyVS QSIP and 0V QSIP. A protection circuit SS lies between Q SIP and GND to clamp the output to ground at low impedance in the event of undervoltage atVS.

Semiconductor Group 9 05.96 When the supply to the switch-mode power supply is switched on, the capacitive displacement current from the gate of the SIPMOS transistor is conducted to the smoothing capacitor at VS QSIP by the diode connected toVS QSIP. The voltage at VS QSIP may reach about 2.3 V in the process without the SIPMOS transistor being turned-ON. The diode connected to ground clamps negative voltages at Q SIP to minus 0.7 V. Capacitive currents which occur with voltage dips at the drain terminal of the SIPMOS transistor can then flow away unimpeded. The output is active Low with supply voltages at VS andVS QSIP from about 4 V on. The function of the diode connected toVS QSIP and the resistor are then taken over by the pull-down source. The two ground terminals 0V SQIP and 0V GND can lie at different levels. This permits connections to be made to the SIPMOS transistor in such a way that the drive currents for the gate do not flow to the source via the current-sensing resistor. The maximum permissible level differences between 0V GND and 0V SQIP are given under Functional Range. If greater level differences are anticipated, it is better to join the two terminals.

Semiconductor Group 10 05.96 Absolute Maximum Ratings TA = – 40 to 85°C Parameter Symbol Limit Values Unit Test Condition min. max. Supply voltage;VS,VS QSIP I OP, I K1, I K3, I K4, I K5, I K6, I SYN Q SYN VS,VVS QSIP VI VI SYN II SYN VQ SYN – 0.3 – 0.3 – 0.3 V V V mA V VI SYN > 5 V or VI SYN < 0 V Frequency Generator; CT,RT VCT, RT ICT, RT – 0.3 V mA VCT > 5 V Ramp Generator;C R VCR ICR – 0.3 VCRH V mA VCRH (see charact.) VCR >VCRH Reference voltage;VREF VREF IREF – 0.3 –1 0 V mA VREF > 6 V or VREF < – 0.3 V Output Opamp; Q OP Inhibited Conducting VQO P IQO P – 0.3 V mA Output Overcurrent Turn-OFF; QK 6 Inhibited Conducting VQK 6 IQK 6 – 0.3 V mA Driver output; Q SIP VQ SIP – 0.3 VS V 1) Q SIP clamping diodes IQ SIP –1 0 1 0 m A VQ SIP >VS or VQ SIP < – 0.3 V Soft start;C SS VCSS ICSS – 0.3 VSSH 100 V µA VSSH (see charact.) VSS >VSSH Pulse omission; PO VPO IPO – 0.3 VPOH V mA VPOH (see charact.) VPO >VPOH Series feed; SF VSF – 0.3 17 V Junction temperature Tj – 65 150 °C Storage temperature Ts – 65 150 °C Thermal resistance system - ambient Rth S/A 60 K/W The values refer to the two connected ground terminals. 1) Important: observe max. power loss or junction temperature.

Semiconductor Group 11 05.96 Operating Range Function Symbol Limit Values Unit min. max. Supply voltage VS VVS QSIP V V Frequency generator f 0.05 400 kHz Ramp generator f 0.05 400 kHz Ambient temperature TA – 40 + 100 °C Ground Q SIP V0V QSIP GND – 300 mV GND + 2 V V Resistor atRT RRT 27 1000 k Ω Characteristics VSon <VS < 15 V, – 25°C < TA < 85°C; VSon means thatVS has exceededVSH , but has not gone belowVSL. Parameter Symbol Limit Values Unit Test Condition min. typ. max. Current inVS IVS 7 mA 1) mA 1) FG at 100 kHz FG at 300 kHz Q SYN unconnected mA mA 1) FG at 100 kHz FG at 300 kHz Q SYN to 0V GND Current in VS QSIP IVS QSIP 2.5 5.5 mA 1) mA 1) FG at 100 kHz FG at 300 kHz Current in VS + VS QSIP ISum 9 mA 1) mA 1) FG at 100 kHz FG at 300 kHz Q SYN unconnected mA mA 1) FG at 100 kHz FG at 300 kHz Q SYN to 0 V GND

Semiconductor Group 12 05.96 Current Drain2) Hysteresis atV S Turn-ON threshold forVS rising Turn-OFF threshold for VS falling VSH VSL 8.0 7.9 9.1 9.0 9.9 V V 1) C T;RT (see oscillator nomogram). 2) The currents asVS andVS QSIP are in each case without loads and without internal discharge toC R , as well as with active output Q SIP. Reference Voltage Voltage Load current VREF – IREF 2.460 2.500 2.540 V mA IREF = 250µA; VS =1 2V ΔVREF <3 0m V Voltage change Voltage change ΔVREF ΔVREF mV mV 0m A< IREF < 500µA

12 V <VS <1 4V

ΔVREF / ΔT – IREFO 3 0.1 61 0 mV/K mA Frequency Generator Nominal frequency spread ΔfF/fO – 4 4 % 20 kHz < fO < 150 kHz; Q SYN to GND; VS =1 2V ; TA =2 5°C Voltage dependence of nominal frequency Δ fV/fO –1 1 % 1 0V< VS < 14.4 V; TA =2 5°C; relative to fO at 12 V; 20 kHz <fO < 150 kHz Characteristics(cont’d) VSon <VS < 15 V, – 25°C < TA < 85°C; VSon means thatVS has exceededVSH , but has not gone belowVSL. Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 13 05.96 Temperature- dependence of nominal frequency Δ fτ/fO –3 3 % –2 5 °C< TA <+8 5 °C; VS =1 2V ; relative to fO at 25°C; 20 kHz <fO < 150 kHz Nominal frequency f20150 0.92fO fO 1.08fO kHz1) 20 kHz to 150 kHz Nominal frequency f150250 0.88fO fO 1.12fO kHz1),2) 150 kHz to 250 kHz Nominal frequency f250300 0.85fO fO 1.15fO kHz1),2) 250 kHz to 300 kHz Maximum duty cycleν20150 48 52 % 2) 20 kHz to 150 kHz Maximum duty cycleν150200 46 54 % 2) 150 kHz to 250 kHz Maximum duty cycleν250300 44 56 % 2) 250 kHz to 300 kHz Ramp Generator Frequency range f 0.05 300 kHz Maximum voltage at C R VCRH 4.8 5.8 6.8 V Minimum voltage atC R VCRL 1.4 1.8 2.2 V Discharge current at C R Idis 0.75 1.00 1.25 mA internally fixed Capacitance atC R C R 10 pF ON-time spread (limited byC SS ) ΔtOt/tOt –9 9 % C r = 200 pF; VIK1 > VSSH ; IRr = 150µA; TA =2 5°C; relative to tOt = 4.0µs 1) C T;RT (see oscillator nomogram). 2) See diagram: Tolerance of oscillator frequency, duty cycle. Characteristics(cont’d) VSon <VS < 15 V, – 25°C < TA < 85°C; VSon means thatVS has exceededVSH , but has not gone belowVSL. Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 14 05.96 ON-time drift ΔtOt/tOt –2 2 % C r = 200 pF; VIK1 > VCAH ; IRr = 150µA; relative to tOt =2 5°C ON-time spread tOt 3.6 4.0 4.4 µs C r = 200 pF; VIK1 > VCAH ; IRr = 150µA Operational Amplifier OP Open-loop gain G o 60 80 100 dB IQO P = 100µA Input offset voltageVio –5 + 5m V IQO P = 100µA Input current – Ii 1 µA Input common-mode range Vcm – 0.2 4 V Output current IQO P – 3 mA 0.5 < VQO P <1 5V Output voltage VQO P 0.5 15 V 0 mA < IQO P <2m A Transit frequency ft 2 5 8 MHz Transit phase φ t 90 120 150 Deg. Temp. coeff. ofVio Tc –1 0 +1 0 µV/K Rate of rise of voltage at output ΔV/Δt 1 ± 36 V / µs IQO P = 100µA Comparator K1 Input current – IK1 1 µA Input common-mode range Vcm 0 VCAH V Turn-OFF delay tOFF 200 400 ns 1) Nominal load 1 nF at Q SIP 1) Step functionΔV – 100 mV ΔV + 100 mV (for delay from comparator input to Q SIP). Characteristics(cont’d) VSon <VS < 15 V, – 25°C < TA < 85°C; VSon means thatVS has exceededVSH , but has not gone belowVSL. Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 15 05.96 Overvoltage K3 Input current – Ii 0.2 µA Switching voltage VSW VREF – 5m V VREF + 5m V V Turn-OFF delay tOFF 12 4 µs Undervoltage K4 Input current at K4 –Ii 0.2 µA Switching voltage at K4 VSW VREF – 5m V VREF + 5m V V Hysteresis currentIhy4H Ihy4L 51 0 1 5 0.1 µA µA V+ IK4< Vsw V+ IK4> Vsw Turn-OFF delay to 12 4 µs1) Current Sensor K5; Overcurrent Turn-OFF K6 Input current – Idyn 1 µA Input offset voltageVio –5 +5 m V Input common-mode range Vcm 04 V Turn-OFF delay tOFF 150 250 300 400 ns2) ns3) Load 1 nF at Q SIP Output K6 inhibitedIQK6 2 µA VQK6 =5V Conducting VQK6 1.2 V IQK6 =1m A 1) Step functionVREF – 100 mV VREF + 100 mV (for delay from comparator input to Q SIP). 2) Step functionΔV – 100 mV ΔV + 100 mV (for delay from comparator input to Q SIP). 3) Step functionΔV – 10 mV ΔV + 10 mV (for delay from comparator input to Q SIP). Characteristics(cont’d) VSon <VS < 15 V, – 25°C < TA < 85°C; VSon means thatVS has exceededVSH , but has not gone belowVSL. Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 16 05.96 Soft StartC SS Charging current atC SS – Ich 45 8 µA Discharge current at C SS Idis 0.8 1.5 3.0 µA Upper clamping voltage VSSH 4.4 4.8 5.2 V Difference VCRH –VSSH VDSS 0.1 V VCRH – VSSH Switching voltage of VK2 1.1 1.4 1.7 V Pulse Omission PO Charging current at PO int. – Ich 46 9 µA Charging current at PO ext. Ich 1m A Voltage at – K7 V–K 7 VS/3 –5% VS/3 VS/3 +5% V Upper clamping voltage at + K7 VPOH V-K7 + 0.2 V-K7 + 0.7 V-K7 + 1.2 V 0 mA < IPO <1m A Minimum voltage applied to PO VPOM 1V Synchronization Input I SYN II SYN – 70 200 µA0 V < VI SYN < 4.5 V Switching threshold at I SYN Open Rising edge Falling edge VI SYNO VI SYNR VI SYNF 1.5 2.5 1.0 2.7 3.4 2.0 3.5 4.0 3.0 V V V Characteristics(cont’d) VSon <VS < 15 V, – 25°C < TA < 85°C; VSon means thatVS has exceededVSH , but has not gone belowVSL. Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 17 05.96 Switchover delay int. free-running - synchronized synchronized - free-running tdf-s tds-f µs µs Limiting diodes – II SYN II SYN mA mA VI SYN <1V VI SYN >5V Output Q SYN High Low VQ SYNH VQ SYNL 4.1 0.6 V V – 500µA< IQ SYN <0 µA 0 µA< IQ SYN < 500µA Fan-out of Q SYN for control I SYN

2 Q SYN to 0V GND

9.0 500 500 10.0 10.5 V mV µA V V ISF >5 µA; VSF = 13 V VS = 11.5 V; VSF = 12.5 V IZ1 = 20µA; 0 ≤ VS ≤ 8 V IZ1 = 500µA 0 ≤ VS ≤ 8 V Output Driver Q SIP Saturation voltage source VQ SIPH VQ SIPH VQ SIPH 1.8 2.2 2.5 2.0 2.5 3.0 V V V IQ SIP =0m A IQ SIP =–1m A IQ SIP = – 200 mA VS = VQ SIP > VSon Saturation voltage sink VQ SIPL VQ SIPL 0.1 1.7 0.5 2.2 V V IQ SIP =1 0m A IQ SIP = 200 mA VS = VQ SIP > VSon Characteristics(cont’d) VSon <VS < 15 V, – 25°C < TA < 85°C; VSon means thatVS has exceededVSH , but has not gone belowVSL. Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 18 05.96 Saturation voltage sink VQ SIPP 1.5 V IQ SIP =+5m A IC passive Output current Falling edge Rising edge IQ SIP – IQ SIP 0.7 0.7 1.0 1.0 1.5 1.5 A A1) C Q SIP =1 0n F ; VS = VQ SIP =1 2V C Q SIP =1 0n F ; VS = VQ SIP =1 2V Output voltage Fall time Rise time tQ SIPF tQ SIPR 200 200 ns ns2) C Q SIP =1 0n F ; VS = VQ SIP =1 2V C Q SIP =1 0n F ; VS = VQ SIP =1 2V 1) Maximum dynamic current during rising or falling edge. 2) Voltage level 10 %/90 %. Characteristics(cont’d) VSon <VS < 15 V, – 25°C < TA < 85°C; VSon means thatVS has exceededVSH , but has not gone belowVSL. Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 19 05.96 Figure 3 Application Circuit 1: Forward Converter with Output Regulation

Semiconductor Group 20 05.96 Figure 4 Application Circuit 2: Flyback Converter with EMF Regulation

Semiconductor Group 21 05.96 Figure 5 Timing Diagram

Semiconductor Group 22 05.96 Figure 6 Soft StartC SS / Fault/ON - OFF

Semiconductor Group 23 05.96 Nomogram for FG fo = 97.5 kHz @Tj = 25°C; RT = 40.2 kΩ ;C T = 560 pF

Semiconductor Group 24 05.96 Instructions for the Approximate Calculation of the Maximum Duty Cycle of the FG when R VS orR GND is Connected to InputC T. 1. General remarks Duty cycleν = ON time/period Time t =C T ΔVCT /ICT ΔVCT = approx. 0.6 V CurrentIRGND = 2.2 V/RGND CurrentIRT = 2.5 V/RT CurrentIRVS = (12 V − 2.2 V)/RVS Mean valueVCT Mean = approx. 2.2 V To facilitate better general understanding, the equations are not abbreviated in the following. The wanted quantity can be isolated using the rules of arithmetic. 2. Calculation for connection of RVS (ν > 0.5) 3. Calculation for connection ofRGND (ν < 0.5) νmax C T 0.6 V⋅ IRT IRVS– C T 0.6 V⋅ IRT IRVS– C T 0.6 V⋅ IRT IRVS+ νmax C T 0.6 V⋅ IRT IRGND+ C T 0.6 V⋅ IRT IRGND+ C T 0.6 V⋅ IRT IRGND–

Semiconductor Group 25 05.96 Duty Cycle LimitingfFG = 100 kHz Example forνmax = 44 %: Step➀ to get 44 % a resistorRGND = 220 kΩ is found Step➁ for the sameν we getRT = 39 kΩ to setfFG to 100 kHz

Semiconductor Group 26 05.96 Tolerance of Osc. FrequencyΔfmax versus Osc. Frequencyf Tolerance of Duty CycleΔν max versus Osc. Frequencyf

Semiconductor Group 27 05.96 Package Outlines P-DSO-24-1 (SMD) (Plastic Dual Small Outline Package) GPS05144 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mmSMD = Surface Mounted Device