TCA965B SIEMENS | Alldatasheet

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– direct setting of lower and upper edge voltage (window edges) – indirect setting by window center voltage and half window width l Adjustable hysteresis l Digital outputs with open collectors for currents up to 50 mA l Adjustable reference voltageVStab Semiconductor Group 1 1998-02-10 TCA 965 B

Semiconductor Group 2 1998-02-10 Functional Description Amplifier Amp 3 increases the voltage of the reference sourceR toVStab = 2 xVREF . The amplification factor can be altered by external wiring. With direct setting of the window, the input voltage appears on amplifier Amp 1 ( V8), the upper edge voltage on comparator K2 (V6) and the lower edge voltage on comparator K1 (V7). With indirect setting of the window, the input voltage appears on inputs V6 and V7, while the center voltage is connected to amplifier A1 (V8). The voltage applied to the input (V9) of amplifier Amp 2 is subtracted symmetrically from the output voltage of amplifier Amp 1 and added. The comparators switch with hysteresis. The logic gates have open-collector outputs. If the inhibit input A or B is connected to ground, output A or B will always be high. Block Diagram Outputs A, B, C, D are open-collector IEB00091 20 kW20 kW +Amp 3 R Amp 1 Amp 2 V = 1 V = 1 11 1 5 S+VV REF VStab A Inhibit A C D Inhibit B B

Semiconductor Group 3 1998-02-10 Pin Configuration (top view) Pin Definitions and Functions Pin Symbol Pin Function in Direct Setting Indirect Setting of Window GND A D Inhibit A VREF GND Logic output A Logic output D = A @ B (AND) Connected to GND: logic output A = HIGH InternalVREF = 3 V Upper edge voltage Lower edge voltage Input voltage GND Input voltage V6/7 Input voltageV6/7 Center voltage Half window width VStab + VS Inhibit B C B Internal VStab = 6 V Supply voltage Connected to GND: logic output B = HIGH Logic output C = A @ B (NAND) Logic output B TCA 965 B IEP00292 C D A GND 7 8 6 9 5 10 4 11 3 12 2 13 1 14 B Inhibit A REFV Inhibit B V 9 V S V Stab V 8

Semiconductor Group 4 1998-02-10 Absolute Maximum Ratings Maximum ratings for ambient temperatureTA = – 25 to 85°C Parameter Symbol Limit Values Unit min. max. Supply voltage (pin 11) Difference in input voltage between pins 6, 7, 8 Input voltage (pins 6, 7, 8, 9) VS VI VI V V V Output current (pins 2, 3, 13, 14) IQ –5 0 m A Output voltage (pins 2, 3, 13, 14) independent ofVS Voltage onVREF (pin 5) VQ VR V V Output current of stabilized voltage (pin 10) I10 –1 0 m A Inhibit input voltage (pins 4, 12) VIH –7V Junction temperature Storage temperature Tj Tstg –5 5 150 125 Thermal resistance system - air P-DIP-14-1Rth SA – 80 K/W Operating Range Supply voltage VS 4.5 30 V Ambient temperature TA –2 5 8 5 °C

Semiconductor Group 5 1998-02-10 Characteristics VS = 10 V;TA = 25°C Parameter Symbol Limit Values Unit Test Condition Test Circuit min. typ. max. Current consumption Input current (pins 6, 7, 8) Input current, pin 9 IS II – II 400 3000 mA nA nA V2,V13 =VQH 1 Input offset voltage in direct setting of window Input offset voltage in indirect setting of window Input-voltage range on pins 6, 7, 8 Input-voltage range on pin 9 Differential input voltage Reference voltage Stabilized voltage on pin 10 TC of reference voltage Sensitivity of reference voltage to supply-voltage variation VIO VIO VI VI V6 –(V8 – V9) (V8 + V9)– V7 V10 a V5 DV5/DVS –2 0 –5 0 1.5 2.8 5.5 0.4 VS –1 VS/2 3.2 6.5 mV mV V mV V V V V mV/K mV/V D VI <1 3V IREF = 0 VS > 7.9 V Output reverse current IQH ––1 0 mA– – Output saturation voltage Hysteresis of window edges Inhibit threshold VQL VU – VL V4, 12 100 500 200 800 1.8 mV mV mV V IQ = 10 mA IQ = 50 mA Inhibit current I4, 12 – – 100 – mA– – Switching frequency fdir find kHz kHz

Semiconductor Group 6 1998-02-10 Test Circuit 1 Direct Setting of Window IES00086 V5 V10 VQL14 VQL13 VQL3 VQL2V6 V7 V8 IQH14 QH13I QH3I QH2II 6 62 I 7 II 4V V12 I 9 91 4 1 2 R L R L R L R L IS11 VS TCA 965B I I I = == = =

Semiconductor Group 7 1998-02-10 Test Circuit 2 Indirect Setting of Window by Center Voltage and Half Window Width IES00087 V6/7 V8 V9 14 1 2 V5 V10 VQL14 VQL13 VQL3 VQL2 IQH14 QH13I QH3I QH2I2 4V V12 R L R L R L R L IS11 VS TCA 965B = == = =

Semiconductor Group 8 1998-02-10 Schematic Circuit Diagrams Inhibit Inputs 4,12 Inputs 6, 7, 8 Outputs 2, 3, 13, 14 IES00088 Outputs Input 9 Outputs A, B GND High Not permitted> 7 V Normal functionopen Low> 1.8 V 100 1 k VS V4,12 V6,7,8 1 k VREF Q R VStab VREF VStab, V4,12 WW W

Semiconductor Group 9 1998-02-10 Application Circuit 1 Direct Setting of Lower and Upper Edge Voltages V6 –V9 = Upper edge voltage V7 +V9 = Lower edge voltage V8 = Input voltage TCA 965 B A D C B C 1 10 11 R 4 R 3 IES00294 1 41 2 C 3 R 6 IV V 6 SV R 2 To increase the switching frequency, pin 9 may be grounded

Semiconductor Group 10 1998-02-10 Definition of the Offset VoltageV IO IES00296 A VL VU V10 t V 10 V L V U+

Semiconductor Group 11 1998-02-10 Application Circuit 1 Direct Setting of Lower and Upper Edge Voltages Upper Edge Edge Lower tLU t t A B C D D C B A A B C DD C B A A B C D Pin 4 on GND Pin 12 on GND Inhibit A Inhibit B

1.8 V < Pin 12 < 7 V

1.8 V < Pin 4 < 7 V

Semiconductor Group 12 1998-02-10 Application Circuit 2 Indirect Setting of Window by Center Voltage and Half-Window Width V V6 = V7 = Input voltage V8 = Center voltage V9 = Half window width TCA 965 B A D C B C 1 10 11 1RR 3 R 5 4RR 2 IES00297 1 41 2 C 3 R 7 IV SV

Semiconductor Group 13 1998-02-10 Definition of the Offset VoltageV IO IES00299 B VL VU V10 t V9- V10 = VL -VU V8 -V92 - () V 10 V L V U+

Semiconductor Group 14 1998-02-10 Application Circuit 2 Indirect Setting of Window by Center Voltage and Half-Window Width V Upper Edge Edge Lower tLU t t A B C D D C B A A B C D D C B A A B C D Inhibit A Inhibit B IED00298 tULtt LU t Pin 4 on GND 1.8 V < Pin 4 < 7 V Pin 12 on GND 1.8 V < Pin 12 < 7 V

Semiconductor Group 15 1998-02-10 Application Circuit 3 Symmetrically Enlarged Edge Hysteresis in Direct Setting of Window Calculation of HysteresisV H IES00089 VS VI R 1 R 3 R LR LR L R 4 10 11 TCA 965B VH R 2 VH V7 V6 PR 5= V H V 10 R 5 V 10 V 10

Semiconductor Group 16 1998-02-10 Application Circuit 4 Symmetrically Enlarged Edge Hysteresis in Indirect Setting of Window Calculation of HysteresisV H VH =V9/2 –V9/1 IES00090 VS VI R 1 R 2 R LR LR L R 3R 5 R 4 10 11 TCA 965B V V9/1 9/2 6/7V VH = 9/1VV9/2- V 9/1 V 10 R 4 R 5|| V 9/2 V 10 R 4

Semiconductor Group 17 1998-02-10 P-DIP-14-1 (Plastic Dual In-line Package) GPD05005 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mm