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  • PDF pages: 10

Technical content

Features

  • Broadband internal input and output matching
  • Asymmetrical Doherty design - Main : P1dB = 20 W Typ - Peak : P1dB = 35 W Typ
  • Typical Pulsed CW performance, 1990 MHz, 28 V, Doherty Configuration - Output power at P1dB = 40.7 W - Efficiency = 63.7 % - Gain = 16.7 dB
  • Capable of handling 10:1 VSWR @27 V, 55 W (CW) output power
  • Integrated ESD protection
  • Human Body Model Class 1B (per ANSI/ESDA/ JEDEC JS-001)
  • Low thermal resistance
  • Pb-free and RoHS compliant-80 -60 -40 -20 27 31 35 39 43 47 Efficiency (%) Peak/Average Ratio, Gain (dB) Average Output Power (dBm) Single-carrier WCDMA Drive-up VDD = 27 V, IDQ = 150 mA, ƒ = 1990 MHz 3GPP WCDMA signal, PAR = 10.0 dB, 3.84 MHz BW Gain Efficiency PAR @ 0.01% CCDF pxac210552md_g1

Data Sheet 2 of 10 Rev. 03.1, 2017-01-25 PXAC210552MD DC Characteristics (each side) Characteristic Conditions Symbol Min Typ Max Unit Drain-Source Breakdown Voltage VGS = 0 V, IDS = 10 mA V(BR)DSS 65 — — V Drain Leakage Current VDS = 28 V, VGS = 0 V IDSS — — 1 µA V DS = 63 V, VGS = 0 V IDSS — — 10 µA Gate Leakage Current VGS = 10 V, VDS = 0 V IGSS — — 1 µA On-State Resistance (main) VGS = 10 V, VDS = 0.1 V RDS(on) — 0.38 — W On-State Resistance (peak) VGS = 10 V, VDS = 0.1 V RDS(on) — 0.19 — W Operating Gate Voltage (main) VDS = 27 V, IDQ = 0.15 A VGS 2.1 2.6 3.1 V (peak) VDS = 27 V, IDQ = 0 A VGS 1.23 1.73 2.23 V Maximum Ratings Parameter Symbol Value Unit Drain-Source Voltage VDSS 65 V Gate-Source Voltage VGS –6 to +10 V Operating Voltage VDS 0 to +32 V Junction Temperature TJ 225 °C Storage Temperature Range TSTG –65 to +150 °C Thermal Resistance (TCASE = 85°C, 8.5 W CW) RqJC 1.004 °C/W

Ordering Information

Type and Version Order Code Package Description Shipping PXAC210552MD V1 R5 PXAC210552MDV1R5XUMA1 PG-HB1DSO-4, earless flange Tape & Reel, 500 pcs

Data Sheet 3 of 10 Rev. 03.1, 2017-01-25 Typical Performance (data taken in a production test fixture) -65 -55 -45 -35 -25 -15 27 31 35 39 43 47 Efficiency(%) ACP Up & Low (dBc) Average Output Power (dBm) Single-carrier WCDMA Drive-up VDD = 27 V, IDQ = 150 mA, ƒ = 1990 MHz, 3GPP WCDMA signal, PAR = 10 dB, BW = 3.84 MHz ACPU ACPL Eff pxac210552md_g2 -25 -20 -15 -10 -40 -35 -30 -25 -20 1820 1870 1920 1970 2020 2070 2120 Return Loss (dB) ACP Up (dBc) Frequency (MHz) Single-carrier WCDMA Broadband Performance VDD = 27 V, IDQ = 150 mA, POUT = 39.3 dBm, 3GPP WCDMA signal, PAR = 10 dB Return Loss ACP Up pxac210552md_g4 1820 1870 1920 1970 2020 2070 2120 Efficiency (%) Gain (dB) Frequency (MHz) Single-carrier WCDMA Broadband Performance VDD = 27 V, IDQ = 150 mA, POUT = 39.3 dBm, 3GPP WCDMA signal, PAR = 10 dB Efficiency Gain pxac210552md_g3 29 34 39 44 49 Efficiency (%) Gain (dB) Output Power (dBm) CW Performance VDD = 27 V, IDQ = 150mA 1930MHz Gain 1960MHz Gain 1990MHz Gain 1930MHz Eff 1960MHz Eff 1990MHz Eff Efficiency Gain pxac210552md_g5

Data Sheet 4 of 10 Rev. 03.1, 2017-01-25 PXAC210552MD Typical Performance (cont.) Load Pull Performance Main Side Load Pull Performance – Pulsed CW signal: 16 µs, 10% duty cycle, 28 V, IDQ = 130 mA P1dB Max Output Power Max PAE Freq [MHz] Zs [W] Zl [W] Gain [dB] POUT [dBm] POUT [W] PAE [%] Zl [W] Gain [dB] POUT [dBm] POUT [W] PAE [%] Peak Side Load Pull Performance – Pulsed CW signal: 16 µs, 10% duty cycle, 28 V, IDQ = 250 mA P1dB Max Output Power Max PAE Freq [MHz] Zs [W] Zl [W] Gain [dB] POUT [dBm] POUT [W] PAE [%] Zl [W] Gain [dB] POUT [dBm] POUT [W] PAE [%] -15 -10 1850 1900 1950 2000 2050 2100 Input Return Loss (dB) Power Gain (dB) Frequency (MHz) Small Signal CW Gain & Input Return Loss VDD = 27 V, IDQ = 150 mA IRL Gain pxac210552md_g7 27 32 37 42 47 52 Efficiency (%) Gain (dB) Output Power (dBm) CW Performance at various VDD IDQ = 150 mA, ƒ = 1990 MHz VDD = 24 V VDD = 27 V VDD = 30 V Gain Efficiency pxac210552md_g6

Data Sheet 5 of 10 Rev. 03.1, 2017-01-25 Reference Circuit, 1805 – 2170 MHz Reference circuit assembly diagram (not to scale) C105 R104 C211 C210 C206 C207 C203 C107 C202 C208 C201 C205 C204 R105 R103 R102 C108 R106 C102 C104 C209 C103 C101 R101 C106 RO4350, 20MIL (201) PXAC210552MD_01 RF_IN RF_OUT VDD VGS(MAIN) VGS(PEAK) VDD

Data Sheet 6 of 10 Rev. 03.1, 2017-01-25 PXAC210552MD Reference Circuit (cont.) Reference Circuit Assembly DUT PXAC210552MD V1 Test Fixture Part No. LTA/PXAC210522MD V1 PCB Rogers 4350, 0.508 mm [0.020”] thick, 2 oz. copper, εr = 3.66, ƒ = 1805 – 2170 MHz Find Gerber files for this test fixture on the Infineon Web site at http://www.infineon.com/rfpower Components Information Component Description Manufacturer P/N Input C101 Capacitor, 4.7 pF ATC ATC600F4R7CW250T C102, C104, C106 Capacitor, 12 pF ATC ATC600F120JW250T C103 Capacitor, 5.6 pF ATC ATC600F5R6CW250T C105, C108 Capacitor, 10 µF Taiyo Yuden UMK325C7106MM-T C107 Capacitor, 2 pF ATC ATC600F2R0CW250T R101, R106 Resistor, 10 ohms Panasonic Electronic Components ERJ-3GEYJ100V R102 Resistor, 50 ohms Richardson C8A50Z4A R103, R104 Resistor, 470 ohms Panasonic Electronic Components ERJ-8GEYJ471V R105 Resistor, 10 ohms Panasonic Electronic Components ERJ-3GEYJ100V U1 Hybrid Coupler Anaren X3C25P1-02S Output C201, C202, C206, C209 Capacitor, 10 µF Taiyo Yuden UMK325C7106MM-T C203 Capacitor, 2 pF ATC ATC600F2R0CW250T C204 Capacitor, 0.2 pF ATC ATC600F0R2CW250T C205, C207, C208 Capacitor, 12 pF ATC ATC600F120JW250T C210, C211 Capacitor, 47 µF Cornell Dubillier Electronnics (CDE) SEK470M100ST

Data Sheet 7 of 10 Rev. 03.1, 2017-01-25 Pinout Diagram (top view) Pin Description D1 Drain device 1 (Main) D2 Drain device 2 (Peak) G1 Gate device 1 (Main) G2 Gate device 2 (Peak) S Source (flange) Main Peak PG_HB1DSO- 4_gw_pd_02-18-2015 S G1 G2 D1 D2 MainPeak

Data Sheet 8 of 10 Rev. 03.1, 2017-01-25 PXAC210552MD Package Outline Specifications VIEWÊY 2X 0.50 3.45 6.91 3.00 16.26 18.44 2. 2. 19.44 4X 4.90 2X 6.554X 3.99 3.28 2X 1.65 2X 2.02 14.94 ± 0.15

0.50 X 45°

9.02 Y 0.25 1.02 1.00 2X 13.05 4.00

4 X 7°

2 X 10°

4X 1.02 2.62 1.86 R0.45 0...0.1 5°± 3° 1.27 PG-HB1DSO-4_01_02-13-2015 D1 D2 G1 G2 0.10 MAX. 2X 0.35 Diagram Notes–unless otherwise specified: 1. Mold/Dam Bar/Metal protusion of 0.30mm max per side not included. 2. Metal protrusion are connected to source and shall not exceed 0.10mm max. 3. Fillets and radii: all radii are 0.3 mm max. 4.Interpret dimensions and tolerances per ISO 8015. 5. Dimensions are mm. 6. All tolerances ± 0.1mm unless specified otherwise. 7. All metal surfaces pre-plated, except area of cut. 8. Lead thickness: 0.25 mm. 9. Gold plating thickness: 0.25 micron [10 microinch] max. 10. Pins: D1, D2 – drain; G1, G2 – gate; S – source. VIEW Y 2X 0.50 3.45 6.91 3.00 16.26 18.44 2. 2. PG-HB1DSO-4_01_02-13-2015 D1 D2 G1 G2 S Diagram Notes—unless otherwise specified: 1. Mold/dam bar/metal protrusion of 0.30 mm max per side not included. 2. Metal protrusions are connected to source and shall not exceed 0.10 mm max. 3. Fillets and radii: all radii are 0.30 mm max. 4. Interpret dimensions and tolerances per ISO 8015. 5. Dimensions are mm. 6. All tolerances ± 0.1 mm unless specified otherwise. 7. All metal surfaces pre-plated, except area of cut. 8. Lead thickness: 0.25 mm. 9. Gold plating thickness: 0.25 micron [10 microinch] max. 10. Pins: D1, D2 – drain; G1, G2 – gate; S – source.

Data Sheet 9 of 10 Rev. 03.1, 2017-01-25 Package Outline Specifications Find the latest and most complete information about products and packaging at the Infineon Internet page http://www.infineon.com/rfpower VIEWÊY 2X 0.50 3.45 6.91 3.00 16.26 18.44 2. 2. 19.44 4X 4.90 2X 6.554X 3.99 3.28 2X 1.65 2X 2.02 14.94 ± 0.15 9.02 Y 0.25 1.02 1.00 2X 13.05 4.00 4X 1.02 2.62 1.86 R0.45 0...0.1 5°± 3° 1.27 PG-HB1DSO-4_01_02-13-2015 D1 D2 G1 G2 0.10 MAX. 2X 0.35 Diagram Notes–unless otherwise specified: 1. Mold/Dam Bar/Metal protusion of 0.30mm max per side not included. 2. Metal protrusion are connected to source and shall not exceed 0.10mm max. 3. Fillets and radii: all radii are 0.3 mm max. 4.Interpret dimensions and tolerances per ISO 8015. 5. Dimensions are mm. 6. All tolerances ± 0.1mm unless specified otherwise. 7. All metal surfaces pre-plated, except area of cut. 8. Lead thickness: 0.25 mm. 9. Gold plating thickness: 0.25 micron [10 microinch] max. 10. Pins: D1, D2 – drain; G1, G2 – gate; S – source. VIEW Y 2X 0.50 3.45 6.91 3.00 16.26 18.44 2. 2. PG-HB1DSO-4_01_02-13-2015 D1 D2 G1 G2 S Diagram Notes—unless otherwise specified: 1. Mold/dam bar/metal protrusion of 0.30 mm max per side not included. 2. Metal protrusions are connected to source and shall not exceed 0.10 mm max. 3. Fillets and radii: all radii are 0.30 mm max. 4. Interpret dimensions and tolerances per ISO 8015. 5. Dimensions are mm. 6. All tolerances ± 0.1 mm unless specified otherwise. 7. All metal surfaces pre-plated, except area of cut. 8. Lead thickness: 0.25 mm. 9. Gold plating thickness: 0.25 micron [10 microinch] max. 10. Pins: D1, D2 – drain; G1, G2 – gate; S – source. PG-HB1DSO-4-1_01_01-16-2017 0.05 6.91 3.45 16.26 18.44 3.00 2X 0.50 2 2 D1D2 G1G2

Data Sheet 10 of 10 Rev. 03.1, 2017-01-25 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Y our feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: (highpowerRF@infineon.com) To request other information, contact us at: +1 877 465 3667 (1-877-GO-LDMOS) USA or +1 408 776 0600 International Edition 2017-01-25 Published by Infineon Technologies AG

85579 Neubiberg, Germany

© 2015 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com/rfpower). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of In- fineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. PXAC210552MD V1

Revision History

Revision Date Data Sheet Type Page Subjects (major changes since last revision) 01 2015-07-24 Advance All Data Sheet reflects advance specification for product development 02 2016-04-01 Production All All Data Sheet reflects released product specification Revised all data and includes updated final specs, typical performance graphs, loadpull, refer- ence circuit, package outline 03 2016-06-02 Production 1–4 5, 6 8, 9 Revised graphs, VSWR voltage number Labeled VDD, VGG, RFIN and RFOUT in reference circuit, corrected components information Corrected package name 03.1 2017-01-25 Production 8, 9 Revised typo package outline