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Technical content

Features

  • Input matched
  • Asymmetric Doherty design - Main: P1dB = 17 W Typ - Peak: P1dB = 33 W Typ
  • Typical Pulsed CW performance, 2350 MHz,

28 V, 160 µs pulse width, 10% duty cycle,

  • Output power at P 1dB = 45.7 W - Efficiency = 46.2% - Gain = 14.6 dB
  • Typical single-carrier WCDMA performance, 2350 MHz, 28 V, 8.4 dB PAR @ 0.01% CCDF - Output power = 8.91 W - Efficiency = 44.2% - Gain = 14.2 dB - ACPR = –31 dBc @ 5 MHz
  • Capable of handling 10:1 VSWR @28 V, 50 W (CW) output power
  • Integrated ESD protection : Human Body Model, Class 1B (per JESD22-A114)
  • Low thermal resistance
  • Pb-free and RoHS compliant 26 30 34 38 42 46 Drain Efficiency (%) Gain (dB) Output Power (dBm) Two-carrier WCDMA Drive-up VDD = 28 V, IDQ = 120 mA, VGS1 = 2.6 V, VGS2 = 1.3 V, ƒ = 2400 MHz, 3GPP WCDMA signal, PAR = 8 dB, 10 MHz carrier spacing, BW 3.84 MHz Gain Efficiency ptac240502fc_g1

Data Sheet 2 of 8 Rev. 02.3, 2016-06-21 PTAC240502FC DC Characteristics Characteristic Conditions Symbol Min Typ Max Unit Drain-Source Breakdown Voltage VGS = 0 V, IDS = 10 mA V(BR)DSS 65 — — V Drain Leakage Current VDS = 28 V, VGS = 0 V IDSS — — 1 µA VDS = 63 V, VGS = 0 V IDSS — — 10 µA On-State Resistance (main) VGS = 10 V, VDS = 0.1 V RDS(on) — 0.4 — W On-State Resistance (peak) VGS = 10 V, VDS = 0.1 V RDS(on) — 0.2 — W Operating Gate Voltage (main) VDS = 28 V, IDQ = 120 mA VGS 2.6 2.7 2.8 V Operating Gate Voltage (peak) VDS = 28 V, IDQ = 0 mA VGS 1.2 1.3 1.5 V Gate Leakage Current VGS = 10 V, VDS = 0 V IGSS — — 1 µA Maximum Ratings Parameter Symbol Value Unit Drain-Source Voltage VDSS 65 V Gate-Source Voltage VGS –6 to +10 V Operating Voltage VDD 0 to +32 V Junction Temperature TJ 225 °C Storage Temperature Range TSTG –65 to +150 °C Thermal Resistance (TCASE = 60°C, 50 W CW) RqJC 1.29 °C/W

Ordering Information

Type and Version Order Code Package Description Shipping PTAC240502FC V1 R0 PTAC240502FCV1R0XTMA1 H-37248-4, earless flange Tape & Reel, 50 pcs PTAC240502FC V1 R250 PTAC240502FCV1R250XTMA1 H-37248-4, earless flange Tape & Reel, 250 pcs

Data Sheet 3 of 8 Rev. 02.3, 2016-06-21 Typical Performance (data taken in a production test fixture) -45 -40 -35 -30 -25 -20 -15 26 30 34 38 42 46 IMD (dBc) Output Power (dBm) Two-carrier WCDMA Drive-up VDD = 28 V, IDQ = 120 mA, VGS1 = 2.6 V, VGS2 = 1.3 V, 3GPP WCDMA signal, PAR = 8 dB, 10 MHz carrier spacing, BW 3.84 MHz

2300 IMDL

2300 IMDU

2350 IMDL

2350 IMDU

2400 IMDL

2400 IMDU

ptac240502fc_g3 26 30 34 38 42 46 50 Efficiency (%) Gain (dB) Output Power (dBm) CW Performance VDD = 28 V, IDQ = 120 mA

2300 MHz

2350 MHz

2400 MHz

ptac240502fc_g4 5 26 30 34 38 42 46 50 Efficiency (%) Power Gain (dB) Output Power (dBm) CW Performance at various VDD IDQ = 120 mA, ƒ = 2400 MHz VDD = 24V VDD = 28V VDD = 32V Gain Efficiency ptac240502fc_g5 -50 -40 -30 -20 -10 26 30 34 38 42 46 Drain Efficiency (%) IMD & ACPR (dBc) Output Power (dBm) Two-carrier WCDMA Drive-up VDD = 28 V, IDQ = 120 mA, VGS1 = 2.6 V, VGS2 = 1.3 V, ƒ = 2400 MHz, 3GPP WCDMA signal, PAR = 8 dB, 10 MHz carrier spacing, BW 3.84 MHz IMD Low IMD Up ACPR Efficiency ptac240502fc_g2

Data Sheet 4 of 8 Rev. 02.3, 2016-06-21 PTAC240502FC Typical Performance (cont.) Main Side Load Pull Performance – Pulsed CW signal: 160 µs, 10% duty cycle, 28 V, 114 mA P1dB Max Output Power Max PAE Freq [MHz] Zs [W] Zl [W] Gain [dB] POUT [dBm] POUT [W] PAE [%] Zl [W] Gain [dB] POUT [dBm] POUT [W] PAE [%] Load Pull Performance Peak Side Load Pull Performance – Pulsed CW signal: 160 µs, 10% duty cycle, 28 V, 252 mA P1dB Max Output Power Max PAE Freq [MHz] Zs [W] Zl [W] Gain [dB] POUT [dBm] POUT [W] PAE [%] Zl [W] Gain [dB] POUT [dBm] POUT [W] PAE [%] -30 -25 -20 -15 -10 2200 2250 2300 2350 2400 2450 2500 2550 Input Return Loss (dB) Power Gain (dB) Frequency (MHz) Small Signal CW Performance Gain & Input Return Loss VDD = 28 V, IDQ = 120 mA IRL Gain ptac240502fc_g6

Data Sheet 5 of 8 Rev. 02.3, 2016-06-21 Reference Circuit , 2300 – 2400 MHz Reference circuit assembly diagram (not to scale) PTAC240502FC IN_01_D C102 RF_IN RF_OUT VDD VG2 VG1 VDD p t a c 2 4 0 5 0 2 f c _ C D _ 1 1 - 0 5 - 2 0 1 3 C101 C103C105 C104 C106 R102 R101 R103 C205 C204 C206 C208 C207 C209 C202 C201 C203 RO4350, .020 (194) C210 PTAC240502FC OUT_01_D RO4350, .020 (194) R104 R105 C214 C212 C213 C211

Data Sheet 6 of 8 Rev. 02.3, 2016-06-21 PTAC240502FC Reference Circuit (cont.) Reference Circuit Assembly DUT PTAC240502FC V1 Test Fixture Part No. LTA/PTAC240502FC V1 PCB Rogers 4350, 0.508 mm [0.020”] thick, 2 oz. copper, εr = 3.66, ƒ = 2300 – 2400 MHz Find Gerber files for this test fixture on the Infineon Web site at http://www.infineon.com/rfpower Components Information Component Description Suggested Manufacturer P/N Input C101, C105 Capacitor, 4.7 µF Murata Electronics North America GRM32ER71H475KA88L C102, C103, C104, C106 Capacitor, 18 pF ATC ATC800A180JT250T R101, R102 Resistor, 10 W Panasonic Electronic Components ERJ-8GEYJ100V R103 Resistor, 50 W Anaren 060120A15Z50 R104 Resistor, 300 W Venkel CR0603-16W-3010FB R105 Resistor, 12.1 W Venkel CR0603-16W-12R1FB U1 Directional coupler Anaren X3C25P1-05S Output C201, C202, C203, C204, C206, C208 Capacitor, 18 pF ATC ATC800A180JT250T C205 Capacitor, 0.5 pF ATC ATC800A180JT250T C207, C210, C214 Capacitor, 4.71 µF Murata Electronics North America GRM32ER71H475KA88L C209, C212 Capacitor, 10 µF Taiyo Yuden UMK325C7106MM-T C211, C213 Capacitor, 100 µF Panasonic Electronic Components EEE-FP1V101AP Pinout Diagram (top view) Lead connections for PTAC240502FC S D1 D2 G1 G2 MainPeak Pin Description D1 Drain device 1 (Peak) D2 Drain device 2 (Main) G1 Gate device 1 (Peak) G2 Gate device 2 (Main) S Source (flange)

Data Sheet 7 of 8 Rev. 02.3, 2016-06-21 Package Outline Specifications Package H-37248-4 Find the latest and most complete information about products and packaging at the Infineon Internet page http://www.infineon.com/rfpower Diagram Notes—unless otherwise specified: 1. Interpret dimensions and tolerances per ASME Y14.5M-1994. 2. Primary dimensions are mm. Alternate dimensions are inches. 3. All tolerances ± 0.127 [.005] unless specified otherwise. 4. Pins: D1, D2 – drains; G1, G2 – gates; S – source. 6. Gold plating thickness: 1.14 ± 0.38 micron [45 ± 15 microinch]. CL LC CL 2X 12.70 [.500] 19.81±0.20 [.780±0.008] 4X 3.81 [.150] LID 9.40 [.370] FLANGE 9.78 [.385] 2X 4.83±0.51 [.190±0.020] 3.76±0.25 [.148±0.010] SPH 1.57 [.062] 4X R0.76+0.13 -0.38 [R.030 +0.005 -0.015 ]D1 D2 G1 G2 1.02 [.040] 20.57 [.810]S 2X 45° X 2.72 [45° X .107] (8.89 [.350]) (5.08 [.200]) 19.43±0.51 [.765±0.020] 0.0381 [.0015] -A-

Data Sheet 8 of 8 Rev. 02.3, 2016-06-21 Edition 2016-06-21 Published by Infineon Technologies AG

85579 Neubiberg, Germany

© 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com/rfpower). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of In- fineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Y our feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: highpowerRF@infineon.com To request other information, contact us at: +1 877 465 3667 (1-877-GO-LDMOS) USA or +1 408 776 0600 International PTAC240502FC V1

Revision History

Revision Date Data Sheet Type Page Subjects (major changes since last revision) 01 2013-07-16 Advance All Data Sheet reflects advance specification for product development 02 2013-11-13 Production All Data Sheet reflects released product specification 02.1 2013-11-27 Production 1 Revised ESD classification 02.2 2014-05-14 Production 2 Revised juntion temperature in Maximum Ratings table 02.3 2016-06-21 Production 2 Updated ordering information