PT7C433833 PERICOM | Alldatasheet
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and 56 bytes of nonvolatile RAM. minutes, hours, day, date, month, and year information. 24-hour or 12-hour format with AM/PM indicator. details are shown in section: overview of functions. Table 1. Basic functions of PT7C4338
1 Oscillator
2 Time
3 Alarm interrupt -
5 RAM 568
6 Battery backup
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) Pin Assignment Pin Description Pin no. Pin Type Description
1 X1 I
32.768kHz Crystal Connections. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF. Pin X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, pin X2, is floated if an external oscillator is connected to pin X1. An external 32.768kHz oscillator can also drive the PT7C4338. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.
2 X2 O
6 SCL I Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface. 5 SDA I/O Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The SDA pin is open-drain output and requires an external pull-up resistor.
7 SQW/OUT O
Square-Wave/Output Driver. When enabled and the SQWE bit set to 1, the SQW/OUT pin outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz, 32kHz). It is open drain and requires an external pull up resistor. Operates with either VCC or VBAT applied.
8 VCC P
Supply Voltage. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected to the device and VCC is below VPF, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage.
3 VBAT P
+3V Battery Input. Backup supply input for any standard 3V lithium cell or other energy source. Battery voltage must be held between the minimum and maximum limits for proper operation. If a backup supply is not required, VBAT must be grounded. UL recognized to ensure against reverse charging when used with a lithium battery.
4 GND P
Ground. DC power is provided to the device on these pins. VCC is the primary power input. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected to the device and VCC is below VPF, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. VBAT GND VCC SQW/OUT SCL 6 4 5SDA PT7C4338 SOIC-8 MSOP-8
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) Function Block Maximum Ratings Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions (VCC = VCC(MIN) to VCC(MAX), TA = -40℃ to +85℃.) (Note 1) Parameter Symbol Conditions Min. Typ. Max. Unit Supply Voltage VCC PT7C433833 2.7 3.3 5.5 V Logic 1 VIH Note 2 0.7 * VCC - VCC + 0.3 Logic 0 VIL Note 2 -0.3 - +0.3 * VCC Power-Fail Voltage VPF PT7C433833 - 2.59 - VBAT Battery Voltage VBAT Note 2 1.5 3.0 3.7 Note 1: Limits at -40° C are guaranteed by design and not production tested. Note 2: All voltages are referenced to ground.
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) (VCC = VCC(MIN) to VCC(MAX), TA = -40℃ to +85℃.) (Note 1) Parameter Symbol Conditions Min. Typ. Max. Unit VBAT Battery Voltage VBAT Note 2 1.5 - 3.7 V Input Leakage ILI Note 3 - - 1 μA I/O Leakage ILO Note 4 - - 1 μA SDA Logic 0 Output IOLSDA VCC > 2V; VOL = 0.4V 3.0 - - mA VCC < 2V; VOL = 0.2 VCC 3.0 - - SQW/OUT Logic 0 Output IOLSQW 1.5V < VCC < 1.71V; VOL = 0.2 VCC 250 - - μA Active Supply Current (Note 5) ICCA PT7C433833 - 120 200 μA Standby Current (Note 6) ICCS PT7C433833 - 85 125 μA VBAT Leakage Current (VCC Active) IBATLKG - - 25 100 nA (VCC = 0V, TA = -40℃ to +85℃.) (Note 1) Parameter Symbol Min. Typ. Max. Unit VBAT Current (OSC ON); VBAT =3.7V, SQW/OUT OFF (Note 7) IBATOSC1 - 400 1200 nA VBAT Current (OSC ON); VBAT =3.7V, SQW/OUT ON (32kHz) (Note 7) IBATOSC2 - 570 1400 nA VBAT Data-Retention Current (OSC OFF); VBAT =3.7V (Note 7) IBATDAT - - 300 nA Note 1: Limits at -40° C are guaranteed by design and not production tested. Note 2: All voltages are referenced to ground. Note 3: SCL only. Note 4: SDA and SQW/OUT. Note 6: Specified with the I2C bus inactive. Note 7: Measured with a 32.768kHz crystal attached to X1 and X2. Sym Description Value Unit VHM Rising and falling threshold voltage high 0.7 VCC V VHL Rising and falling threshold voltage low 0.3 VCC V Measurement level Signal tf tr VHM VLM
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) (TA = -40℃ to +85℃) (Note 1) Parameter Symbol Conditions Min. Typ. Max. Unit SCL Clock Frequency fSCL Fast mode 100 - 400 kHz Standard mode - - 100 Bus Free Time Between STOP and START condition tBUF Fast mode 1.3 - - μs Standard mode 4.7 - - Hold Time (Repeated) START Condition (Note 2) tHD:STA Fast mode 0.6 - - μs Standard mode 4.0 - - LOW Period of SCL Clock tLOW Fast mode 1.3 - - μs Standard mode 4.7 - - HIGH Period of SCL Clock tHIGH Fast mode 0.6 - - μs Standard mode 4.0 - - Setup Time of Repeated START Condition tSU:STA Fast mode 0.6 - - μs Standard mode 4.7 - - Data Hold Time (Note 3, 4) tHD:STA Fast mode 0 - 0.9 μs Standard mode 0 - - Data Setup Time (Note 5) tSU:STA Fast mode 100 - - ns Standard mode 250 - - Rise Time of Both SDA and SCL Signals (Note 6) tr Fast mode 20+0.1CB - 300 ns Standard mode 20+0.1CB - 1000 Fall Time of Both SDA and SCL Signals (Note 6) tf Fast mode 20+0.1CB - 300 ns Standard mode 20+0.1CB - 300 Setup Time for STOP Condition tSU:STO Fast mode 0.6 - - μs Standard mode 4.0 - - Capacitance Load for Each Bus Line CB Note 6 - - 400 pF I/O Capacitance (SDA, SCL) CI/O Note 1 - - 10 pF Oscillator Stop Flag (OSF) Delay tOSF Note 7 - 100 - ms Note 1: Limits of full temperature are guaranteed by design not production test. Note 2: After this period, the first clock pulse is generated. Note 3: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V IHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 4: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 5: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t r MAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 7: The parameter tOSF is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ≤ VCC ≤ VCC MAX and 1.3V ≤ VBAT ≤ 3.7V.
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) Timing Diagram Power-Up/Power-Down Characteristics (TA = -40℃ to +85℃) (Note 1, Fig 3) Parameter Symbol Min. Typ. Max. Unit Recovery at Power-Up (Note 2) tREC - - 2 ms VCC Fall Time: VPF(MAX) to VPF(MIN) tVCCF 300 - - μs VCC Rise Time: VPF(MIN) to VPF(MAX) tVCCR 0 - - μs Note 1: Limits at -40° C are guaranteed by design and not production tested. Note 2: This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power -up delay occurs. Fig 3. Power-Up/Power-Down Timing
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) Recommended Layout for Crystal Built-in Capacitors Specifications and Recommended External Capacitors Parameter Symbol Typ Unit Build-in capacitors X1 to GND CG 20 pF X2 to GND CD 20 pF Recommended External capacitors X1 to GND C1 4 pF X2 to GND C2 4 pF Note: The frequency of crystal can be optimized by external capacitor C1 and C2, for frequency=32.768KHz, C1 and C2 should meet the equation as below: Cpar + [(C1+CG)*(C2+CD)]/ [(C1+CG)+(C2+CD)] =CL Cpar is all parasitical capacitor between X1 and X2. CL is crystal’s load capacitance. Crystal Specifications Parameter Symbol Min Typ Max Unit Nominal Frequency fO - 32.768 - kHz Series Resistance ESR - - 70 k Load Capacitance CL - 12.5 - pF Note: The crystal, traces and crystal input pins should be isolated from RF generating signals.
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) Function Description Overview of Functions Clock function CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two -digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100. Programmable square wave output Interface with CPU Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data). Since the output of the I/O pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O is also open drain. The SCL's maximum clock frequency is 400 kHz, which supports the I 2C bus's high-speed mode. Oscillator enable/disable Oscillator can be enabled or disabled by /EOSC bit. Registers Allocation of registers Addr. (hex)*1 Function Register definition Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00 Seconds (00-59) /EOSC*2 S40 S20 S10 S8 S4 S2 S1
01 Minutes (00-59) 0 M40 M20 M10 M8 M4 M2 M1
02 Hours (00-23 / 01-12) 0 12, /24 H20 or
P, /A H10 H8 H4 H2 H1
03 Days of the week (01-07) 0 0 0 0 0 W4 W2 W1
04 Dates (01-31) 0 0 D20 D10 D8 D4 D2 D1
05 Months (01-12) 0 0 0 MO10 MO8 MO4 MO2 MO1
06 Years (00-99) Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1
07 Control*3 OUT*4 0 OSF SQWE*5 0 0 RS1*6 RS0*6
Caution points: *1. PT7C4338 uses 6 bits for address. That is if write data to 41H, the data will be written to 01H address register. *2. Oscillator Enable bit. When this bit is set to 1, oscillator is stopped but time count chain is still active. *3. Control register was used to select SQW/OUT pin output square wave with one of 4 kinds of frequency or DC level. *4. Control SQW/OUT pin output DC level when square wave is disabled. *5. Square wave outputs enable at SQW/OUT pin. *6. Square wave output frequency select. *7. PT7C4338 has 568 static RAM for customer use. It is volatile RAM. *8. All bits marked with "0" are read-only bits. Their value when read is always "0". All bits marked with "-" are customer using space.
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) Control and status register Addr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0
07 Control OUT 0 OSF SQWE 0 0 RS1 RS0
(default) 1 0 1 1 0 0 1 1 OUT It controls the output level of the SQW/OUT pin when the square wave output is disabled. OUT Data Description Read / Write 0 When SQWE = 0, SQW/OUT pin output low. 1 When SQWE = 0, SQW/OUT pin output high. Default SQWE (Square Wave Enable) This bit, when set to logic 1, will enable the oscillator output. The frequency of the square wave output depends upon the value of the RS0 and RS1 bits. With the square wave output set to 1Hz, the clock registers update on the falling edge of the square wa ve. RS (Rate Select) These bits control the frequency of the square wave output when the square wave output has been enabled. RS1, RS0 Data SQW output freq. (Hz) Read / Write 00 1 01 4.096k 10 8.192k 11 32.768k Default OSF(Oscillator Stop Flag) Logic 1 in this bit indicates that the oscillat or either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and calendar data. This bit is set to logic 1 anytime that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltage present on VCC and VBAT is insufficient to support oscillation. 3) The /EOSC bit is set to 1, disabling the oscillator. 4) External influences on the crystal (e.g., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF bit to logic 1 leaves the value unchanged.
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) Time Counter Time digit display (in BCD code): Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00. Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. Addr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0
00 Seconds /EOSC S40 S20 S10 S8 S4 S2 S1
(default) 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined
01 Minutes 0 M40 M20 M10 M8 M4 M2 M1
(default) 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined
02 Hours 0 12, /24 H20 or P,/A H10 H8 H4 H2 H1
(default) 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 12, /24 bit This bit is used to select between 12-hour clock system and 24-hour clock system. 12, /24 Data Description Read / Write 0 24-hour system 1 12-hour system This bit is used to select between 12-hour clock operation and 24-hour clock operation. 12, /24 Description Hours register 0 24-hour time display 1 12-hour time display * Be sure to select between 12-hour and 24-hour clock operation before writing the time data. 24-hour clock 12-hour clock 24-hour clock 12-hour clock 00 52 ( AM 12 ) 12 72 ( PM 12) 01 41 ( AM 01 ) 13 61 ( PM 01 ) 02 42 ( AM 02 ) 14 62 ( PM 02 ) 03 43 ( AM 03 ) 15 63 ( PM 03 ) 04 44 ( AM 04 ) 16 64 ( PM 04 ) 05 45 ( AM 05 ) 17 65 ( PM 05 ) 06 46 ( AM 06 ) 18 66 ( PM 06 ) 07 47 ( AM 07 ) 19 67 ( PM 07 ) 08 48 ( AM 08 ) 20 68 ( PM 08 ) 09 49 ( AM 09 ) 21 69 ( PM 09 ) 10 50 ( AM 10 ) 22 70 ( PM 10 ) 11 51 ( AM 11 ) 23 71 ( PM 11 )
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) Days of the week Counter The day counter is a divide-by-7 counter that counts from 01 to 07 and up 07 before starting again from 01. Values that correspond to the day of week are user defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illog ical time and date entries result in undefined operation. Addr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0
03 Days of the week 0 0 0 0 0 W4 W2 W1
(default) 0 0 0 0 0 Undefined Undefined Undefined Calendar Counter The data format is BCD format. Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December). Range from 1 to 30 (for April, June, September and November). Range from 1 to 29 (for February in leap years). Range from 1 to 28 (for February in ordinary years). Carried to month digits when cycled to 1. Month digits: Range from 1 to 12 and carried to year digits when cycled to 1. Year digits: Range from 00 to 99 and 00, 04, 08, … , 92 and 96 are counted as leap years. Addr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0
04 Dates 0 0 D20 D10 D8 D4 D2 D1
(default) 0 0 Undefined Undefined Undefined Undefined Undefined Undefined
05 Months 0 0 0 M10 M8 M4 M2 M1
(default) 0 0 0 Undefined Undefined Undefined Undefined Undefined
06 Years Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1
(default) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Note: Any registered imaginary time should be replaced by correct time, otherwise it will cause the clock counter malfunction.
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) I2C Bus Interface Overview of I2C-BUS The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SC L (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on. Both the SCL and SDA signals are held at high level whenever communications are not being per formed. The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of o ne bit per clock pulse. The I 2C bus device does not include a chip select pin such as is found in ordinary l ogic devices. Instead of using a chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when i ts slave address matches the slave address in the received data. System Configuration All ports connected to the I 2C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices. SCL and SDA are both connected to the VDD line via a pull -up resistance. Consequently, SCL and SDA are both held at high level when the bus is released (when communication is not being performed). Fig 1. System configuration Master MCU Slave RTC Other Peripheral Device Vcc SDA SCL Note: When there is only one master, the MCU is ready for driving SCL to "H" and RP of SCL may not required. RP RP
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) Starting and Stopping I2C Bus Communications Fig 2. Starting and stopping on I2C bus 1) START condition, repeated START condition, and STOP condition a) START condition SDA level changes from high to low while SCL is at high level b) STOP condition SDA level changes from low to high while SCL is at high level c) Repeated START condition (RESTART condition) In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the START condition, the SDA level changes from high to low while SCL is at high level. 2) Data Transfers and Acknowledge Responses during I2C-BUS Communication a) Data transfers Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. The address auto increment function operates during both write and read operations. Updating of data on the transmitter (transmitting side)'s SDA line is performed whil e the SCL line is at low level. The receiver (receiving side) captures data while the SCL line is at high level. *Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART, or STOP condition.
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) b) Data acknowledge response (ACK signal) When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8 -bit data segment is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This does not include instances where the master device intentionally does not generate an ACK signal.) Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on th e SCL line, the transmitter releases the SDA line and the receiver sets the SDA line to low (= acknowledge) level. After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at t he falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the transmitter. When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent fr om the slave, that indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and aw aits a STOP condition from the Master. Slave Address The I2C bus device does not include a chip select pin suc h as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device. All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving devic e responds to this communication only when the specified slave address it has received matches its own slave address. Slave addresses have a fixed length of 7 bits. See table for the details. An R/W bit is added to each 7-bit slave address during 8-bit transfers. Table Operation Transfer data Slave address R / W bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read D1 h 1 1 0 1 0 0 0 1 (= Read) Write D0 h 0 (= Write) I2C Bus’s Basic Transfer Format SCL from Master 1 2 8 9 SDA from transmitter (sending side) SDA from receiver (receiving side) Release SDA Low active ACK signal S Start indication P Stop indication Sr Restart indication A RTC Acknowledge A Master Acknowledge
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) 1) Write via I2C bus 2) Read via I2C bus a) Standard read b) Simplified read Note: 1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred during actual communications. 2. 49H, 4AH are used as test mode address. Customer should not use the addresses. Slave address (7 bits) 1 1 0 1 0 0 0 0 write Addr. setting Slave address + write specification Address Specifies the write start address. A bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit A P Write data S A A C K A C K A C K Start Stop Slave address (7 bits) 1 1 0 1 0 0 0 0 write Slave address + write specification Address Specifies the read start address. Addr. setting AS Slave address (7 bits) 1 1 0 1 0 0 0 1 Read Slave address + read specification Data read (1) Data is read from the specified start address and address auto increment. A bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit /A PSr 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bitbit Data read (2) Address auto increment to set the address for the next data to be read. A C K N O A C K A A C K A C K A C K A Start StopRestart Data read (2) Address register auto increment to set the address for the next data to be read. Data read (1) Data is read from the address pointed by the internal address register and address auto increment. Slave address (7 bits) 1 1 0 1 0 0 0 1 Read A bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit /A PS 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bitbit A C K N O A C K A C K A StopStart Slave address + read specification
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) Mechanical Information WE (Lead free and Green SOIC-8) Min Max A 1.350 1.750 A1 0.100 0.250 A2 1.350 1.550 b 0.330 0.510 c 0.170 0.250 D 4.700 5.100 E 3.800 4.000 E1 5.800 6.200 e L 0.400 1.270 θ 0° 8° Symbol Dimensions In Millimeters
1.27 BSC
Note: 1) Controlling dimensions in millimeters. 2) Ref: JEDEC MS -012E/AA
12-07-0001 PT0321-6 07/04/12 PT7C433833 Real-time Clock Module (I2C Bus) UE(Lead free and Green MSOP-8) Min Max A 0.82 1.10 A1 0.02 0.15 A2 0.75 0.95 b 0.25 0.38 c 0.09 0.23 D 2.90 3.10 E 2.90 3.10 E1 4.75 5.05 e L 0.40 0.80 θ 0° 6° Symbol Dimensions In Millimeters
0.65 BSC
Note: 1) Controlling dimensions in millimeters. 2) Ref: JEDEC MO-187E/BA
Ordering Information
Part Number Package Code Package PT7C433833WE W Lead free and Green 8-Pin SOIC PT7C433833UE U Lead free and Green 8-Pin MSOP Note: E = Pb-free and Green Adding X Suffix= Tape/Reel Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.