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Document overview
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Technical content
Features
ÎÎ Compliant with VESA DisplayPort 1.2 specification for HBR2, HBR, RBR rate (5.4/2.7/1.62Gbps) ÎÎ Dual mode DisplayPort Outputs by providing DDC signals across the Aux sink pin ÎÎ Built-in Aux interception circuit only listen to the link training, but does not affect link training ÎÎ Sink Request Auto Test Mode through Aux Channels ÎÎ Dynamic EQ through Aux configuration register programming for deterministic jitter reduction ÎÎ Cable Detection pins, toggle between DP and TMDS mode ÎÎ Automatic power down state when HPD signal is low ÎÎ Low insertion loss across the Aux signal path ÎÎ Dedicated pin control mode for Equalization setting control ÎÎ Internally Biased AC coupled in Aux channel ÎÎ Single Power Supply: 3.3V ÎÎ Integrated ESD protection ÎÎ Package : 48-pin TQFN, 7mm x 7mm DP++ Source Device DP Redriver ConnectorDP Mux 5-10” trace length recommended Typical Application
Description
PI3EQXDP1201 provides the ability to reduce signal jitter by transmission line effects to enable longer cable length on the 5.4Gbps DisplayPort1.2 signals. Integrated AUX decoder can support Displayport link training. It can decipher the link training message and auto- matically configure Displayport differential signal outputs with the best pre-emphasis and output swing level settings. Input Equalization, Output level swing and pre-emphasis are controlled by either Aux link snooping or pin configu - ration. Decoding of the Aux command happens during link training. Built-in Sync Request Auto Test mode enables users to com- plete DisplayPort link status through Aux channels in min- utes. PI3EQXDP1201 is intended for use in any systems, DP sig- nal compliance is required, including notebook PC and docking stations, Graphic cards and digital video systems.
Applications
ÎÎ Notebook and Dock station ÎÎ PC system boards ÎÎ Digital video systems COMPANY CONFIDENTIAL HPD_SRC ENABLE CNTRL CAD_SRC AUX_SRC SCL/SDA AUX_SNK CAD_SNK HPD_SNK OUT0P/N OUT1P/N OUT2P/N OUT3P/N IN0P/N IN1P/N IN2P/N IN3P/N Equalizer Pre-Emphasis Control Logic & Configuration Registers Aux Listener, Aux Pass-through, DDC pass-through Blocks Functional Block Diagram 15-0021
3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode www.pericom.com 02/27/15 COMPANY CONFIDENTIAL Package Pinout V3P3 DNC OC_1 OP_0 OP_1 V3P3 CNTRL CAD_SRC HPD_SRC CAD_SNK HPD_SNK V3P3 GND OUT0P OUT0N DNC OUT1P OUT1N GND OUT2P OUT2N DNC OUT3P OUT3N V3P3 AUTO_EQ SDA_DDC SCL_DDC V3P3 GND AUX_SRCP AUX_SRCN AUX_SNKP AUX_SNKN ENABLE V3P3 DNC IN0P IN0N EQ IN1P IN1N DNC IN2P IN2N OC_0 IN3P IN3N GND 15-0021
3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode www.pericom.com 02/27/15 COMPANY CONFIDENTIAL continued > Pin Description Pin # Pin Name Pin Ty pe Description 1 V3P3 Power 3.3V +/10% Power rail
2 DNC NC Do Not Connect; leave pin floating
3 OC_1 Input Swing control bit 1. Pulled-up internally with 100kOhm See truth tables for functionality 4 OP_0 Input Pre-emphasis control bit 1. Internally pulled-up with 100kOhm See truth tables for functionality 5 OP_1 Input Pre-emphasis control bit 0. Internally pulled-up with 100kOhm See truth tables for functionality 6 V3P3 Power 3.3V +/-10% Power rail
7 CNTRL Input Configure Output Voltage Swing and Pre-Emphasis (See truth table for functionality)
8 CAD_SRC Output
Cable Adapter Detection from DP connector CAD_SRC = "0" : no cable adapter; enable DP ReDriver mode with AUX listening and link training active CAD_SRC = "1" & Installed cable adapter; enable TMDS ReDriver mode and disable AUX interception 9 HPD_SRC Output Hot Plug detect to system DP source. 3.3V CMOS output. 10 CAD_SNK Input Cable detect from sink side.
11 HPD_SNK Input
Hot Plug Detect from the sink side 200kOhm Pull-down 12 V3P3 Power 3.3V +/- 10% Power rail
13 OUT3N Output Lane 3 data negative output
14 OUT3P Output Lane 3 data positive output
15 DNC NC Do Not Connect
16 OUT2N Output Lane 2 data negative output
17 OUT2P Output Lane 2 data positive output
18 GND Power Ground
19 OUT1N Output Lane 1 data negative output
20 OUT1P Output Lane 1 data positive output
21 DNC NC Do Not Connect
22 OUT0N Output Lane 0 data negative output
23 OUT0P Output Lane 0 data positive output
24 GND Power Ground
25 V3P3 Power 3.3V +/10% Power rail
26 ENABLE Input External Power Down pin "1"=Enable ; "0"=Disable ; Pulled-up internally with 100kOhm
27 AUX_SNKN I/O AUX negative channel connected to DP sink device
28 AUX_SNKP I/O AUX positive channel connected to DP sink device
3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode www.pericom.com 02/27/15 COMPANY CONFIDENTIAL Pin # Pin Name Pin Ty pe Description
29 AUX_SRCN I/O AUX negative channel connected to DP source device
30 AUX_SRCP I/O AUX positive channel connected to DP source device
31 GND Power Ground
32 V3P3 Power 3.3V +/10% Power rail
33 SCL_DDC I/O DDC clock channel from source side when CAD_SNK=1
34 SDA_DDC I/O DDC Data channel from source side when CAD_SNK=1
35 AUTO_EQ Input
Auto EQ Control pin. Enable = “1”, Disable = “0”. This pin is internally pulled up through 100kOhm. EQ-pin (Pin 40) can control Auto EQ mode 0, 1 and 2. 36 V3P3 Power 3.3V +/10% Power rail
37 DNC NC Do Not Connect
38 IN0P Input Lane 0 data positive input
39 IN0N Input Lane 0 data negative input
40 EQ Input Be able to configure Fixed EQ setting, when disable Auto-EQ mode (AUTO_EQ pin =“0”). This pin is internally biased to 50% of V3P3.
41 IN1P Input Lane 1 data positive input
42 IN1N Input Lane 1 data negative input
43 DNC NC Do Not Connect
44 IN2P Input Lane 2 data positive input
45 IN2N Input Lane 2 data negative input
46 OC_0 Input
Output Control pin. See Output Control truth table for functionality Internally pulled-high with 100kOhm
47 IN3P Input Lane 3 data positive input
48 IN3N Input Lane 3 data negative input
3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode Mode Control Pins Output Swing Pre-emphasis EQ setting CNTRL CAD SINK OC_1, OC_0 OP_1, OP_0 Normal Mode 0 1 X X X X 800mV 0dB Follow Auto EQ & Fixed EQ Table 0 0 X, X X,X Follow listener Follow listener Follow Auto EQ & Fixed EQ Table Test Mode 1 X 0 0 1 1 400mV 0dB\` Pin Control 1 X 0 0 0 0 400mV 3.5dB Pin Control
1 X 0 0 0 1 400mV 6dB Pin Control
1 X 0 0 1 0 400mV 9.5dB Pin Control
1 X 0 1 1 1 600mV 0dB Pin Control
1 X 0 1 0 0 600mV 3.5dB Pin Control
1 X 0 1 0 1 /
1 X 1 1 1 1 800mV 0dB Pin Control
1 X 1 1 0 X /
800mV 3.5dB Pin Control
1 X 1 0 XX 1200mV 0dB Pin Control
Fixed Eq. 2.5dB @ 2.7GHz Fixed Eq. 5.1dB @ 2.7GHz Fixed Eq. 7.2dB @ 2.7GHz Notes EQ L M H L M H EQ pin is internally biased to ~50% of V3P3 at "M(Middle)" or floating statue. Measured Gains 1.62G 2.7G 5.4G Unit M 2.41 3.9 5.16 dB H 6.96 9.28 10.8 dB Auto EQ H H H L L L Auto EQ pin has a internal pull-up. EQ Setting in Auto EQ Mode PRE-EMPHASIS_SET Bit[4:3] in DPCD registers Auto EQ mode 0 Auto EQ mode 1 Auto EQ mode 2 Control Pin Functional Tables www.pericom.com 02/27/15 COMPANY CONFIDENTIAL 15-0021
3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode www.pericom.com 02/27/15 COMPANY CONFIDENTIAL Functional Description Intelligent Power Management Pericom’s block based design and intelligent detection scheme allow portions, or all of the IC, to be disabled for power sav- ings. For example, in DP mode, if only one or two lanes are active, the other lanes will be automatically powered off. If there is no input video signal the entire IC will be powered down. If there is no monitor detected, Pericom’s PI3EQXDP1201 can also automatically power down the IC. This intelligent power management concept not only saves system power, but also stops the device from outputting useless data or noise when no signal is present at the input of the IC. The power-down mode can also be entered using hard pin EN - ABLE, or through DPCD register (AUX link training) DisplayPort AUX Listener PI3EQXDP1201 integrates an AUX listener(decoder), which enables the device to receive and deci - pher all AUX link training data and use this ex - tracted information for its own configuration. The intercepted DPCD data is used to adjust the active lane count, output swing level, output pre-emphasis level, and to manage the device’s D3 power saving state. AUX Listener Specification DP AUX listener will support Native AUX CH Syntax. Mapping of I 2C onto AUX CH Syntax is not supported. AUX listener monitors AUX channel from requester and replier for transactions and stored AUX command from requester and reply command from sinks that are related to the link settings. AUX listener recovered the clock from AUX data input by cycle counting the synchronization pulse at the beginning of the AUX cycle. In a AUX write request cycle, the AUX address compare the addresses with the following registers’ address, data is extracted and stored into the respective registers when the addresses matches. These registers are set during link training se - quence following hot plug detection. 00100h Data Rate Register 00101h LANE_COUNT_SET 00103h TRAINING_LANE0_SET 00104h TRAINING_LANE1_SET 00105h TRAINING_LANE2_SET 00106h TRAINING_LANE3_SET 00260h Sink Test request response 00600h Power Down The AUX listener support Sink request Test sequence. After HPD IRQ event and DP source read 00201h AUX register and if bit 1 is high, the DP source will enter a Sink request test mode and initiate a sequence of AUX read request cycle. During the read cycle, data matching the fol- lowing registers address are stored in the listener. 00206h ADJUST_REQUEST_LANE0_1 00207h ADJUST_REQUEST_LANE2_3 00218h Test Request 00219h Test link rate 00220h Test Lane count After the read request cycle, the DP source will write 1 to Bit 0 register 00260h if the DP source enters sink request mode, or 1 to Bit 1 of register 00260h if the source declined the sink test request. The data stored in registers 002xx above will override the value set in 00101h to 00106h reg- isters when the sink entered the Sink Test mode. Sink Test Request Acknowledgement 00260h mode Buffer configuration outputs xxxxxx00b No action 00100 : 00106h xxxxxx01b Sink Test mode 00206h,00207h,00219h,00220h Override 00100,1,3,4,5,6h register settings xxxxxx10b Sink test mode declined 00100h : 00106h xxxxxx11b Not Legal code 00100h : 00106h 15-0021
3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode www.pericom.com 02/27/15 COMPANY CONFIDENTIAL A complete two way AUX transaction is defined as one of the following AUX write and Sink issue ACK reply From Source Sync Start/Start Pattern 4-bit cmd 1000 20-bit address 8-bit length Data Stop From sink ACK Sync Start bit 00000000 Stop 2. AUX write and Sink issue NACK reply For Write transaction: A data byte “M” must follow AUX NACK, “M” indi- cates the number of data bytes successfully written. When a Source Device is writing a DPCD address not supported by the Sink Device, the Sink Device shall reply with AUX NACK and “M” equal to zero. From Source Sync Start bit 4-bit cmd 1000 20-bit adr 8-bit length Data Stop From sink NACK Sync Start bit 00010000 8-bit data byte M Stop 3. AUX Read and Sink issue ACK reply For Read transaction: Ready to reply to Read request with data following. DisplayPort receiver may assert a STOP condition before transmitting the total number of requested data bytes when not all the bytes are available. From Source Sync Start bit 4-bit cmd 1001 20-bit ad- dress 8-bit length Stop From sink ACK Sync Start bit 00000000 Data Stop 4. AUX Read and Sink issue NACK reply For Read transaction: A Sink Device receiving a Native AUX CH read request for an unsupported DPCD address must reply with an AUX ACK and read data set equal to zero instead of replying with AUX NACK. From Source Sync Start bit 4-bit cmd 1001 20-bit address 8-bit length Stop From Sink NACK Sync Start bit 00001000 data = 0 Stop Typical AUX Test request handshake se- quences with HPD_IRQ AUX listener stores the last transaction in the register to identify the current transaction type. Sink side Source side AUX reply 00218h AUX ACK 00218h to 0027Fh AUX read 00218h to 0027Fh AUX write 00260h AUX write 00260h Enable Test registers If bit0=1, do nothing if bit1=1. AUX reply 00201h AUX ACK 00201h.. AUX ACK 00201h 15-0021
3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode www.pericom.com 02/27/15 COMPANY CONFIDENTIAL Start up Sequence and Hot Plug Detect (HPD) Usage After Power on, HPD_SNK control state machine goes to Low Power state 1 and then state 2, and then monitor HPD_ SNK. At Power on Reset state, low power state 1 and low power state 2, all outputs are HiZ, equalizer is powered down, HPD _SRC is HiZ. At Lower Power Mode State 2, if HPD_SNK is asserted, it will turn output signals active. If output port is active and HPD_SNK = 0, then it will go to a debounce timer and wait for 300ms, if HPD_SNK is still =0, the controller will return to Low Power mode wait state 2. If HPD_SNK is 1 then the controller will return to output port active state. HPD_SNK will pass through HPD _SRC. Low Power Mode 2 HPDA=1 Port A active Port A wait HPDA=0 Power On Reset Low Power Mode 1 HPDA=1 HPDA=0 Wait 2ms HPD Detection & Control Circuit State Diagram 15-0021
3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode www.pericom.com 02/27/15 COMPANY CONFIDENTIAL Symbol Parameters Condition Min. Ty p. Max. Units V3P3 3.3V Power Supply 3.0 3.3 3.6 V Control Pin ENABLE VIH LVTTL input high voltage 2.4 V3P3 V VIL LVTTL input low voltage GND 0.8 V IIH Input High-level current VIH=2V to V3P3 -5 5 uA IIL Input Low-level current VIL=GND to 0.8V -50 -15 uA HPD_SRC and HPD_SNK Pins VIH LVTTL input high voltage 2.4 V3P3 V VIL LVTTL input low voltage 1/3*V3P3 2/3*V3P3 V IIH Input High-level current GND 0.6 uA IIL Input Low-level current 20 40 uA VOH LVTTL high level output voltage IOH=-8mA 2.4 V VOL LVTTL low level output voltage IOL= 8mA 0.4 V AUXP/N, SCL/SDA When Configure SCL/SDA pins IIH Input High-level current VIH=V3P3 -1 1 uA IIL Input Low-level current VIL=0 -1 1 uA When configure as Aux pins Vcom Common mode voltage 0 2.0 V VAUX-PP Peak to peak differential voltage 0.19 1.26 V RON On resistance Vin = -0.3V to +0.4V ION=-40mA 11 20 Ω BW 3dB Bandwidth 1 dB V3P3 I/O supply voltage to ground potential DC Signal Voltage Current Output Power Dissipation Continous Operating Temperature ESD Protection2 Note: 1) Stresses greater than those listed under MAXIMUM RAT - INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2) ESD results are for single supply mode only Maximum Ratings(1) (Above which useful life may be impaired. For user guidelines, not tested.) 15-0021
3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode www.pericom.com 02/27/15 COMPANY CONFIDENTIAL Symbol Parameters Condition Min. Ty p. Max. Units DP differential Input VID Peak to peak differential input voltage 400 1200 mV VODO Differential overshoot voltage 15%*V3P3 V3P3 VODU Differential undershoot voltage 25%*V3P3 V3P3 Ioff Single end standby current 10 uA Isc Output short current 60 mA DP differential Output Vtx diff-lev1 Differential pk-pk level 1 340 400 460 mV Vtx diff-lev2 Differential pk-pk level 2 510 600 680 mV Vtx diff-lev3 Differential pk-pk level 3 690 800 920 mV Vtx diff-lev4 Differential pk-pk level 4 1020 1200 1380 mV Pre-emphasis level 0dB Vtx diff = 0.8V 0 0 0 dB 6dB (2x) Vtx diff = 0.8V 4.8 6 7.2 dB DP differential output CML driver AC Switching Characteristics Trise / Tfall Rise and Fall Time 20% to 80 % 80 115 150 ps Tsk(D) Intrapair differential skew 50 ps Tsk(O) Intrapair differential skew 50 ps Power Consumption Symbol Condition Min Ty p Max Units Icc_V3P3 ENABLE = High, HPD_SNK = High
4 DP lanes active, Pre-emphasis = 0dB,
Output Swing = 400mV 5.4Gbps 340 mA2.7Gbps 310 1.62Gbps 300 Icc_V3P3_ SB ENABLE = Low 1.4 5 mA Iccq_V3P3 ENABLE = High, HPD_SNK = Low 4 20 mA PowerDown_V3P3 AUX Reg 600h = 02h, ENABLE= High, HPD_SNK = High, CNTRL = Low 5 mA 15-0021
3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode Swing=400mV, Preemph=0dB Swing=600mV, Preemph=0dB Swing=800mV, Preemph=0dB Swing=1200mV, Preemph=0dB Swing=400mV, Preemph=3.5dB Swing=600mV, Preemph=3.5dB Swing=800mV, Preemph=3.5dB Swing=400mV, Preemphasis=6dB Swing=600mV, Preemph=6dB Swing=400mV, Preemphasis=9.5dB Measured Output Waveforms As following is shown the actual measured output waveforms on the condition of 5.4Gbps with PRBS27-1 pattern. Auto EQ=High; CAD_Snk=0; HPD=High; OC_1=High; OC_0=OP_0=Low; OP_1=Low; Input Level is 0.6V differential peak- peak with 12-in FR4 Length and 36-in output Coaxial Cable www.pericom.com 02/27/15 COMPANY CONFIDENTIAL 15-0021
3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode www.pericom.com 02/27/15 COMPANY CONFIDENTIAL Packaging Mechanical: 48-Contact TQFN (ZBE) Notes: 2012 DATE: 03/25/10 DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZB48 DOCUMENT CONTROL #: PD-2080-T REVISION: A
Ordering Information
Ordering Code Package Code Package Ty pe PI3EQXDP1201ZBE ZB Pb-free & Green, 48-pin TQFN 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. Adding an X suffix = Tape/Reel Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 15-0021
3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode www.pericom.com 02/27/15 COMPANY CONFIDENTIAL
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3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode www.pericom.com 02/27/15 COMPANY CONFIDENTIAL Appendix: 1. Displayport Compliance Test Report Notebook application example Notebook Docking application example 15-0021
3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode www.pericom.com 02/27/15 COMPANY CONFIDENTIAL 2. Reference Schematics Dual-mode DP Source Application Diagram with Combined AUX and DDC Channels from Source Dual-mode DP Source Application Diagram with Separate AUX and DDC Channels from Source 15-0021
Revision History
2015/2/4 Removed 3.3/1.5V power supply and SMBus option for new design. Please contact Pericom if you need this func - tion support. PI3EQXDP1201 3.3V , 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode www.pericom.com 02/27/15 COMPANY CONFIDENTIAL 15-0021