PT7C4050

PT7C4050 PERICOM | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 13

Technical content

Features

• PLL with quartz stabilized VCXO
• Crystal output jitter less than 20ps
• Dual redundant reference input clocks with loss of signal detection
• Manual or automatic switch over between reference input clocks
• VCXO provides smooth output transition during switch over of input clocks
• Lock detection
• Selectable metal mask options for phase detectors, op. Amps, and charge pump
• Loss of signals alarm
• Return to nominal clock upon LOS
• Input data rates from 8 kb/s to 40 Mb/s
• Tri-state output
• User defined PLL loop response
• NRZ data compatible
• +3.3 and +5.0V supply voltage

Description

The device is composed of phase-lock loop with integrated VCXO for use in clock recovery, data re- timing, frequency translation and clock smoothing applications in telecom and datacom systems. Crystal Frequencies Supported: 12.624~38.880MHz.

Ordering Information

PT7C4050xLE Lead free 28-Pin TSSOP Note: Pls see below specification of part no.

Applications

• Frequency translation
• Clock Smoothing, Clock Switching
• NRZ Clock Recovery
• Optical Switching/Routing, Base Station

PT0239L (06/07) Ver: 0 Data Sheet PT7C4050 PLL with Integrated VCXO Block Diagram OPN OPP VC CLK1 CLK2 OPOUT CLKIN RCLK DATAIN HIZ RDAT A LOS Op Amp VCXO Divider Phase Detector & Loss Of S ignal Circuit PHO LOS IN Pin Configuration

PT0239L (06/07) Ver: 0 Data Sheet PT7C4050 PLL with Integrated VCXO Pin Description Pin Sym Description

1 X1 Crystal oscillator connected between X1 and X2

2 VC Control voltage input. It controls crystal oscillator (VCXO). 3 NC Not connected. 4 AGND Analog ground. 5 OPN Negative input. terminal to internal operational amplifier. 6 OPOUT Output. terminal of internal operational amplifier. 7 OPP Positive input. terminal to internal operational amplifier. 8 S1 9 S2 10 S3 S1, S2, S3 Options for selectable divider N

11 LOS-IN1

(LOSIN) TTL input. Internal pull down. Normally this pin is connected to OUT1 and selects REF-CLK1 input 12 PHO Output. signal produced by phase detector of data.

13 REF-CLK1

(DATAIN) Input clock signal. to phase detector (TTL switching thresholds for recovering DATAIN)

14 FB-CLK

(CLKIN) TTL switching thresholds input. Connected to external feedback clock. 15 DGND Digital ground. 16 LOS Loss of signal detection. for DATAIN input. Refer to LOS detection description.

17 RCLK

(CLK-OUT3) Output recovered clock.

18 RDATA

(CLK-OUT4) Output recovered data stream. 19 DVDD Digital power supply. 20*1 CLK-OUT2 Output clock of internal VCXO frequency controlled by S3, S2, S1 while S4 set logic high

21 HIZ

TTL input. When set to a logic low, output pins CLK-OUT1, CLK-OUT2, RCLK, and RDATA buffers are set to high-impedance state. When set to logic high or no connection, the device functions and output pins CLK-OUT1, CLK-OUT2, RCLK, and RDATA etc. are active. This input has an internal pull-up resistor. 22 CLK-OUT1 Output clock. of internal VCXO or half VCXO frequency, controlled by SEL-OUT1. 23*2 SEL-OUT1 CMOS input. ‘LO’ selects half of internal VCO frequency. ‘HI’ selects internal VCO frequency. Internal pull up. 24 GND Ground.

25 AVDD

(XT-VDD) Analog power supply. 26 NC Not connected. 27 NC Not connected.

28 X2 Crystal oscillator connected between X1 and X2

Note: *1: S3, S2, S1 option for selectable divider N, Please refer to Table 1 *2: SEL-OUT1 option for VCXO or half VCXO output freq. Please refer to Table 2 ( ): For pin11/13/14/17/18/25, die option

PT0239L (06/07) Ver: 0 Data Sheet PT7C4050 PLL with Integrated VCXO Pad Location IFr VC REF-indicator1 LF OPN OPOUT NC1 AGND2 REF-indicator2 AGND1 REF-SEL LOS-OUT1 LOS-OUT2 RCLK(CLK-OUT3) RDATA(CLK-OUT 4) DVDD1 DVDD2 Sel_050 NC6 CLK-OUT2 NC7 LD HIZ NC8 NC9 CLK-OUT1 SEL-OUT1 GND(CDL) XT-GND XT-VDD AVDD X1-1 LOS-IN1(LOSIN) NC3 Alarm-res CTRL-SEL OPP NC2 LOS-IN2 PHO NC4 REF-CLK1(Datain) NC5 FB-CLK(Clkin) DGND1 DGND2 REF-CLK2 X1-2 X2-2 X2-1 S4 LOS* PT7C4050 Die size: 2190×3401µm(Including scribe line). Die thickness: 300µm(no coating). Table 1 Bonding Options for selectable divider N S3 S2 S1 Divider N 1 1 1 2 1 1 0 4 1 0 1 8 1 0 0 16 0 1 1 32 0 1 0 64 0 0 1 128 0 0 0 256 Table 2 Bonding Options for CLK-OUT1 SEL-OUT1 CLK-OUT1 frequency

1 Internal VCXO frequency

0 Half of internal VCXO frequency

PT0239L (06/07) Ver: 0 Data Sheet PT7C4050 PLL with Integrated VCXO Function Description LOS detection LOS-OUT1 provides output alarm flag when REF-CLK1 is lost. The LOS output is set to logic high after 256 consecutive FB-CLK (CLKIN) periods with no REF-CLK1 (DATAIN) transitions. As soon as a transition occurs at REF-CLK1 (DATAIN), LOS is reset to a logic low. Divider output signals outputs to CLK-OUT3 pin, F16N outputs to CLK-OUT4 pin. The F8, TSP, RSP can be selected by S4:1 (bond option) and output to CLK-OUT2 pin. 8KHZ frame signals’ generator based on 32MHZ VCXO frequency. All signals are compatible with 4409 DPLL product.

PT0239L (06/07) Ver: 0 Data Sheet PT7C4050 PLL with Integrated VCXO Maximum Rating DC Characteristics Sym Parameter Test Condition Min Typ Max Unit - 4.5 - 5.5 VDD Supply Voltage - 3.0 3.6 V ILEAK Input Leakage Current - -10 - 10 µA VTIH TTL Input High Voltage - 2 - - V VTIL TTL Input Low Voltage - - - 0.8 V VCIH CMOS Input High Voltage - 0.7V DD - - V VCIL CMOS Input Low Voltage - - - 0.3V DD V VOH1 Output High Voltage for CLK-OUT1/2/3/4 Ioh = 8mA 2.4 - - V VOL1 Output Low Voltage for CLK-OUT1/2/3/4 Iol = 8mA - - 0.4 V IPULLUP1 Input Pull up Current for HIZ - -160 - - IPULLUP2 Input Pull up Current for S4:0, Test V i = 0V -50 - - IPULLDOWN Input Pull down Current for LOS-IN1 V i = VDD - - 50 µA ICC Maximum Supply Current Full Active - - 60 mA TA Ambient Temperature - -40 - 85 oC Note: Stresses greater than those listed under MAXI- MUMRATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

PT0239L (06/07) Ver: 0 Data Sheet PT7C4050 PLL with Integrated VCXO AC Characteristics Sym Parameter Test Condition Min Typ Max Unit DATAIN Input NRZ Data Rates - 0.008 - 65.536 Mb/s REF-CLK Input RZ Data and Clock Rates - 0.008 - 32.768 Mb/s OUT1 Nominal Output Frequency CLK-OUT1 - 12.0 - 61.44 MHz OUT2 Nominal Output Frequency CLK-OUT2 - out1 /8192 - out1 /2 MHz tR Rise Time 0.5V to 2.5V 0.5 - 5 ns tF Fall Time 2.5V to 0.5V 0.5 - 5 ns SYM 1 CLK-OUT1 (Symmetry or Duty cycle) VC = 1.4V 40 - 60 % SYM 2 CLK-OUT2 (Symmetry or Duty cycle) VC = 1.4V 45 - 55 % RCLK RCLK (Symmetry or Duty cycle) VC = 1.4V 40 - 60 % BW Control Voltage Bandwidth -3 dB, VC = 1.65 V - 25 - kHz ∆F/∆V C Sensitivity VC = Vdd/2 - - 100 ppm/V NR VCXO Negative Resistor - - - -40 Ohm OUT1 -75 - 75 ppm from fo 1 OUT2 Nominal Output Frequency on Loss of Signal: CLK-OUT1/2 -75 - 75 ppm from fo 2 Phase Detector Gain Internal design value - - 0.53 x Data Density V/rad KD Phase Detector Gain offset Internal design value, DATAIN and CLKIN is “0” degree phase difference, OP-Amp gain=2/3 - - TDB V GB Loop Filter Op-Amp Unity Gain Band Width Internal design VALUE. - 750 - KHz

PT0239L (06/07) Ver: 0 Data Sheet PT7C4050 PLL with Integrated VCXO Application Circuit CLKI N14 DATAI N13 PHO12 LOSIN11 S310 S29 S18 OPP7 OPO6 OPN5 AGND4 NC3 VC2 X11 DGND 15LOS 16RCL K 17RDATA 18DVDD 19CLK- OUT2 20HI Z 21CLK- OUT1 22SEL-OUT1 23XTGND 24VDD 25NC 26NC 27X2 28 PT7C4050 C3 0. 1uF R1 Optiona l R2 Optiona l C4 0. 1uF VCC R3 Optiona l C5 Optiona l Optiona l 22nF VCC LOS OUT1 Y1 32.768MHz Normal Test Cir cui t C1 C2Optiona l Optiona l DATAI N CLKW 1 2 1 2 1 2 LOS PHO OPN VC VC CLKI N14 DATAI N13 PHO12 LOSIN11 S310 S29 S18 OPP7 OPO6 OPN5 AGND4 NC3 VC2 X11 DGND 15LOS 16RCL K 17RDATA 18DVDD 19CLK- OUT2 20HI Z 21CLK- OUT1 22SE L-OUT 1 23XTGND 24VDD 25NC 26NC 27X2 28 PT7C4050LE C3 0. 1uF R1 5. 1K R2 5. 1K C4 0. 1u F VCC R3 120K C5 0. 1uF 18K 22nF VCC LOS Y1 32.768MHz Applicat ion circuit for PT7C4050 C1 C2Optiona l Optiona l VC VC LOS PHO X- 2MHz R6 33 R7 33 32MHz X32MHz 4MHz CLKIN Input: 2MHz Output: 32.768MHz S1aS2aS 3 Jum p for selectable divider N S 1 00001111 S 2 00110011 S 3 01010101 Di vi der N 256 1 2 1 2 1 2 8 6 43 21 68 4 2

PT0239L (06/07) Ver: 0 Data Sheet PT7C4050 PLL with Integrated VCXO CLKI N14 DATAI N13 PHO12 LOSIN11 S310 S29 S18 OPP7 OPO6 OPN5 AGND4 NC3 VC2 X11 DGND 15LOS 16RCL K 17RDATA 18DVDD 19CLK- OUT2 20HI Z 21CLK- OUT1 22SEL-OUT1 23XTGND 24VDD 25NC 26NC 27X2 28 PT7C4050LE C3 0. 1uF R1 5. 1K R2 5. 1K C4 0. 1uF VCC R3 180K C5 2. 2uF 22nF VCC Y1 38.88MHz 38.88/19.44 C1 C2Optional Optional RUOPN R4 22 0K RUPHO SYN16K R5 4. 7KVCC 8KREF VC_CK R7 12.1K R8 12.1K 0. 1uF RUOPN RUPHO KGND CLKI N14 DATAI N13 PHO12 LOSIN11 S310 S29 S18 OPP7 OPO6 OPN5 AGND4 NC3 VC2 X11 DGND 15LOS 16RCL K 17RDATA 18DVDD 19CLK- OUT2 20HI Z 21CLK- OUT1 22SEL-OUT1 23XTGND 24VDD 25NC 26NC 27X2 28 PT7C4050ALE C3 0. 1uF R1 5. 1K R2 5. 1K C4 0. 1uF VCC R3 100K C5 0. 1uF 11K 22nF VCC LOS 16.384M_1 8. 192M_1 RRDATA1 RRCLK1 Y1 16.384MHz 16.384/8.192 C1 C2Optiona l Optiona l EYE1 CLKI N1

PT0239L (06/07) Ver: 0 Data Sheet PT7C4050 PLL with Integrated VCXO CLKI N14 DATAI N13 PHO12 LOSIN11 S310 S29 S18 OPP7 OPO6 OPN5 AGND4 NC3 VC2 X11 DGND 15LOS 16RCL K 17RDATA 18DVDD 19CLK- OUT2 20HI Z 21CLK- OUT1 22SEL-OUT1 23XTGND 24VDD 25NC 26NC 27X2 28 PT7C4050LE C3 0. 1uF R1 5. 1K R2 5. 1K C4 0. 1uF VCC R3 30K C5 0. 1uF 3. 9K 22nF VCC LOS SHR1 R4 0M1 Y1 40.096MHz 40.096/2.560 C1 C2Optiona l Optiona l XRSIG CLKW LOS PHO CLKI N14 DATAI N13 PHO12 LOSIN11 S310 S29 S18 OPP7 OPO6 OPN5 AGND4 NC3 VC2 X11 DGND 15LOS 16RCL K 17RDATA 18DVDD 19CLK- OUT2 20HI Z 21CLK- OUT1 22SE L-OUT 1 23XTGND 24VDD 25NC 26NC 27X2 28 PT7C4050LE C3 0. 1uF R1 5. 1K R2 5. 1K C4 0. 1u F VCC R3 120K C5 0. 1uF 18K 22nF VCC LOS Y1 32.768MHz 32.768/2.048 C1 C2Optiona l Optiona l 4MHz VC VC LOS PHO OPN X- 2MHz R6 33 R7 33 32MHz X32MHz

PT0239L (06/07) Ver: 0 Data Sheet PT7C4050 PLL with Integrated VCXO CLKI N14 DATAI N13 PHO12 LOSIN11 S310 S29 S18 OPP7 OPO6 OPN5 AGND4 NC3 VC2 X11 DGND 15LOS 16RCL K 17RDATA 18DVDD 19CLK- OUT2 20HI Z 21CLK- OUT1 22SEL-OUT1 23XTGND 24VDD 25NC 26NC 27X2 28 PT7C4050ALE R1 5. 1K R2 5. 1K VCC R3 47 0K C3 1u F/ 16V 22.1K 22nF VCC Y1 16.384MHz 16.384/2.048 C1 C2Optional Optional R6 33 PHO 32K CLK_ 32 K R5 22 .1 K 0. 1uF 2. 048MHz Recommended Crystal Specifications Description Crystal Mode of Oscillation Fundamental, AT cut Frequency Range 12.0000 to 41.0000MHz Frequency Tolerance ±20ppm (Max, 25¥) Operating Temperature -40¥ to 85¥ Load Capacitance (CL) 12pF Frequency Range (MHz) Motional Capacitance Shunt Capacitance R R max 12.0000 – 13.0000 11 fF 2.4 pF 50 Ω 13.0001 – 15.0000 12 fF 2.6 pF 50 Ω 15.0001 – 17.0000 13 fF 3.0 pF 40 Ω 17.0001 – 20.0000 14 fF 3.2 pF 40 Ω 20.0001 – 23.0000 15 fF 3.5 pF 30 Ω 23.0001 – 26.0000 16 fF 4.0 pF 30 Ω 26.0001 – 41.0000 17 fF 4.5 pF 25 Ω

PT0239L (06/07) Ver: 0 Data Sheet PT7C4050 PLL with Integrated VCXO Mechanical Information LE (28-Pin TSSOP)

PT0239L (06/07) Ver: 0 Data Sheet PT7C4050 PLL with Integrated VCXO Notes Pericom Technology Inc. China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 U.S.A.: 3545 North First Street, San Jose, California 95134, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100 Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation.