PT7A6632 PERICOM | Alldatasheet
Document overview
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Technical content
Features
- Provides up to 32 full-duplex HDLC/SDLC channels Compatible with 1.544 Mb/s T1 and 2.048Mb/s CEPT PCM-30 carrier format Provides on-board buffer memory management Supports standard hyperchannel configuration and fully programmable hyperchannel configuration Provides on-board CRC-16, automatic flag and zero insertion and deletion functions in HDLC format Provides programmable tri-state outputs to T1/E1 serial interface and FILL/MASK, thus enabling up to 8 devices connecting to a TDM bus Provides data rate adaptation functions Compatible with HDLC, SNA SDLC, X.25, X.75, LAPB, and LAPD protocols Support non-HDLC signaling channels Single +5V power supply Package: 68-pin PLCC Introduction The PT7A6632 HDLC controller operates at layer 2 (data link protocol level) of the Open Systems Inter- connection (OSI) reference model. It supports HDLC and ISDN implementations. The PT7A6632 processes data transmitting and re- ceiving on a T1 or E1 communication link. It con- nects between the T1/E1 serial bus and an external memory shared with CPU(s), multiplexing / demultiplexing up to 32 fully-duplex high-speed data channels. It provides additional functions that support X.30 and X.31 rate adaptation and fully flexible hyperchannels.
Applications
Primary rate interfaces Basic-rate D-channel controller Multi-channel HDLC interfaces CPU External Shared Memory HDLC PT7A6632 D0-D7 A0-A15 E1/T1 Trunk Interface T1/CEPT PCM-30 Line Figure 1. Application Diagram of PT7A6632
PT7A6632 32-Channel HDLC Controller PT019(05/02) V er:2
Contents
PT7A6632 32-Channel HDLC Controller PT019(05/02) V er:2
Figure 2. Block Diagram of PT7A6632 Table 1. Pin Assignment
Figure 3. Pin Configuration
Table 2. Pin Description
36 CN noitcennocoNn oitcennocoN noitcennocoN noitcennocoNn oitcennocoN
Table 2. Pin Description (Continued)
rate, then transmits the data to the T1/E1 trunk interface. Figure 4. PT7A6632 Interface Signals mode can be set up in external memory independently by CPU.
Figure 11. Standard Hyperchannel Provisory changed (when HCS1 HCS0 = 00) to create flexible hyperchannels by programming command buffers. Table 3. Hyperchannel Selection as well as T1/CEPT pins. See Table 3 and Figure 11.
Table 4. Output Selection on TSER the transmit command buffer for details (Figure 24). flags is specified in the transmit data buffer. flag number will be adjusted according to the counting result. Reset the device will make all channels in HDLC mode. ensure uninterrupted data transmit. ganization and Definition” and Tables 8 and 14. Loop Mode does not support hyperchannel. loop channel defined, the loop operation can not be performed. Reset the device will delete all Loop Mode. flexible hyperchannels, as well. transmitted first; the LSB transmitted last.
Figure 12. Block Diagram of Receive Bit-Level Processor the Section “External Memory Organization and Definition”. trunk interface is not correlated with that of a transmit frame. of the RCLK. See Figure 14-17. The RSYNC is used for receive frame synchronization. ternal Memory Organization and Definition”. as well as T1/CEPT pins. See Table 3 and Figure 11. ganization and Definition” for details (Figure 27).
Figure 17. Receive Frame Synchronization Timing - CEPT PCM-30 Mode, SIS = 0 tical. The Loop Mode does not support hyperchannel. Reset the device will delete all Loop Mode. Reset the device will make all channel in inversion mode. memory in the same order in which they are received in time. (D7) position of the data byte.
ferred as Activation Memory and Data Processing Memory. Details are shown in Figures 20-22.
128 Bytes of System Memory
Figure 20. External Memory Map - Top Level
The Activation Memory map is shown in the Figure 21. table 5. The PT7A6632 reads this byte so that gets the channel when it accesses the Activation Memory. Table 5. Channel Activation Byte
PT7A6632 32-Channel HDLC Controller PT019(05/02) V er:2 Figure 21b. Activation Memory Map Locations (MDFS = LOW) 7 6 5 4 3 2 1 0 XX00 Active x Rx/Tx Channel Number XX01 XX7F Byte Addresses xx01 Through xx7F Are Not Used by PT7A6632 XX80 Transmit Channel 0 Start Address (Low-Order Byte) XX81 Transmit Channel 0 Start Address (High-Order Byte) XX82 Transmit Channel 1 Start Address (Low-Order Byte) XX83 Transmit Channel 1 Start Address (High-Order Byte) Transmit Channels 2 to 30 Start Addresses XXBE Transmit Channel 31 Start Address (Low-Order Byte) XXBF Transmit Channel 31 Start Address (High-Order Byte) XXC0 Receive Channel 0 Start Address (Low-Order Byte) XXC1 Receive Channel 0 Start Address (High-Order Byte) Receive Channels 1 to 30 Start Address XXFE Receive Channel 31 Start Address (Low-Order Byte) XXFF Receive Channel 31 Start Address (High-Order Byte) ~~ ~~ ~ ~~ ~ ~~ b. MDFS = LOW (iAPX 86 Based) (Address) (HEX) (Contents) Channel Activation Byte Channel Buffer Pointers
8 Bytes of Buffer Descriptor*
2 Bytes of Channel Mode
Figure 22. Organization and Linking of Data or Command Buffers
Table 6. Descriptors in Transmit Data Buffer
Figure 24. Transmit Command Buffer
Table 7. Descriptors in Transmit Command Buffer respectively. See Table 7 for the definition.
Table 8. MODE Byte in Transmit Command Buffer loop, inversion or non-inversion. The details are shown in Table 8.
Table 9. Examples of FILL/MASK Options Bit-Level Processor” and Table 9.
a channel to be grouped into or removed from a hyperchannel. tively. See Table 10 for details. Data Length > 2, there is hyperchannel process. group any number of 32 64kb/s channels into a hyperchannel. be restored once the channel is released from the hyperchannel. will override the flexible hyperchannel. buffer, the HDLC ABORT or non-HDLC all-ones will be sent. the current buffer type and next buffer type. Refer to Figure 25.
3 Bytes
6 Bytes
2 Bytes
5 Bytes
Figure 25. Minimum Data Bytes for Transmit Buffer
Figure 26. Receive Data Buffer Status respectively. See Table 11 for the definition.
Table 11. Descriptors in Receive Data Buffer
Figure 27. Receive Command Buffer
Table 12. Descriptors in Receive Command Buffer respectively. See Table 12 for the definition.
Table 13. MODE Byte in Receive Command Buffer non-loop, inversion or non-inversion. The details are shown in Table 13.
Table 14. Receive Buffer Data Arrangement for Non-HDLC Bit-Oriented Signaling Channel
PT7A6632 32-Channel HDLC Controller PT019(05/02) V er:2 FILL/MASK Byte (Rate Definition) The PT7A6632 FILL/MASK byte is used as a masking pattern on the HDLC-formatted (including FLAG, header, data, CRC, and ABORT code) or non-HDLC-formatted data in order to adapt subrates that are multiples of 8kb/s to the 64kb/s rate. The 8-bit sequence is applied to data on a bit by bit basis to remove time-fill (FILL/MASK bit = 0) bits. See an example in Figure 13 in Section “Receive Bit-Level Processor” and Table For bit-oriented signaling mode, the FILL/MASK should be set as 1111 1111, otherwise the PT7A6632 will not override any other FILL/MASK pattern. Flexible Hyperchannel Configuring Byte (Optional) The byte follows the FILL/MASK byte if any. It is used to configure flexible hyperchannel. Bits 0 - 4 specify number of a channel to be grouped into or removed from a hyperchannel. Bits 6 and 7 is for hyperchannel enable and add/delete respec- tively. See Table 10 for details. reffuBataDevieceRr effuBataDevieceR reffuBataDevieceR reffuBataDevieceRr effuBataDevieceR dnammoCevieceRd nammoCevieceR dnammoCevieceR dnammoCevieceRd nammoCevieceR reffuB reffuB eziS )srotpircseD(setyB8 )ataD(setyB6+ )srotpircseD(setyB8 )dnammoC(setyB2+ Data Length is used to specify flexible hyperchannel. When Data Length = 0, 1 or 2, only non-hyperchannel process. When Data Length > 2, there is hyperchannel process, while the Data Length indicates how many additional channels to be added to the hyperchannel. See Section “Flexible Hyperchannel” in Transmit Command Buffer. Minimum Buffer Size The size of receive data buffer must ensure normal buffer main- tenance and buffer transition without losing data. Table 15
and reception by CPU asserting the A TTN signal. negation of A TTN. The channel initialization is completed. The process is illustrated in Figure 28. ! CPU prepares data buffer and writes to activation byte for a channel. of the first buffer allocated for the channel. # PT7A6632 informs task completion by asserting ATACK. Figure 28. Channel Initialization
Figure 29. Typical Linked Buffer Transmit Sequence 2: PT7A6632 reads activation byte (xx00). or data), then sets ATACK, & starts processing that buffer. 4: PT7A6632 resets ATACK after ATTN goes low. controlled by the status of each. buffer if necessary. See figure 30 for example.
Figure 30. Typical Linked Buffer Receive Activity 2: PT7A6632 accesses Activation Memory (xx00). or data), then sets ATACK, & starts processing that buffer. 4: PT7A6632 resets ATACK after ATTN goes low. controlled by the status of each.
agement and data processing. to the memory for Rx channels.
8 TCLK Periods
A TTN signal asserted by the CPU. negate it after Activation Memory access completed. Figure 31. Channel Period
- Activated by status write only.
Figure 43. PT7A6632 External Memory Example Interface Waveforms - Write/Read Double Memory Access Plus a Table 16. Recommended Operating Conditions extended periods may affect reliability. oC and are for design aid only; not production tested.
Table 17. DC Electrical, Power Supply and Capacitance Characteristics Typical figures are at 25oC and are for design aid only; not production tested.
- IOL and IOH are obsolute values.
Table 18. Transmit Frame Synchronization Timing Figure 44. Diagram of Transmit Frame Synchronization Timing (SIS = 1)
- Clock Timing
Table 19. Clock Timing Figure 45. Clock Timing
Table 20. TCLK - RCLK Timing Figure 46. TCLK - RCLK Timing
Table 29. Receive Frame Synchronization Timing Figure 47. Diagram of Receive Frame Synchronization Timing (SIS=1)
Table 22. Read Cycle Timing Figure 48. Read Cycle Timing
Table 23. Write Cycle Timing Figure 49. Write Cycle Timing
Table 24. Channel Activation/Deactivation Timing Figure 50. Channel Activation/DeactivationTiming
Table 25. Input Characteristics
Table 26. Output Characteristics
Figure 51. 68-Pin PLCC
PT7A6632 32-Channel HDLC Controller PT019(05/02) V er:2
Ordering Information
Table 27. Ordering Information
PT7A6632 32-Channel HDLC Controller PT019(05/02) V er:2 Pericom Technology Inc. China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 U.S.A.: 2380 Bering Drive, San Jose, California 95131, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100 Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. Notes