PSB4860

PSB4860 SIEMENS | Alldatasheet

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Digital Answering Machine with Full Duplex Speakerphone SAM EC PSB 4860 Version 2.1 Data Sheet 10.97 DS 1

Edition 10.97 This edition was realized using the software system FrameMaker . Published by Siemens AG, HL TS © Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components 1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be en- dangered. PSB 4860 Revision History: Current Version: 10.97 Previous Version: Preliminary Data Sheet 09.97 Page (in previous Version) Page (in new Version) Subjects (major changes since last revision) Index added

Semiconductor Group 3 10.97

Semiconductor Group 4 10.97

2.4.1 IOM

IOM ® , IOM® -1, IOM® -2, SICOFI® , SICOFI® -2, SICOFI® -4, SICOFI® -4µC, SLICOFI® , ARCOFI® , ARCOFI® -BA, ARCOFI ® -SP, EPIC® -1, EPIC® -S, ELIC® , IPAT® -2, ITAC® , ISAC® -S, ISAC® -S TE, ISAC® -P, ISAC® -P TE, IDEC® , SICAT ® , OCTAT® -P, QUAT® -S are registered trademarks of Siemens AG. DigiTape™ , MUSAC ™ -A, FALC™ 54, IWE™ , SARE™ , UTPT™ , ASM™ , ASP™ are trademarks of Siemens AG.

Semiconductor Group 8 10.97 General Functional Units Memory Management - General Memory Management - Commands

Semiconductor Group 9 10.97 Miscellaneous Interfaces Table 70: SSDI vs. IOM

Semiconductor Group 10 10.97

Electrical Characteristics

Semiconductor Group 11 10.97 PSB 4860 Overview 1O v e r v i e w GeneralGeneral Combined with an analog front end the PSB 4860 provides a solution for embedded or stand alone answering machine applications. Together with a standard microcontroller for analog telephones these two chips form the core of a featurephone with full duplex speakerphone and answering machine capabilities. The chip features recording by DigiTape ™ , a family of high performance algorithms. Messages recorded with DigiTape™ can be played back with variable speed without pitch alteration. Messages recorded with a higher bitrate can be converted into messages with a lower bitrate arbitrarily. Current members of DigiTape (TM) span the range from 3.3 kbit/s to 10.3 kbit/s. Furthermore the PSB 4860, V2.1 has a full duplex speakerphone, a caller ID decoder, DTMF recognition and generation and call progress tone detection. The frequency response of cheap microphones or loudspeakers can be corrected by a programmable equalizer. Messages and user data can be stored in ARAM/DRAM or flash memory which can be directly connected to the PSB 4860. The PSB 4860 also supports a voice prompt EPROM for fixed announcements. The PSB 4860 provides an IOM ® -2 compatible interface with two channels for speech data. Alternatively to the IOM® -2 compatible interface the PSB 4860 supports a simple serial data interface (SSDI) with separate strobe signals for each direction (linear PCM data, one channel). A separate interface is used for a glueless connection to the PSB 4851. The chip is programmed by a simple four wire serial control interface and can inform the microcontroller of new events by an interrupt signal. For data retention the PSB 4860 supports a power down mode where only the real time clock and the memory refresh (in case of ARAM/DRAM) are operational. The PSB 4860 supports interface pins to +5 V levels.

Semiconductor Group 12 10.97 Digital Answering Machine with Full Duplex Speakerphone SAM EC PSB 4860 Version 2.1 CMOS Type Package PSB 4860 P-MQFP-80

1.1 Features

• High performance recording by DigiTape™
• Selectable compression rate (3.3 kbit/s, 10.3 kbit/s)
• Variable playback speed
• Support for ARAM or Flash Memory
• Optional voice prompt EPROM
• Full duplex speakerphone
• DTMF generation and detection
• Call progress tone detection
• Caller ID recognition
• Direct memory access
• Real time clock
• Equalizer
• Automatic gain control
• Automatic timestamp
• Auxiliary parallel port
• Ultra low power refresh mode General Features
• SSDI/IOM ® -2 compatible interface
• Serial control interface for programming

Semiconductor Group 13 10.97

1.2 Pin Configuration

(top view) Figure 1 Pin Configuration of PSB 4860 11 0 2 0 4160 50 VDDA XTAL 1 XTAL 2 OSC 1 OSC 2 VSSA SCLK SDR VDD AFEDD AFEDU VDD VSS VDD VSS AFEFS AFECLK FSC DU/DX DD/DR DXST DRST VDD VSS DCL W /FWE FRDY VPRD /FCLE RAS /FOE CAS 1/FCS SPS 0 SPS 1 VDD VSS MD 1 MD 2 MA 3 MA 2 MA 1 MA 0 MD 7 MD 6 MD 5 MD 4 MD 3 VDD VSS VDD VSS VSS VSS RO VDD MA 4 MA 5 MA 6 VDD MA 8 VSS MA 15 VSS MA 7 MA 9 MA 10 VDD MA 12 MA 13 MA 14 VSS MA 11 VDDP RST CLK VSS MD 0 V DDP INT SDX CS CAS 0/ALE SAM EC PSB 4860

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1.3 Pin Definitions and Functions

Table 1 Pin Definitions and Functions Pin No. P-MQFP-80 Symbol Dir. Reset Function 41, 80 VDDP -- Power supply (5V %) Power supply for the interface. 7, 15, 21, 29, 39, 49, 58, 61, 67, VDD -- Power supply (3.0 V - 3.6 V) Power supply for logic. 1 VDDA -- Power supply (3.0 V - 3.6 V) Power supply for clock generator.

4 VSSA -- Power supply (0 V)

Ground for clock generator. 9, 16, 22, 30, 40, 48, 57, 59, 60, 78, 66, 72 VSS -- Power supply (0 V) Ground for logic and interface.

17 AFEFS O L Analog Frontend Frame Sync:

8 kHz frame synchronization signal for the analog front end.

18 AFECLK O L Analog Frontend Clock:

Clock signal for the analog front end.

19 AFEDD O L Analog Frontend Data Downstream:

Data output to the analog frontend.

20 AFEDU I - Analog Frontend Data Upstream:

Data input from the analog frontend.

79 RST I - Reset:

Active high reset signal.

23 FSC I - Data Frame Synchronization:

8 kHz frame synchronization signal (IOM® -2 and SSDI mode).

24 DCL I - Data Clock:

Data Clock of the serial data interface. 10±

Semiconductor Group 15 10.97

26 DD/DR I/OD

I - IOM ® -2 Compatible Mode: Receive data from IOM® -2 controlling device. SSDI Mode: Receive data of the strobed serial data interface.

25 DU/DX I/OD

• IOM ® -2 Compatible Mode: Transmit data to IOM® -2 controlling device. SSDI Mode: Transmit data of the strobed serial data interface.

27 DXST O L DX Strobe:

Strobe for DX in SSDI interface mode.

28 DRST I - DR Strobe:

Strobe for DR in SSDI interface mode.

14 CS I- Chip Select:

Select signal of the serial control interface (SCI).

11 SCLK I - Serial Clock:

Clock signal of the serial control interface (SCI).

13 SDR I - Serial Data Receive:

Data input of the serial control interface (SCI).

12 SDX O/

H Serial Data Transmit: Data Output of the serial control interface (SCI).

10 INT O/

New status available. Table 1 Pin Definitions and Functions

Semiconductor Group 16 10.97 MA MA 1 MA 2 MA 3 MA 4 MA 5 MA 6 MA 7 MA 8 MA 9 MA 10 MA 11 MA 12 MA 13 MA 14 MA 15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O L1) L L L L L L L L L L L L L L L Memory Address 0-15: Multiplexed address outputs for ARAM, DRAM access. Non-multiplexed address outputs for voice prompt EPROM. Auxiliary Parallel Port: General purpose I/O. MD MD 1 MD 2 MD 3 MD 4 MD 5 MD 6 MD 7 I/O I/O I/O I/O I/O I/O I/O I/O Memory Data 0-7: Memory (ARAM, DRAM, Flash Memory, EPROM) data bus. CAS ALE CAS 1/ FCS O O H 2) ARAM, DRAM: Column address strobe for memory bank 0 or 1. Flash Memory: Address Latch Enable for address lines A16-A23. Chip select signal for Flash Memory

34 RAS /

OH 2) ARAM, DRAM: Row address strobe for both memory banks. Flash Memory: Output enable signal for Flash Memory.

33 VPRD

OH 2) ARAM, DRAM: Read signal for voice prompt EPROM. Flash Memory: Command latch enable for Flash Memory. Table 1 Pin Definitions and Functions

Semiconductor Group 17 10.97 1) These lines are driven low with 125 µA until the mode (address lines or auxiliary port) is defined. 2) These lines are driven high with 70µA during reset.

32 W /FWE OH 2) ARAM, DRAM:

Write signal for all memory banks. Flash Memory: Write signal for Flash Memory.

31 FRDY I - Flash Memory Ready

Input for Ready/Busy signal of Flash Memory OSC OSC 2 I O Z Auxiliary Oscillator: Oscillator loop for 32.768 kHz crystal. 8C L K I - Alternative AFECLK Source 13,824 MHz XTAL 1 XTAL 2 I O Z Oscillator: XTAL 1: External clock or input of oscillator loop. XTAL 2: output of oscillator loop for crystal. SPS 0 SPS 1 O O L L Multipurpose Outputs: General purpose, speakerphone, address lines or status

56 RO O - Reserved Output

Must be left open. Table 1 Pin Definitions and Functions

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1.4 Logic Symbol

Figure 2 Logic Symbol of PSB 4860 DU/DX DD/DR DCL FSC SDX SDR SCLK CS IOM ® -2 SCI AFECLK AFEFS AFEDU AFEDD PSB MA 0-MA 15 MD 0-MD 7 CAS 0/ ALE CAS 1/ FCS FOE RAS / VPRD/ FCLE W / FWE Memory VDDA VDD VSS OSC 2OSC 1 XTAL 1 XTAL 2RST SSDI4851 INT FRDY DXST DRST CLK PSB 4860

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1.5 Functional Block Diagram

Figure 3 Block Diagram of PSB 4860

1.6 System Integration

The PSB 4860 combined with an analog front end (PSB 4851) can be used in a variety of applications. This combination offers outstanding features like full duplex speakerphone and emergency operation. Some applications are given in the following sections.

1.6.1 Analog Featurephone with Digital Answering Machine

Figure 4 shows an example of an analog telephone system. The telephone can operate during power failure by line powering. In this case only the handset and ringer circuit are active. All other parts of the chipset are shut down leaving enough power for the external microcontroller to perform basic tasks like keyboard monitoring. DU/DX DD/DR DCL FSC SDX SDR SCLK CS AFECLK AFEFS AFEDU AFEDD MA 0-MA 15 MD 0-MD 7 CAS 0/ ALE CAS 1/ FCS FOE RAS /V P R D / FCLE W / FWE OSC 2OSC 1 XTAL 1 XTAL 2RST DSP Memory Interface Reset and Timing Unit Data Interface Control Interface Analog Front End Interface INT FRDY DXST DRST

Semiconductor Group 20 10.97 For answering machine operation the voice data is stored in ARAM or Flash Memory devices. In addition, voice prompts can be played back from an optional voice prompt EPROM. If flash memory is used the functionality of the voice prompt EPROM can be realized by the flash memory devices. The microcontroller can use the memory attached to the PSB 4860/PSB 4851 to store and retrieve binary data. Figure 4 Analog Full Duplex Speakerphone with Digital Answering Machine Voice Prompt ARAM Flash Memory EPROM Microcontroller 077-3445 line tip/ ring PSB 4860 PSB 4851

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1.6.2 Featurephone with Digital Answering Machine for ISDN Terminal

Figure 5 shows an ISDN featurephone that takes full advantage of two simultaneous connections. In this application one channel of the PSB 4851 interfaces to the handset and speakerphone while the other provides an interface for an external analog device (e.g. FAX machine). Figure 5 Featurephone with Answering Machine for ISDN Terminal In addition, the two channels of the PSB 4851 can be used for holding two connections simultaneously. One connection can be switched to the handset and the other to the speakerphone box. Local three party conferences are also possible. Flash Memory PSB 4860 PSB 4851 Microcontroller 077-3445 IOM ® -2 SCI PSB 2186 ISAC ® -S TE S0-BUS Power Controller PSB 2120/1 SLIC POTS

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1.6.3 DECT Basestation with Integrated Digital Answering Machine

Figure 6 shows a DECT basestation based on the PSB 4860/PSB 4851 chipset. In this application it is possible to service both an external call and an internal call at the same time. For programming the serial control interface (SCI) is used while voice data is transferred via the strobed serial data interface (SSDI/IOM ® -2). Figure 6 DECT Basestation Flash Memory Microcontroller 077-3445 AntennaSSDI/IOM® -2 SCI Burstmode Controller DECT HF line tip/ ring PSB 4860 PSB 4851

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2 Functional Description

Functional UnitsFunctional Units The PSB 4860 contains several functional units that can be combined with almost no restrictions to perform a given task. Figure 7 gives an overview of the important functional units. Figure 7 Functional Units - Overview DTMF Generator DTMF Detector Speech Coder Speaker- phone CID Decoder Speech Decoder CPT Detector line line micro- loud- SSDI/IOM® -2 IOM ® -2 S5 S7 S11 S12S10 S13 S8S6 signal summation: signal sources: S1,...,S18 in out speaker phone line side acoustic side Memory SCI I1 I1 Channel 2Channel 1 I3 I4 I1 I2 I1 I2 I3 I1 I2 I3 I1 I2 Alert Tone Detector CNG Detector I1 I1 Universal Attenuator S14 Line Echo Canceller I1 I2 S15 AGC I1 I2 S17 Equalizer S18S16

Semiconductor Group 24 10.97 Each unit has one or more signal inputs (denoted by I). Most units have at least one signal output (denoted by S). Any input I can be connected to any signal output S. In addition to the signals shown in figure 7 there is also the signal S 0 (silence), which is useful at signal summation points. Table 2 lists the available signals within the PSB 4860 according to their reference points. Table 2 Signal Summary Signal Description S0 Silence S1 Analog line input (channel 1 of PSB 4851 interface) S2 Analog line output (channel 1 of PSB 4851 interface) S3 Microphone input (channel 2 of PSB 4851 interface) S4 Loudspeaker/Handset output (channel 2 of PSB 4851 interface) S5 Serial interface input, channel 1 S6 Serial interface output, channel 1 S7 Serial interface input, channel 2 S8 Serial interface output, channel 2 S9 DTMF generator output S10 DTMF generator auxiliary output S11 Speakerphone output (acoustic side) S12 Speakerphone output (line side) S13 Speech decoder output S14 Universal attenuator output S15 Line echo canceller output S16 Automatic gain control output (after gain stage) S17 Automatic gain control output (before gain stage) S18 Equalizer output

Semiconductor Group 25 10.97 The following figures show the connections for two typical states during operation. Units that are not needed are not shown. Inputs that are not needed are connected to S0 which provides silence (denoted by 0). In figure 8 a hands-free phone conversation is currently in progress. The speech coder is used to record the signals of both parties. The alert tone detector is used to detect an alerting tone of an off-hook caller id request while the CID decoder decodes the actual data transmitted in this case. Figure 8 Functional Units - Recording a Phone Conversation Alert Tone Detector Speech coder Speaker- phone CID decoder Line Echo Canceller line line micro- loud- in out speaker phone line side acoustic side Memory SCI AGC

Semiconductor Group 26 10.97 In figure 9 a phone conversation using the speakerphone is in progress. One party is using the base station of a DECT system while the other party is using a mobile handset. At the same time an external call is serviced by the answering machine. In the current state a message (recorded or outgoing) is being played back. In this case the DTMF detector is used to detect signals for remote access while the CPT detector is used to determine the end of the external call. Figure 9 Functional Units - Simultaneous Internal and External Call Speaker- phone Speech decoder line line micro- loud- SSDI/IOM® -2 in out speaker phone line side acoustic side Memory SCI Channel 1 DTMF Detector CPT decoder Line Echo Canceller Equalizer

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2.1 Functional Units

In this section the functional units of the PSB 4860 are described in detail. The functional units can be individually enabled or disabled.

2.1.1 Full Duplex Speakerphone

The speakerphone unit (figure 10) is attached to four signals (microphone, loudspeaker, line out and line in). The two input signals (microphone, line in) are preceded by a signal summation point. Figure 10 Speakerphone - Signal Connections Internally, this unit can be divided into an echo cancellation unit and an echo suppression unit (figure 11). The echo cancellation unit provides the attenuation Gc while the echo suppression unit provides the attenuation Gs. The total attenuation ATT of the speakerphone is therefore ATT=GC +G s. Figure 11 Speakerphone - Block Diagram The echo suppression unit can be enabled without the echo cancellation unit. If the echo cancellation unit is disabled, the echo suppression unit still provides speakerphone functionality, albeit only half duplex. As the echo cancellation must be disabled during recording or playback of speech data, this option allows for speakerphone operation Speakerphone S11 S12 a c o u s t i c s i d e l i n e s i d e microphone loudspeaker line out line in Echo Cancellation line outmicrophone loudspeaker line in Echo Suppression G c G S

Semiconductor Group 28 10.97 even if recording or playback is going on. The echo suppression unit is also used to provide additional attenuation if the echo cancellation unit cannot provide all of the required attenuation itself.

2.1.2 Echo Cancellation

A simplified block diagram of the echo cancellation unit is shown in figure 12. Figure 12 Echo Cancellation Unit - Block Diagram The echo cancellation unit consists of an finite impulse response filter (FIR) that models the expected acoustic echo, an NLMS based adaption unit and a control unit. The expected echo is subtracted from the actual input signal from the microphone. If the model is exact and the echo does not exceed the length of the filter then the echo can be completely cancelled. However, even if this ideal state can be achieved for one given moment the acoustic echo usually changes over time. Therefore the NLMS unit continuously adapts the coefficients of the FIR filter. This adaption process is steered by the control unit. As an example, the adaption is inhibited as long as double talk is detected by the control unit. Furthermore the control unit informs the echo suppression unit about the achieved echo return loss. Table 3 shows the registers associated with the echo cancellation unit. Table 3 Echo Cancellation Unit Registers Register # of Bits Name Comment SAELEN 9 LEN Length of FIR filter SAEATT 15 ATT Attenuation reduction during double-talk SAEGS 3 GS Global scale (all blocks) microphone loudspeaker FIR FilterNLMSControl line out line in

Semiconductor Group 29 10.97 The length of the FIR filter can be varied from 127 to 511 taps (15.875ms to 63.875ms). The taps are grouped into blocks. Each block contains 64 taps. The performance of the FIR filter can be enhanced by prescaling some or call of the coefficients of the FIR filter. A coefficient is prescaled by multiplying it by a constant. The advantage of prescaling is an enhanced precision and consequently an enhanced echo cancellation. The disadvantage is a reduced echo cancellation performance if the signal exceeds the maximal coefficient value. More precisely, if a coefficient at tap T i is scaled by a factor Ci then the level of the echo (room impulse response) must not exceed Max/ C i (Max: Maximum PCM value). As an example figure shows a typical room impulse response. Figure 13 Echo Cancellation Unit - Typical Room Impulse Response First of all, the echo never exceeds 0.5 of the maximum value. Furthermore the echo never exceeds 0.25 of the maximum value after time t0.25. Therefore all coefficients can be scaled by a factor of 2 and all coefficients for taps corresponding to times after t0.25 can be scaled a factor of 4. The echo cancellation unit provides three parameters for scaling coefficients. The first parameter (GS) determines a scale for all coefficients. The second parameter (FB) determines the first block for which an additional scale (PS) takes effect. This feature can be used for different default settings like large or small rooms. SAEPS1 3 AS Partial scale (for blocks >= SAEPS2:FB) SAEPS2 3 FB First block affected by partial scale Table 3 Echo Cancellation Unit Registers t A 0.5 0.25 t0.25

Semiconductor Group 30 10.97

2.1.3 Echo Suppression

The echo suppression unit can be in one of three states:

• transmit state
• receive state
• idle state In transmit state the microphone signal drives the line output while the line input is attenuated. In receive state the loudspeaker signal is driven by the line input while the microphone signal is attenuated. In idle state both signal paths are active with evenly distributed attenuation. Figure 14 Echo Suppression Unit - States of Operation line out line in microphone loudspeaker idle state line out line in microphone loudspeaker receive state line out line in microphone loudspeaker transmit state

Semiconductor Group 31 10.97 Figure15 shows the signal flow graph of the echo suppression unit in more detail. Figure 15 Echo Suppression Unit - Signal Flow Graph State switching is controlled by the speech comparators (SCAS, SCLS) and the speech detectors (SDX, SDR). The amplifiers (AGCX, AGCR, LGAX, LGAR) are used to achieve proper signal levels for each state. All blocks are programmable. Thus the telephone set can be optimized and adjusted to the particular geometrical and acoustical environment. The following sections discuss each block of the echo suppression unit in detail. SCLSSCAS SDX SDR AGCR AGCX Attenuation Control line outmicrophone loudspeaker LGAX LGAR line in GHX GHR

Semiconductor Group 32 10.97

2.1.3.1 Speech Detector

For each signal source a speech detector (SDX, SDR) is available. The speech detectors are identical but can be programmed individually. Figure 16 shows the signal flow graph of a speech detector. Figure 16 Speech Detector - Signal Flow Graph The first three units (LIM, LP1, PD) are used for preprocessing the signal while the actual speech detection is performed by the background noise monitor. Background Noise Monitor The tasks of the noise monitor are to differentiate voice signals from background noise, even if it exceeds the voice level, and to recognize voice signals without any delay. Therefore the Background Noise Monitor consists of the Low-Pass Filter 2 (LP2) and the offset in two separate branches. Basically it works on the burst-characteristic of the speech: voice signals consist of short peaks with high power (bursts). In contrast, background noise can be regarded approximately stationary from its average power. Low-Pass Filter 2 provides different time constants for noise (non-detected speech) and speech. It determines the average of the noise reference level. In case of background noise the level at the output of LP2 is approximately the level of the input. As in the other branch an additional offset OFF is added to the signal, the comparator signals noise. At speech bursts the digital signals arriving at the comparator via the offset branch change faster than those via the LP2-branch. If the difference exceeds the offset OFF, the LIM LP1 PD LP2 OFF LP1 PDS PDN LP2S LP2N LP2L Background Noise Monitor Signal Preprocessing LIM

Semiconductor Group 33 10.97 comparator signals speech. Therefore the output of the background noise monitor is a digital signal indicating speech (1) or noise (0). A small fade constant (LP2N) enables fast settling of LP2 to the average noise level after the end of speech recognition. However, a too small time constant for LP2N can cause rapid charging to such a high level that after recognizing speech the danger of an unwanted switching back to noise exists. It is recommended to choose a large rising constant (LP2S) so that speech itself charges the LP2 very slowly. Generally, it is not recommended to choose an infinite LP2S because then approaching the noise level is disabled. During continuous speech or tones the LP2 will be charged until the limitation LP2L is reached. Then the value of LP2 is frozen until a break discharges the LP2. This limitation permits transmission of continuous tones and “music on hold”. The offset stage represents the estimated difference between the speech signal and averaged noise. Signal Preprocessing As described in the preceding chapter, the background noise monitor is able to discriminate between speech and noise. In very short speech pauses e.g. between two words, however, it changes immediately to non-speech, which is equal to noise. Therefore a peak detection is required in front of the Noise Monitor. The main task of the Peak Detector (PD) is to bridge the very short speech pauses during a monolog so that this time constant has to be long. Furthermore, the speech bursts are stored so that a sure speech detection is guaranteed. But if no speech is recognized the noise low-pass LP2 must be charged faster to the average noise level. In addition, the noise edges are to be smoothed. Therefore two time constants are necessary. As the peak detector is very sensitive to spikes, the low-pass LP1 filters the incoming signal containing noise in a way that main spikes are eliminated. Due to the programmable time constant it is possible to refuse high-energy sibilants and noise edges. To compress the speech signals in their amplitudes and to ease the detection of speech, the signals have to be companded logarithmically. Hereby, the speech detector should not be influenced by the system noise which is always present but should discriminate between speech and background noise. The limitation of the logarithmic amplifier can be programmed via the parameter LIM. LIM is related to the maximum PCM level. A signal exceeding the limitation defined by LIM is getting amplified logarithmically, while very smooth system noise below is neglected. It should be the level of the minimum system noise which is always existing; in the transmit path the noise generated by the telephone circuitry itself and in receive direction the level of the first bit which is stable without any speech signal at the receive path. Table 6 shows the parameters for the speech detector.

Semiconductor Group 34 10.97 The input signal of the speech detector can be connected to either the input signal of the echo suppression unit (as shown for SDX) or the output of the associated AGC (as shown for SDR). Table 4 Speech Detector Parameters Parameter # of bytes Range Comment LIM 1 0 to 95 dB Limitation of log. amplifier OFF 1 0 to 95 dB Level offset up to detected noise PDS 1 1 to 2000 ms Peak decrement PD1 (speech) PDN 1 1 to 2000 ms Peak decrement PD1 (noise) LP1 1 1 to 2000 ms Time constant LP1 LP2S 1 2 to 250 s Time constant LP2 (speech) LP2N 1 1 to 2000 ms Time constant LP2 (noise) LP2L 1 0 to 95 dB Maximum value of LP2

Semiconductor Group 35 10.97

2.1.3.2 Speech Comparators (SC)

The echo suppression unit has two identical speech comparators (SCAS, SCLS). Each comparator can be programmed individually to accommodate the different system characteristics of the acoustic interface and the line interface. As SCAS and SCLS are identical, the following description holds for both SCAS and SCLS. The SC has two input signals SX and SR, which map to microphone/loudspeaker for SCAS and line in/line out for SCLS. In principle, the SC works according to the following equation: Therefore, SCAS controls the switching to transmit state and SCLS controls the switching to receive state. Switching is done only if SX exceeds SR by at least the expected acoustic level enhancement V which is divided into two parts: G and GD. A block diagram of the SC is shown in figure 17. Figure 17 Speech Comparator - Block Diagram At both inputs, logarithmic amplifiers compress the signal range. Hence after the required signal processing for controlling the acoustic echo, pure logarithmic levels on both paths are compared. The main task of the comparator is to control the echo. The internal coupling due to the direct sound and mechanical resonances are covered by G. The external coupling, mainly caused by the acoustic feedback, is controlled by GD/PD. if SX > SR + V then switch state G GDS GDN PDS PDN SX SR Log. Amp. Base Gain Gain Reserve Peak Decrement Log. Amp. PDS PDN Peak Decrement

Semiconductor Group 36 10.97 The base gain (G) corresponds to the terminal couplings of the complete telephone: G is the measured or calculated level enhancement between both receive and transmit inputs of the SC. To control the acoustic feedback two parameters are necessary: GD represents the actual reserve on the measured G. Together with the Peak Decrement (PD) it simulates the echo behavior at the acoustic side: After speech has ended there is a short time during which hard couplings through the mechanics and resonances and the direct echo are present. Till the end of that time (Δ t) the level enhancement V must be at least equal to G to prevent clipping caused by these internal couplings. Then, only the acoustic feedback is present. This coupling, however, is reduced by air attenuation. For this in general the longer the delay, the smaller the echo being valid. This echo behavior is featured by the decrement PD. Figure 18 Speech Comparator - Interdependence of Parameters According to figure 18, a compromise between the reserve GD and the decrement PD has to be made: a smaller reserve (GD) above the level enhancement G requires a longer time to decrease (PD). It is easy to overshout the other side but the intercommunication is harder because after the end of the speech, the level of the estimated echo has to be exceeded. In contrary, with a higher reserve (GD*) it is harder to overshout continuous speech or tones, but it enables a faster intercommunication because of a stronger decrement (PD*). t dB Δt GD* GD PD* PD RX-Speech RX-noise G G

Semiconductor Group 37 10.97 Two pairs of coefficients, GDS/PDS when speech is detected, and GDN/PDN in case of noise, offer a different echo handling for speech and non-speech. With speech, even if very strong resonances are present, the performance will not be worsened by the high GDS needed. Only when speech is detected, a high reserve prevents clipping. A time period ET [ms] after speech end, the parameters of the comparator are switched to the “noise” values. If both sets of the parameters are equal, ET has no function.

2.1.3.3 Attenuation Control

The attenuation control unit controls the attenuation stages GHX and GHR and performs state switching. The programmable attenuation ATT is completely switched to GHX (GHR) in receive state (transmit state). In idle state both GHX and GHR attenuate by ATT/2. In addition, attenuation is also influenced by the automatic gain control stages (AGCX, AGCR). State switching depends on the signals of one speech comparator and the corresponding speech detector. While each state is associated with the programmed attenuation, the time is takes to reach the steady-state attenuation after a state switch can be programmed (T SW ). If the current state is either transmit or receive and no speech on either side has been detected for time TW then idle state is entered. To smoothen the transition, the attenuation is incremented (decremented) by DS until the evenly distribution ATT/2 for both GHX and GHR is reached. Table 6 shows the parameters for the attenuation unit. Note that TSW is dependent on the current attenuation by the formula . Table 5 Speech Comparator Parameters Parameter # of bytes Range Comment G 1 – 48 to + 48 dB Base Gain GDS 1 0 to 48 dB Gain Reserve (Speech) PDS 1 0.025 to 6 dB/ms Peak Decrement (Speech) GDN 1 0 to 48 dB Gain Reserve (Noise) PDN 1 0.025 to 6 dB/ms Peak Decrement (Noise) ET 1 0 to 992 ms Time to Switch from speech to noise parameters T sw SW ATT×=

Semiconductor Group 38 10.97 Note: In addition, attenuation is also influenced by the Automatic Gain Control stages (AGCX, AGCR) in order to keep the total loop attenuation constant.

2.1.3.4 Echo Suppression Status Output

The PSB 4860 can report the current state of the echo suppression unit to ease optimization of the parameter set of the echo suppression unit. In this case the SPS0 and SPS 1 pins are set according to table 7. Furthermore the controller can read the current value of the SPS pins by reading register SPSCTL.

2.1.3.5 Loudhearing

The speakerphone unit can also be used for controlled loudhearing. If enabled in loudhearing mode, the loudspeaker amplifier of the PSB 4851 (ALS) is used instead of GHR (figure 15) when appropriate to avoid oscillation. In order to enable this feature, the PSB 4851 must be programmed to allow ALS override. The ALS field within the AFE control register AFECTL defines the value sent to the PSB 4851 if attenuation is necessary (see specification of the PSB 4851).

2.1.3.6 Automatic Gain Control

The echo suppression unit has two identical automatic gain control units (AGCX, AGCR). Table 6 Attenuation Control Unit Parameters Parameter # of bytes Range Comment TW 1 16 ms to 4 s T W to return to idle state ATT 1 0 to 95 dB Attenuation for GHX and GHR DS 1 0.6 to 680 ms/dB Decay Speed (to idle state) SW 1 0.0052 to 10 ms/dB Decay Rate (used for T SW ) Table 7 SPS Output Encoding SPS 0 SPS 1 Echo Suppression Unit State 0 0 no echo suppression operation 0 1 receive 10 t r a n s m i t 1 1 idle

Semiconductor Group 39 10.97 Operation of the AGC depends on a threshold level defined by the parameter COM (value relative to the maximum PCM-value). The regulation speed is controlled by SPEEDH for signal amplitudes above the threshold and SPEEDL for amplitudes below. Usually SPEEDH will be chosen to be at least 10 times faster than SPEEDL. The bold line in Figure 19 depicts the steady-state output level of the AGC as a function of the input level. Figure 19 Echo Suppression Unit - Automatic Gain Control For reasons of physiological acceptance the AGC gain is automatically reduced in case of continuous background noise (e.g. by ventilators). The reduction is programmed via the NOlS parameter. When the noise level exceeds the threshold determined by NOIS, the amplification will be reduced by the same amount the noise level is above the threshold. The current gain/attenuation of the AGC can be read at any time (AG_CUR). An additional low pass with time constant LP is provided to avoid an immediate response of the AGC to very short signal bursts. If SDX detects noise, AGCX is not working. In this case the last gain setting is used. Regulation starts with this value as soon as SDX detects speech. Likewise, if SDR detects noise, AGCR is not working. In this case the last gain setting is used. Regulation starts with this value as soon as SDR detects speech. When the AGC has been disabled the initial gain used immediately after enabling the AGC can be programmed. Table 8 shows the parameters of the AGC. COM AG_ATT AG_GAIN AGC input level AGC output level max. PCM -10 dB -20 dB -10 dB-20 dB Example: COM AG_GAIN AG_ATT -30 dB 15 dB 20 dB

Semiconductor Group 40 10.97 Note: There are two sets of parameters, one for AGCX and one for AGCR. Note: By setting AG_GAIN to 0 dB a limitation function can be realized with the AGC.

2.1.3.7 Fixed Gain

Each signal path features an additional amplifier (LGAX, LGAR) that can be set to a fixed gain. These amplifiers should be used for the basic amplification in order to avoid saturation in the preceding stages. Table 9 shows the only parameter of this stage.

2.1.3.8 Mode Control

Table 10 shows the registers used to determine the signal sources and the mode. Table 8 Automatic Gain Control Parameters Parameter # of Bytes Range Comment AG_INIT 1 -95 dB to 95dB Initial AGC gain/attenuation COM 1 0 to – 95 dB Compare level rel. to max. PCM-value AG_ATT 1 0 to -95 dB Attenuation range AG_GAIN 1 0 to 95 dB Gain range AG_CUR 1 -95 dB to 95 dB Current gain/attenuation SPEEDL 1 0.25 to 62.5 dB/s Change rate for lower levels SPEEDH 1 0.25 to 62.5 dB/s Change rate for higher levels NOIS 1 0 to – 95 dB Threshold for AGC-reduction by background noise LP 1 0.025 to 16 ms AGC low pass time constant Table 9 Fixed Gain Parameters Parameter # of Bytes Range Comment LGA 1 -12 dB to 12 dB always active Table 10 Speakerphone Control Registers Register # of Bits Name Comment SCTL 1 ENS Echo suppression unit enable SCTL 1 ENC Echo cancellation unit enable SCTL 1 MD Speakerphone or loudhearing mode SCTL 1 AGX AGCX enable

Semiconductor Group 41 10.97 SCTL 1 AGR AGCR enable SCTL 1 SDX SDX input tap SCTL 1 SDR SDR input tap AFECTL 4 ALS ALS value for loudhearing SSRC1 5 I1 Input signal 1 (microphone) SSRC1 5 I2 Input signal 2 (microphone) SSRC2 5 I3 Input signal 3 (line in) SSRC2 5 I4 Input signal 4 (line in) Table 10 Speakerphone Control Registers

Semiconductor Group 42 10.97

2.1.4 Line Echo Canceller

The PSB 4860 contains an adaptive line echo cancellation unit for the cancellation of near end echoes. The unit has two modes: normal and extended. In normal mode, the maximum echo length is 4 ms. This mode is always available. In extended mode, the maximum echo length is 24 ms. Extended mode cannot be used while the speech encoder, the echo cancellation unit or slow playback is active. The line echo cancellation unit is especially useful in front of the various detectors (DTMF, CPT, etc.). A block diagram is shown in figure 20. Figure 20 Line Echo Cancellation Unit - Block Diagram The line echo canceller provides only one outgoing signal (S 15) as the other outgoing signal would be identical with the input signal I1. Input I2 is usually connected to the line input while input I1 is connected to the outgoing signal. In normal mode the adaption process can be controlled by three parameters: MIN, ATT and MGN. Adaption takes only place if both of the following conditions hold: With the first condition adaption to small signals can be avoided. The second condition avoids adaption during double talk. The parameter ATT represents the echo loss provided by external circuitry. The adaption stops if the power of the received signal (I2) exceeds the power of the expected signal (I1-ATT) by more than the margin MGN. Σ Adaptive Filter I2 S15 I1 MIN> I1 I2–A T T M G N+–0 >

Semiconductor Group 43 10.97 Table 11 shows the registers associated with the line echo canceller. Table 11 Line Echo Cancellation Unit Registers Register # of Bits Name Comment Relevant Mode LECCTL 1 EN Line echo canceller enable both LECCTL 1 MD Line echo canceller mode LECCTL 5 I2 Input signal selection for I 2 both LECCTL 5 I1 Input signal selection for I 1 both LECLEV 15 MIN Minimal power for signal I 1 normal LECATT 15 ATT Externally provided attenuation (I 1 to I2) normal LECMGN 15 MGN Margin for double talk detection normal

Semiconductor Group 44 10.97

2.1.5 DTMF Detector

Figure 21 shows a block diagram of the DTMF detector. The results of the detector are available in the status register and a dedicated result register that can be read via the serial control interface (SCI) by the external controller. All sixteen standard DTMF tones are recognized. Figure 21 DTMF Detector - Block Diagram Table 12 to 14 show the associated registers. As soon as a valid DTMF tone is recognized, the status word and the DTMF tone code are updated (table 13). DTV is set when a DTMF tone is recognized and reset when no DTMF tone is recognized or the detector is disabled. The code for the DTMF tone is placed into the register DDCTL. The registers DDTW and DDLEV hold parameters for detection (table 14). Table 12 DTMF Detector Control Register Register # of Bits Name Comment DDCTL 1 EN DTMF detector enable DDCTL 5 I1 Input signal selection Table 13 DTMF Detector Results Register # of Bits Name Comment STATUS 1 DTV DTMF code valid DDCTL 5 DTC DTMF tone code Table 14 DTMF Detector Parameters Register # of Bits Name Comment DDTW 15 TWIST Twist for DTMF recognition DDLEV 6 MIN Minimum signal level to detect DTMF tones DTMF SCII1 Recognition

Semiconductor Group 45 10.97

2.1.6 CNG Detector

The calling tone (CNG) detector can detect the standard calling tones of fax machines or modems. This helps to distinguish voice messages from data transfers. The result of the detector is available in the status register that can be read via the serial control interface (SCI) by the external controller. The CNG detector consists of two band-pass filters with fixed center frequency of 1100 Hz and 1300 Hz. Figure 22 CNG Detector - Block Diagram Table 15 shows the available parameters. Both the programmed minimum time and the minimum signal level must be exceeded for a valid CNG tone. Furthermore the input signal resolution can be reduced by the RES parameter. This can be useful in a noisy environment at low signal levels although the accuracy of the detection decreases. As soon as a valid tone is recognized, the status word of the PSB 4860 is updated. The status bits are defined as follows: Table 15 CNG Detector Registers Register # of Bits Name Comment CNGCTL 1 EN CNG detector enable CNGCTL 5 I1 Input signal selection CNGLEV 16 MIN Minimum signal level CNGBT 16 TIME Minimum time of signal burst CNGRES 16 RES Input signal resolution Table 16 CNG Detector Result Register # of Bits Name Comment STATUS 1 CNG Fax/Modem calling tone detected CNG Detector SCII1

1100 Hz 1300 Hz

Semiconductor Group 46 10.97

2.1.7 Alert Tone Detector

The alert tone detector can detect the standard alert tones (2130 Hz and 2750 Hz) for caller id protocols. The results of the detector are available in the status register and the dedicated register ATDCTL0 that can be read via the serial control interface (SCI) by the external controller. Figure 23 Alert Tone Detector - Block Diagram As soon as a valid alert tone is recognized, the status word of the PSB 4860 and the code for the detected combination of alert tones are updated (table 18). Table 17 Alert Tone Detector Registers Register # of Bits Name Comment ATDCTL0 1 EN Alert Tone Detector Enable ATDCTL0 5 I1 Input signal selection ATDCTL1 1 MD Detection of dual tones or single tones ATDCTL1 1 DEV Maximum deviation (0.5% or 1.1%) ATDCTL1 8 MIN Minimum signal level to detect alert tones Table 18 Alert Tone Detector Results Register # of Bits Name Comment STATUS 1 ATV Alert tone detected ATDCTL0 2 ATC Alert tone code Alert Tone SCII1 Detector

Semiconductor Group 47 10.97

2.1.8 CPT Detector

The selected signal is monitored continuously for a call progress tone. The CPT detector consists of a band-pass and an optional timing checker (figure 24). Figure 24 CPT Detector - Block Diagram The CPT detector can be used in two modes: raw and cooked. In raw mode, the occurrence of a signal within the frequency range, time and energy limits is directly reported. The timing checker is bypassed and therefore the PSB 4860 does not interpret the length or interval of the signal. In cooked mode, the number and duration of signal bursts are interpreted by the timing checker. A signal burst followed by a gap is called a cycle. Cooked mode requires a minimum of two cycles. The CPT flag is set with the first burst after the programmed number of cycles has been detected. The CPT flag remains set until the unit is disabled, even if the conditions are not met anymore. In this mode the CPT is modelled as a sequence of identical bursts separated by gaps with identical length. The PSB 4860 can be programmed to accept a range for both the burst and the gap. It is also possible to specify a maximum aberration of two consecutive bursts and gaps. Figure 25 shows the parameters for a single cycle (burst and gap). Figure 25 CPT Detector - Cooked Mode The status bit is defined as follows: Timing Band-pass SCI (Status)I1 300-640 Hz Checker tBmax tBmin tGmin tGmax

Semiconductor Group 48 10.97 CPT is not affected by reading the status word. It is automatically reset when the unit is disabled. Table 20 shows the control register for the CPT detector. If any condition is violated during a sequence of cycles the timing checker is reset and restarts with the next valid burst. Note: In cooked mode CPT is set with the first burst after the programmed number of cycles has been detected. Note: The number of cycles must be set to zero in raw mode. Table 19 CPT Detector Result Register # of Bits Name Comment STATUS 1 CPT CP tone currently detected [340 Hz; 640 Hz] Table 20 CPT Detector Registers Register # of Bits Name Comment CPTCTL 1 EN Unit enable CPTCTL 1 MD Mode (cooked, raw) CPTCTL 5 I1 Input signal selection CPTMN 8 MINB Minimum time of a signal burst (t Bmin) CPTMN 8 MING Minimum time of a signal gap (t Gmin ) CPTMX 8 MAXB Maximum time of a signal burst (t Bmax ) CPTMX 8 MAXG Maximum time of a signal gap (t Gmax ) CPTDT 8 DIFB Maximum difference between consecutive bursts CPTDT 8 DIFG Maximum difference between consecutive gaps CPTTR 3 NUM Number of cycles (cooked mode), 0 (raw mode) CPTTR 8 MIN Minimum signal level to detect tones CPTTR 4 SN Minimal signal-to-noise ratio

Semiconductor Group 49 10.97

2.1.9 Caller ID Decoder

The caller ID decoder is basically a 1200 baud modem (FSK, demodulation only). The bit stream is formatted by a subsequent UART and the data is available in a data register along with status information (figure 26). Figure 26 Caller ID Decoder - Block Diagram The FSK demodulator supports two modes according to table 21. The appropriate mode is detected automatically. The CID decoder does not interpret the data received. Each byte received is placed into the CIDCTL register (table 23). The status byte of the PSB 4860 is updated (table 22). CIA and CD are cleared when the unit is disabled. In addition, CIA is cleared when CIDCTL0 is read. Table 21 Caller ID Decoder Modes Mode Mark (Hz) Space (Hz) Comment 1 1200 2200 Bellcore 2 1300 2100 V.23 Table 22 Caller ID Decoder Status Register # of Bits Name Comment STATUS 1 CIA CID byte received STATUS 1 CD Carrier Detected Table 23 Caller ID Decoder Registers Register # of Bits Name Comment CIDCTL0 1 EN Unit enable CIDCTL0 5 I1 Input signal selection CIDCTL0 8 DATA Last CID data byte received UARTFSK demod. SCI (Status, Data)I1 (Bellcore, V.23)

Semiconductor Group 50 10.97 When the CID unit is enabled, it first waits for a channel seizure signal consisting of a series of alternating space and mark signals. The number of spaces and marks that have to be received without errors before the PSB 4860 reports a carrier detect by setting status bit CD can be programmed. Channel seizure must be followed by at least 16 continuous mark signals. The first space signal detected is then regarded as the start bit of the first message byte. The interpretation of the data, including message type, length and checksum is completely left to the controller. The CID unit should be disabled as soon as the complete information has been received as it cannot detect the end of the transmission by itself. Note: Some caller ID mechanism may require additional external components for DC decoupling. These tasks must be handled by the controller. Note: The controller is responsible for selecting and storing parts of the CID as needed. CIDCTL1 5 NMSS Number of mark/space sequences necessary for successful detection of carrier detect CIDCTL1 6 NMB Number of mark bits necessary before space of first byte after carrier detect CIDCTL1 5 MIN Minimum signal level for CID detection Table 23 Caller ID Decoder Registers Register # of Bits Name Comment

Semiconductor Group 51 10.97

2.1.10 DTMF Generator

The DTMF generator can generate single or dual tones with programmable frequency and gain. This unit is primarily used to generate the common DTMF tones but can also be used for signalling or other user defined tones. A block diagram is shown in figure 27. Figure 27 DTMF Generator - Block Diagram Both generators and amplifiers are identical. There are two modes for programming the generators, cooked mode and raw mode. In cooked mode, the standard DTMF frequencies are generated by programming a single 4 bit code. In raw mode, the frequency of each generator/amplifier can be programmed individually by a separate register. The unit has two outputs which provide the same signal but with individually programmable attenuation. Table 24 shows the parameters of this unit. Note: DGF1 and DGF2 are undefined when cooked mode is used and must not be written. Table 24 DTMF Generator Registers Register # of Bits Name Comment DGCTL 1 EN Enable for generators DGCTL 1 MD Mode (cooked/raw) DGCTL 4 DTC DTMF code (cooked mode) DGF1 15 FRQ1 Frequency of generator 1 DGF2 15 FRQ2 Frequency of generator 2 DGL 7 LEV1 Level of signal for generator 1 DGL 7 LEV2 Level of signal for generator 2 DGATT 8 ATT1 Attenuation of S DGATT 8 ATT2 Attenuation of S 10 generator generator gain1 gain2 att2 S10 att1

Semiconductor Group 52 10.97

2.1.11 Speech Coder

The speech coder (figure 28) has two input signals I1 and I2. The first signal (I1) is fed to the coder while the second signal (I2) is used as a reference signal for voice controlled recording. The signal I 1 can be coded by either a High Quality coder or a Long Play coder. Figure 28 Speech Coder - Block Diagram In High Quality the output data stream runs at a fixed rate of 10300 bit/s and provides excellent speech quality. In Long Play mode, the output data stream is further reduced to an average of 3300 bit/s while still maintaining good quality. Data is written starting at the current file pointer and the file pointer is advanced as needed. In case of any memory error (e.g. memory full) a file error is indicated and the coder is disabled. The controller must subsequently close the file. The coder can be switched on the fly. However, it may take up to 60 ms until the switch is executed. The controller must therefore wait for at least this time until issuing another command that relies on the mode switch. No audio data is lost during switching. The signal I 2 is first filtered by a low pass LP1 with programmable time constant and then compared to a reference level MIN. If the filtered signal exceeds MIN, then the status bit SD (table 25) is set immediately. If the filtered signal has been smaller than MIN for a programmable time TIME then the status bit SD is reset. The coder can be enabled in permanent mode or in voice recognition mode. In permanent mode, the coder starts immediately and compresses all input data continuously. The current state of the status bit SD does not affect the coder. In voice recognition mode, the coder is automatically started on the first transition of the status bit from 0 to 1. Once the coder has started it remains active until disabled. Table 25 Speech Coder Status Register # of Bits Name Comment STATUS 1 SD Speech detected HQ 10300 bit/s LP 3300 bit/s Memory MIN LP

Semiconductor Group 53 10.97 The operation of the speech coder is defined according to table 26. Note: The peak data rate in LP mode is 4800 bit/s. Note: Both HQ and LP mode will not produce identical bit streams after a coding/ decoding cycle. Table 26 Speech Coder Registers Register # of Bits Name Comment SCCTL 1 EN Enable speech coder SCCTL 1 HQ High quality mode SCCTL 1 VC Voice controlled recording SCCTL 5 I1 Input signal 1 selection SCCTL 5 I2 Input signal 2 selection SCCT2 8 MIN Minimal signal level for speech detection SCCT2 8 TIME Minimum time for reset of SD SCCT3 8 LP Time constant for low-pass

Semiconductor Group 54 10.97

2.1.12 Speech Decoder

The speech decoder (figure 29) decompresses the data previously coded by the speech coder unit and delivers a standard 128 kbit/s data stream. Figure 29 Speech Decoder - Block Diagram The decoder supports fast (1.5 and 2.0 times) and slow (0.5 times) motion independent of the selected quality. The decoder requests input data as needed at a variable rate. Table 27 shows the signal and mode selection for the speech decoder. Data reading starts at the location of the current file pointer. The file pointer is updated during speech decoding. If the end of the file is reached, the decoder is automatically disabled. The PSB 4860 automatically resets SDCTL:EN at this point. Table 27 Speech Decoder Registers Register # of Bits Name Comment SDCTL 1 EN Enable speech decoder SDCTL 2 SPEED Selection of playback speed HQ 10300 bit/s LP 3300 bit/s S13Memory

Semiconductor Group 55 10.97

2.1.13 Analog Front End Interface

There are two identical interfaces at the analog side (to PSB 4851) as shown in figure 30. Figure 30 Analog Front End Interface - Block Diagram For each signal an amplifier is provided for level adjustment. The incoming signals can be passed through an optional high-pass (HP). This high-pass (fg=20 Hz) is useful for blocking DC offsets and should be enabled by default. Furthermore, up to three signals can be mixed in order to generate the outgoing signals (S2,S4). Table 28 shows the associated registers. Table 28 Analog Front End Interface Registers Register # of Bits Name Comment IFG1 16 IG1 Gain for IG1 IFG2 16 IG2 Gain for IG2 IFS1 1 HP High-pass for S IFS1 5 I1 Input signal 1 for IG2 IFS1 5 I2 Input signal 2 for IG2 IFS1 5 I3 Input signal 3 for IG2 IFG3 16 IG3 Gain for IG3 IFG4 16 IG4 Gain for IG4 IFS2 1 HP High-pass for S IFS2 5 I1 Input signal 1 for IG4 IFS2 5 I2 Input signal 2 for IG4 IFS2 5 I3 Input signal 3 for IG4 Channel 2 Channel 1 S2 I1 line out line in IG1 IG2 S4 I1 loudspeaker microphone IG4 HP IG3 HP

Semiconductor Group 56 10.97

2.1.14 Digital Interface

There are two almost identical interfaces at the digital side as shown in figure 31. The only difference between these two interfaces is that only channel 1 supports the SSDI mode. Figure 31 Digital Interface - Block Diagram Each outgoing signal can be the sum of two signals with no attenuation and one signal with programmable attenuation (ATT). The attenuator can be used for artificial echo if there is none externally provided (e.g. ISDN application). Each input can be passed through an optional high-pass (HP). The associated registers are shown in table 29. Table 29 Digital Interface Registers Register # of Bits Name Comment IFS3 5 I1 Input signal 1 for S IFS3 5 I2 Input signal 2 for S 6 IFS3 5 I3 Input signal 3 for S 6 IFS3 1 HP High-pass for S 5 IFS4 5 I1 Input signal 1 for S 8 IFS4 5 I2 Input signal 2 for S 8 IFS4 5 I3 Input signal 3 for S 8 IFS4 1 HP High-pass for S 7 Channel 2 (IOM® -2 Interface)Channel 1 (SSDI/IOM® -2 Interface) I3ATT2 HPS5 I3ATT1 HP

Semiconductor Group 57 10.97 IFG5 8 ATT1 Attenuation for input signal I3 (Channel 1) IFG5 8 ATT2 Attenuation for input signal I3 (Channel 2) Table 29 Digital Interface Registers Register # of Bits Name Comment

Semiconductor Group 58 10.97

2.1.15 Universal Attenuator

The PSB 4860 contains an universal attenuator that can be connected to any signal (e.g. for sidetone gain in ISDN applications). Figure 32 Universal Attenuator - Block Diagram Table 30 shows the associated register. Table 30 Universal Attenuator Registers Register # of Bits Name Comment UA 8 ATT Attenuation for UA UA 5 I1 Input signal for UA S14UAI1

Semiconductor Group 59 10.97

2.1.16 Automatic Gain Control Unit

In addition to the universal attenuator with programmable but fixed gain the PSB 4860 contains an amplifier with automatic gain control (AGC). The AGC is preceeded by a signal summation point for two input signals. One of the input signals can be attenuated. Figure 33 Automatic Gain Control Unit - Block Diagram Furthermore the signal after the summation point is available. Besides providing a general signal summation (S 16 not used) this signal is especially useful if the AGC unit provides the input signal for the speech coder. In this case S17 can be used as a reference signal for voice controlled recording. The operation of the AGC is similar to AGCX (ACCR) of the speakerphone. The differences are as follows:

• No NOIS parameter
• Separate enable/disable control
• Slightly different coefficient format Furthermore the AGC contains a comparator that starts and stops the gain regulation. The signal after the summation point (S17) is filtered by a peak detector with time constant DEC for decay. Then the signal is compared to a programmable limit LIM. Regulation takes only place when the filtered signal exceeds the limit. Table 31 shows the associated registers. Table 31 Automatic Gain Control Registers Register # of Bits Name Comment AGCCTL 1 EN Enable AGCCTL 5 I1 Input signal 1 for AGC AGCCTL 5 I2 Input signal 2 for AGC AGCATT 15 ATT Attenuation for I AGC1 8 AG_INIT Initial AGC gain/attenuation AGC1 8 COM Compare level rel. to max. PCM-value S16AGCI1 ATTI2 S17

Semiconductor Group 60 10.97 AGC2 8 SPEEDL Change rate for lower levels AGC2 8 SPEEDH Change rate for higher level AGC3 8 AG_ATT Attenuation range AGC3 7 AG_GAIN Gain range AGC4 7 DEC Peak detector time constant AGC4 8 LIM Comparator minimal signal level AGC5 7 LP AGC low pass time constant Table 31 Automatic Gain Control Registers Register # of Bits Name Comment

Semiconductor Group 61 10.97

2.1.17 Equalizer

The PSB 4860 also provides an equalizer that can be inserted into any signal path. The main application for the equalizer is the adaption to the frequency characteristics of the microphone, transducer or loudspeaker. The equalizer consists of an IIR filter followed by an FIR filter as shown in figure 34. Figure 34 Equalizer - Block Diagram The coefficients A 1-A9, B2-B9 and C1 belong to the IIR filter, the coefficients D1-D 17 and C 2 belong to the FIR filter. Table 32 shows the registers associated with the equalizer. Table 32 Equalizer Registers Register # of Bits Name Comment FCFCTL 1 EN Enable FCFCTL 5 I Input signal for equalizer FCFCTL 6 ADR Filter coefficient address FCFCOF 16 Filter coefficient data z-1 z-1 z-1 A1 A2 A9 z-1z-1z-1 B2B9 z-1 z-1 z-1 D1 D2 D17 S18 I FIR IIR

Semiconductor Group 62 10.97 Due to the multitude of coefficients the uses an indirect addressing scheme for reading or writing an individual coefficient. The address of the coefficient is given by ADR and the actual value is read or written to register FCFCOF. In order to ease programming the PSB 4860 automatically increments the address ADR after each access to FCFCOF. Note: Any access to an out-of-range address automatically resets FCFCTL:ADR.

Semiconductor Group 63 10.97

2.2 Memory Management

Memory ManagementMemory Management - General This section describes the memory management provided by the PSB 4860. As figure 35 shows, three units can access the external memory. During recording, the speech coder can write compressed speech data into the external memory. For playback, the speech decoder reads compressed speech data from external memory. In addition, the microcontroller can directly access the memory by the SCI interface. Figure 35 Memory Management - Data Flow The memory is organized as a file system. For each memory space (R/W-memory and voice prompt memory) the PSB 4860 maintains a directory with 255 file descriptors (figure 36). Figure 36 Memory Management - Directory Structure The directories must be created after each power failure for volatile R/W-memory. All file descriptors are cleared (all words zero). For non-volatile memory, the directories have to Speech Decoder Speech Coder MemorySCI length (0-65535) user data (16 bits) file descriptor 1 file descriptor 255 file descriptor n file descriptor (R/W)directory RTC1 (16 bits) RTC2 (16 bits)

Semiconductor Group 64 10.97 be created only once. If the directories already exist, the memory has just to be activated after a reset. The file descriptors are not changed in this case. All commands that access the other fields or involve a write access must not be used in voice prompt memory space.

2.2.1 File Definition and Access

A file is a linear sequence of units and can be accessed in two modes: binary and audio. In binary mode, a unit is a word. In audio mode, a unit is a variable number of words representing 30 ms of uncompressed speech. A file can contain at most 65535 units. Figure 37 shows an audio file containing 100 audio units. The length of the message is therefore 3 s. Figure 37 Audio File Organization - Example Figure 38 shows a binary file of 11 words containing a phonebook (with only two entries). Figure 38 Binary File Organization - Example There is one special file in the voice prompt directory (referenced by file number 255) which is intended for a large number of phrases and hence has a different organization.This file exists only in the directory for the voice prompt memory. It consists of up to 2048 phrases of arbitrary individual length. The actual number of units within an individual phrase is determined during creation and cannot be altered afterwards. Phrases can be combined in any sequence without intermediate noise or gaps. Hi Jack, this is Tom. Please call me back tomorrow. 0 99 3 s 544F 4D20 3535 3534 3330 004A 4143 4B20 5555 5538 3131 TO 01 01 M 5 55 43 0 J A C K 5 55 81 1

Semiconductor Group 66 10.97 Writing to FCMD also resets the error bit in the status register. Table 35 shows the parameters defining the access mode and the access location. All parameters can only be written when no file command is currently running. They become effective after the completion of an open command. If another unit (e.g. speech coder) accesses the file, the file pointer is updated automatically. Therefore the controller can monitor the progress of recording or playing by reading the file pointer. Commands are written to the FCMD register. The busy bit in the STATUS register is set within 125µs. The command may start execution after a delay, however (see section 2.2.5). Some commands require additional parameters which are written prior to the command into the specified registers. Data transfer is done by the register FDATA (both reading and writing).

2.2.2 User Data Word

The user data word consists of 12 bits that can be read or written by the user, two bits (R) that are reserved for future use and two read-only bits (D,M) which indicate the status of a file. If D is set, the file is marked for deletion and should not be used any more. This bit is maintained by the PSB 4860 for housekeeping. Table 35 Memory Management Parameters Register # of Bits Name Comment FCTL 1 MS Memory space (R/W or voice prompt) FCTL 1 MD Access mode (audio or binary) FCTL 1 TS Write timestamp (file open only) FCTL 8 FNO File number (active file) FPTR 16 File pointer or phrase selector 15 0 D M R R User Definable

Semiconductor Group 67 10.97

2.2.3 High Level Memory Management Commands

This section describes each of the high level memory management commands in detail. These commands are sufficient for normal operation of an answering machine. In addition, there are four low level commands (section 2.2.4). These commands are only required for special tasks like in-system reprogramming of the voice prompt area. Memory Management - Commands

2.2.3.1 Initialize

This command creates a directory, sets the external memory configuration and delivers the size of usable memory in 1 kByte blocks. Furthermore the voice prompt memory space is scanned for a valid directory. The PSB 4860 can either create an empty directory from scratch or leave the first n files of an existing directory untouched while deleting the remaining files (ARAM/DRAM only). This option is useful if due to an unexpected event (e.g. power loss during recording) some data is corrupted. In that case vital system information can still be recovered if it has been stored in the first files. Possible Errors:

• no R/W memory found
• more than 59 bad blocks (flash and ARAM)
• voice prompt directory requested, but not detected Note: This command must be given only once for flash devices. Table 36 Initialize Memory Parameters Register # of Bits Name Comment FCMD 5 CMD Initialize command code FCMD 1 IN Confirmation for Initialization FCTL 8 FNO 0: delete no file 1: delete all files n: delete starting with file n CCTL 2 MT Type of R/W memory (DRAM, Flash) CCTL 1 MQ Quality of R/W memory (Audio, Normal) CCTL 1 MV Scan for voice prompt directory Table 37 Initialize Memory Results Register # of Bits Name Comment FDATA 16 Number of usable 1kByte blocks in R/W memory

Semiconductor Group 68 10.97

2.2.3.2 Activate

This command activates an existing directory, sets the external memory configuration and delivers the size of usable memory in 1 kByte blocks. Furthermore the voice prompt memory space is scanned for a valid directory. Upon activation the PSB 4860 checks (in case of ARAM/DRAM only) the consistency of the directory in R/W memory space. It returns the first file that contains corrupted data (if any). If corrupted data is detected an initialization should be performed with the same file number as an input parameter. Possible error conditions:

• no memory connected
• no directory found
• device ID wrong (flash only)
• corrupted files found (see FCTL:FNO)
• directory corrupted This command can have three types of result as shown in table 40. Table 38 Activate Memory Parameters Register # of Bits Name Comment FCMD 5 CMD Activate command code CCTL 2 MT Type of R/W memory (DRAM, Flash) CCTL 1 MQ Quality of R/W memory (Audio, Normal) CCTL 1 MV Voice prompt directory available Table 39 Activate Memory Results Register # of Bits Name Comment FDATA 16 Number of usable 1 kByte blocks in R/W memory FCTL 8 FNO n: number of first corrupted file Table 40 Activate Memory Result Interpretation Result STATUS: ERR FCTL: FNO Comment no error 0 0 Command successful, memory activated. soft error 1 n The first n-1 files are O.K. The memory is activated. hard error 1 1 The memory is not activated due to a hard error.

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2.2.3.3 Open File

A specific file is opened for subsequent accesses with the specified access mode. Opening a new file automatically closes the currently open file and clears the file pointer. Opening file number 0 can be used to close all physical files. If the TS flag is set, the current content of RTC1 and RTC2 is written to the appropriate fields of the file descriptor in order to provide a timestamp. Possible error conditions:

• selected file marked for deletion, but not yet deleted by garbage collection
• memory space invalid
• new file selected, but memory full
• <fno> exceeds number of prompts (in voice prompt space only)
• wrong access mode selected for existing file Note: In case of flash memory existing ones in the entries RTC1/RTC2 of the file descriptor cannot be altered. Therefore TS should be set only once during the lifetime of a file.

2.2.3.4 Open Next Free File

The next free file is opened for subsequent write accesses with the specified access mode. The search starts at the specified file number. If the TS flag is set, the current content of RTC1 and RTC2 is written to the appropriate fields of the file descriptor in order to provide a timestamp. If a free file has been found, the file is opened and the file number is returned in FCTL:FNO. Otherwise an error is reported. Table 41 Open File Parameters Register # of Bits Name Comment FCMD 5 CMD Open command code FCTL 1 MS Memory space (R/W, voice prompt) FCTL 1 MD Access mode (audio or binary) FCTL 1 TS Write timestamp FCTL 8 FNO File number <fno> Table 42 Open Next Free File Parameters Register # of Bits Name Comment FCMD 5 CMD Open Next Free File command code FCTL 1 MD Access mode (audio or binary)

Semiconductor Group 70 10.97 Possible error conditions:

• no unused file found
• memory full Note: In case of flash memory existing ones cannot be altered. Therefore TS should be set only once during the lifetime of a file. Note: R/W-memory must be selected. Otherwise the result is unpredictable.

2.2.3.5 Seek

The file pointer of the currently opened file is set to the specified position. If the current file is the phrase file the PSB 4860 starts the speech decoder immediately after the seek is finished. This is done by simply enabling the decoder. All other settings of the decoder remain unaffected. The BSY bit is first set during the file command. It is then reset for a short period until the speech decoder is enabled internally. It is then set again while the decoder is running and finally reset when the phrase is finished. Possible error conditions:

• file pointer out of range
• phrase number out of range FCTL 1 TS Write timestamp FCTL 8 FNO Starting point (>0) Table 43 Open Next Free File Results Register # of Bits Name Comment FCTL 8 FNO File number Table 44 Seek Parameters Register # of Bits Name Comment FCMD 5 CMD Seek command code FPTR 16 (11) File pointer (phrase selector) Table 42 Open Next Free File Parameters Register # of Bits Name Comment

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2.2.3.6 Cut File

All units starting with the unit addressed by the file pointer are removed from the file. If all units are deleted the file is marked for deletion (see user data word). However, the associated file descriptor and memory space are released only after a subsequent garbage collection. Possible error conditions:

• file pointer out of range
• voice prompt memory selected

2.2.3.7 Compress File

An audio file that has been recorded in HQ mode can be recoded using LP mode. This reduces the file size to approximately one third of the original size. The speech quality, however, is somewhat lower compared to a signal that has been recorded in LP mode in the first place. This command can be aborted at any time and resumed later without loss of information. Prior to this command all files must be closed. Table 46 shows the parameters for this command. Possible error conditions:

• <fno> invalid
• another file currently open
• binary file selected Table 45 Cut File Parameters Register # of Bits Name Comment FCMD 5 CMD Cut command code FPTR 16 Position of first unit to delete Table 46 Compress File Parameters Register # of Bits Name Comment FCMD 5 CMD Compress command code FCTL 8 FNO File number <fno>

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2.2.3.8 Memory Status

This command returns the number of available 1 kB blocks in R/W memory space. Possible error conditions:

• file open

2.2.3.9 Garbage Collection

This command initiates a garbage collection. Until a garbage collection files that are marked for deletion still occupy the associated file descriptor and memory space. After the garbage collection these file descriptors and the associated memory space are available again. This command can optionally remap the directory. In this mode the remaining file descriptors are remapped to form a contiguous block starting with file number 1. The original order is preserved. This command requires that all files are closed, i.e. file 0 is opened. Independently of the selected directory only the read/write directory is used. Possible error conditions:

• file open

2.2.3.10 Access File Descriptor

By this command the length, user data word and RTC1/RTC2 of a file descriptor can be read. The user data word can also be written. The file or the other entries of the file descriptor are not affected by this command. Table 47 Memory Status Parameters Register # of Bits Name Comment FCMD 5 CMD Memory status code Table 48 Memory Status Results Register # of Bits Name Comment FDATA 16 FREE Number of free blocks Table 49 Garbage Collection Parameters Register # of Bits Name Comment FCMD 5 CMD Garbage Collection Command Code FCMD 1 RD Remap Directory

Semiconductor Group 73 10.97 Possible error conditions:

• none Note: In case of flash memory bits already set to 1 cannot be altered. Note: Do not use this command with the phrase file (fno = 255).

2.2.3.11 Read Data

This command can be used in binary access mode only. A single word is read at the position given by the file pointer. The file pointer can be set by the Seek command. The file pointer is advanced by one word automatically. Possible error conditions:

• file pointer out of range
• phrase file selected
• audio file selected Table 50 Access File Descriptor Parameters Register # of Bits Name Comment FCMD 5 CMD Read Access or Write Access command code FDATA 16 User data (write access only) Table 51 Access File Descriptor Results Register # of Bits Name Comment FDATA 16 Content of selected entry (read access only) Table 52 Read Data Parameters Register # of Bits Name Comment FCMD 5 CMD Read Data Command Code Table 53 Read Data Results Register # of Bits Name Comment FDATA 16 Data word

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2.2.3.12 Write Data

This commands can be used in binary access mode only. A single word is written at the position of the file pointer. The file pointer is advanced by one word automatically. Note, that for FLASH memory only zeroes can be overwritten by ones. This restriction occurs only if an already used value within an existing file is to be overwritten. Possible error conditions:

• file pointer out of range (for existing files only)
• voice prompt memory selected
• memory full
• audio file selected Table 54 Write Data Parameters Register # of Bits Name Comment FCMD 5 CMD Access Mode Command Code (including mode) FDATA 16 Data word

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2.2.4 Low Level Memory Management Commands

These commands allow the direct access of any location (single word) of the external memory. Additionally it is possible to erase any block in case of a flash device. These commands should not be used during normal operation as they may interfere with the file system. No file must be open when one of these commands is given. The primary use of these commands is the in-system programming of a flash device with voice prompts. Please refer to the appropriate Application Notes.

2.2.4.1 Set Address

This command sets the 24 bit address pointer APTR. Only the address bits A 8-A23 are set, the address bits A0-A7 are automatically cleared. Possible error conditions:

• file open

2.2.4.2 DMA Read

This command reads a single word addressed by APTR. After the read access APTR is automatically incremented by one. Table 56 shows the parameters for this command. Possible error conditions:

• file open Table 55 Set Address Parameters Register # of Bits Name Comment FCMD 5 CMD Set Address command code FDATA 16 ADR Address bits A 8-A23 of address pointer APTR Table 56 DMA Read Parameters Register # of Bits Name Comment FCMD 5 CMD DMA Read command code Table 57 DMA Read Results Register # of Bits Name Comment FDATA 16 DATA Data read from address APTR.

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2.2.4.3 DMA Write

This command writes a single word to the location addressed by APTR. After the write access APTR is automatically incremented by one. Table 58 shows the parameters for this command. Possible error conditions:

• file open Note: If flash memory is connected the actual write is only performed when the last word within a page is written. Until then the data is merely buffered in the flash device. Please check the flash memory data sheets on page size.

2.2.4.4 Block Erase

This command erases the physical block which includes the address given by APTR. The actual amount of memory erased by this command depends on the block size of the flash device. Table 59 shows the parameters for this command. Possible error conditions:

• file open
• ARAM/DRAM configured Table 58 DMA Write Parameters Register # of Bits Name Comment FCMD 5 CMD DMA Write command code FDATA 16 DATA Data to be written to APTR Table 59 Block Erase Parameters Register # of Bits Name Comment FCMD 5 CMD Block Erase command code

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2.2.5 Execution Time

The execution time of the file commands is determined by four factors: 1. Internal state of the PSB 4860 2. Memory configuration 3. Memory state 4. Individual characteristics of the memory devices Therefore there is no general formula for an exact calculation of the execution time for file commands. For ARAM/DRAM items three and four are not significant as the memory access timing is always fixed and no additional delay is incurred for erasing memory blocks. However, the amount of memory has significant impact on the initialization in case of ARAM and flash. For flash devices the particular location of a write access in combination with the internal organization of the memory device may result in a block erase and subsequent write accesses in order to copy data. In this case the individual erase and write timing of the attached devices also prolongs the execution time. The first factor, the internal state of the PSB 4860, can influence all file commands regardless of the memory type attached. In general the PSB 4860 may delay any file command by up to 30 ms. However, it is possible to skip this delay if the following conditions hold: 1. The command is not initialize/activate 2. Neither the DTMF detector nor the speech coder nor the speech decoder are running If neither condition is violated then the PSB 4860 can be forced to start command execution immediately. This is done by setting the EIE bit in the FCMD register along with the command code. Table 60 gives an indication of the execution time for two typical memory configurations. Table 60 Execution Times Command ARAM (4 MBit) KM29LV040 Initialize 40 s 1) <11 s Activate < 10 ms 3 s Open File /Open Next Free File <10 ms <26 ms Seek (within 4 MBit File) <0.5 s <0.5 s Seek (within phrase file) <1 ms <1 ms Cut File <5 ms <5 ms Compress File #units * 30 ms #units * 30 ms Access File Descriptor <10 ms <10 ms

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2.2.6 Special Notes on File Commands

1. No MMU commands must be inserted between opening a file and writing data to it, either by writing data to a binary file or by enabling the coder for audio files. Therefore reading or writing the file descriptor is only allowed after all data writing has happened. 2. If an audio file has been opened for replay, a Write File Descriptor Command must be followed by a Seek command before the decoder can be enabled. 1) less than 20 ms for DRAM Memory Status <10 ms <10 ms Read/Write Data <10 ms <10 ms Garbage Collection <20 ms 3 s Table 60 Execution Times Command ARAM (4 MBit) KM29LV040

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2.3 Miscellaneous

MiscellaneousMiscellaneous

2.3.1 Real Time Clock

The PSB 4860 supplies a real time clock which maintains time with a resolution of a second and a range of up to a year. There are two registers which contain the current time and date (table 61). The real time clock maintains time during normal mode and power down mode only if the auxiliary oscillator OSC is running and the RTC is enabled. Note: Writing out-of-range values to RTC1 and RTC2 results in undefined operation of the RTC

2.3.2 SPS Control Register

The two SPS outputs (SPS0, SPS1) can be used as either general purpose outputs, speakerphone status outputs, extended address outputs for Voice Prompt EPROM or as status register outputs. Table 62 shows the associated register. When used as status register outputs, the status register bit at position POS appears at SPS 0 and the bit at position POS+1 appears at SPS1. This mode of operation can be used for debugging purposes or direct polling of status register bits.

2.3.3 Reset and Power Down Mode

The PSB 4860 can be in either reset mode, power down mode or active mode. During reset the PSB 4860 clears the hardware configuration registers and stops both internal Table 61 Real Time Clock Registers Register # of Bits Name Comment RTC1 6 SEC Seconds elapsed RTC1 6 MIN Minutes elapsed RTC2 5 HR Hours elapsed RTC2 11 DAY Days elapsed Table 62 SPS Registers SPSCTL 1 SP0 Output Value of SPS SPSCTL 1 SP1 Output Value of SPS 1 SPSCTL 3 MODE Mode of Operation SPSCTL 4 POS Position for status register window

Semiconductor Group 80 10.97 and external activity. The address lines MA0-MA 15 provide a weak low until they are actually used as address lines (strong outputs) or auxiliary port pins (I/O). In reset mode the hardware configuration registers can be read and written. With the first access to a read/write register the PSB 4860 enters active mode. In this mode the main oscillator is running and normal operation takes place. By setting the power down bit (PD) the PSB 4860 can be brought to power down mode. In power down mode the main oscillator is stopped and, depending on HWCONFIG2:PPM), the memory control lines are released (weak high). Depending on the configuration (ARAM/DRAM, APP) the PSB 4860 may still generate external activity (e.g. refresh cycles). The PSB 4860 enters active mode again upon an access to a read/ write register. Figure 40 shows a state chart of the modes of the PSB 4860. Figure 40 Operation Modes - State Chart

2.3.4 Interrupt

The PSB 4860 can generate an interrupt to inform the host of an update of the STATUS register according to table 64. An interrupt mask register (INTM) can be used to disable or enable the interrupting capability of each bit of the STATUS register except ABT individually. Table 63 Power Down Bit Register # of Bits Name Comment CCTL 1 PD power down mode Reset Active Mode Power Down Mode Mode CCTL.PD=1 R/W reg. access RST=1RST=1 R/W reg. access

Semiconductor Group 81 10.97 An interrupt is internally generated if any combination of these events occurs and the interrupt is not masked. The interrupt is cleared when the host reads the STATUS register. If a new event occurs while the host reads the status register, the status register is updated after the current access is terminated and a new interrupt is generated immediately after the access has ended. Note: If the internal interrupt occurs after the controller has already selected the device but not yet read the STATUS word, then the STATUS word is updated and the internal interrupt is cleared. Therefore the controller should always evaluate the STATUS word when read.

2.3.5 Abort

If the PSB 4860 cannot continue the current operations in progress (e.g. due to a transient loss of power) it stops operation and initializes all read/write registers to their reset state. After that it sets the ABT bit of the STATUS register and generates an interrupt. The PSB 4860 discards all commands with the exception of a write command to the revision register while ABT is set. Only after the write command to the revision register (with any value) the ABT bit is reset and a reinitialization can take place. Table 64 Interrupt Source Summary STATUS (old) STATUS (new) Set by Reset by RDY=0 RDY=1 Command completed Command issued CIA=0 CIA=1 New Caller ID byte available CIDCTL0 read CD=0 CD=1 Carrier detected Carrier lost CD=1 CD=0 Carrier lost Carrier detected CPT=0 CPT=1 Call progress tone detected CPT lost CPT=1 CPT=0 Call progress tone lost CPT detected CNG=0 CNG=1 Fax calling tone detected CNG lost DTV=0 DTV=1 DTMF tone detected DTMF tone lost DTV=1 DTV=0 DTMF tone lost DTMF tone detected ATV=0 ATV=1 Alert tone detected Alert tone lost ATV=1 ATV=0 Alert tone lost Alert tone detected BSY=1 BSY=0 File command completed New command issued SD=0 SD=1 Speech activity detected Speech activity lost SD=1 SD=0 Speech activity lost Speech activity detected

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2.3.6 Revision Register

The PSB 4860 contains a revision register. This register is read only and does not influence operation in any way. A write to the revision register clears the ABT bit of the STATUS register but does not alter the content of the revision register.

2.3.7 Hardware Configuration

The PSB 4860 can be adapted to various external hardware configurations by four special registers: HWCONFIG0 to HWCONFIG3. These registers are usually only written once during initialization and must not be changed while the PSB 4860 is in active mode. It is mandatory that the programmed configuration reflects the external hardware for proper operation. Special care must be taken to avoid I/O conflicts or excess current by enabling inputs without an external driving source. Table 65 can be used as a checklist.

2.3.8 Frame Synchronization

The PSB 4860 locks itself to either an externally supplied clock or frame sync signal or generates the frame sync signal itself. This internal reference frame sync signal is called master frame sync (MFSC). In addition, the PSB 4860 can derive the AFECLK and AFEFSC from either the main oscillator or an auxiliary clock input. Table 66 shows how AFECLK and MFSC are derived by the PSB 4860. The bits ACS and MFS are contained in the hardware configuration registers. Table 65 Hardware Configuration Checklist Register Name Value Check HWCONFIG0 PFRDY

1 FRDY must not float

HWCONFIG0 OSC 1 OSC1/2 must be connected to a crystal HWCONFIG0 ACS 1 CLK must not float (tie low if no clock present) HWCONFIG1 MFS 1 FSC must not float (tie low if no clock present) HWCONFIG1 ACT 1 FSC must not float (tie low if no clock present) Table 66 Frame Synchronization Selection 0 0 XTAL AFEFSC Analog featurephone 0 1 - FSC ISDN stand-alone 1 0 CLK AFEFSC DECT 1 1 CLK FSC unused

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2.3.9 Clock Tracking

The PSB 4860 can adjust AFECLK and AFEFSC dynamically to a slightly varying FSC if AFECLK and AFEFSC are derived from the main oscillator (XTAL). This mode requires that both AFEFSC and FSC are nominally running at the same frequency (8 kHz). This feature is especially useful when the FSC signal is not derived from the same clock source as AFECLK (ISDN application).

2.3.10 Dependencies of Modules

There are some restrictions concerning the modules that can be enabled at the same time (table 67). A checked cell indicates that the two modules (defined by the row and the column of the cell) must not be enabled at the same time. There are three classes of file commands denoted by the letters B, O and I. Table 68 shows the definition of these classes: Examples:

• The line echo canceller (in 24 ms mode) cannot be enabled when the speech decoder is running at slow speed.
• If the DTMF detector is running, none of the background file commands (B) must be executed. In addition, no file command must be executed with immediate execution 1) if Speech Decoder is running at slow speed Table 67 Dependencies of Modules Speech Encoder Speech Decoder Line EC (24 ms) Acoustic EC DTMF Detector File Command Speech Enc. X X X B,O,I Speech Dec. X X1) X B,O,I Line EC (24 ms) X X1) X B,O Acoustic EC X X X X B,O DTMF Det. X B,I File Cmd. B,O,I B,O,I B,O B,O B,I Table 68 File Command Classes Class Description B Background commands (Activate, Recompress, Garbage Collection, Initialize) O Open Commands (Open, Open Next Free File) I Any command executed with EIE=1 (i.e. immediate execution)

Semiconductor Group 84 10.97 enabled (I). However, files my be opened and other commands (like read or write) may be executed without immediate execution enabled. Furthermore it may be necessary to restrict the length of the FIR filter of the echo cancellation unit if several other units are operating at the same time. The sum of all weights (table 69) of the simultaneously enabled modules must not exceed 100 at any given time. Example:

• For an analog phone echo cancellation, DTMF tone generation, caller ID reception, and line echo cancellation are necessary. The system uses the PSB 4851 and the equalizer to linearize the loudspeaker. In this case the sum of all weights without echo cancellation is 35.6. Therefore 255 taps can be used for a total of 98.1.
• In an ISDN phone echo cancellation, channel 1 of the digital interface, the analog interface with clock tracking and the equalizer shall be enabled at the same time. In 1) The alert tone detector would add another 2.6, but can be disabled after the alert tone has been detected. Therefore it can be left out of the calculation. Table 69 Module Weights Module Weight Comment Example 1 Example 2 Equalizer 2.8 X X CPT Detector 5.6 Caller ID Decoder 1) 4.2 X CNG Detector 2.6 DTMF Generator 2.2 X Echo Cancellation 52.1 127 taps (16 ms) Echo Cancellation 62.5 255 taps (32 ms) X Echo Cancellation 72.9 383 taps (48 ms) Echo Cancellation 83.3 511 taps (64 ms) X Line Echo Cancellation 12.7 X Universal Attenuator 0.2 Digital Interface 1.7 channel 1 or SSDI X Digital Interface 1.7 channel 2 Analog Interface 2.5 X X Clock Tracking 0.6 X Miscellaneous 8.0 always active X X

Semiconductor Group 85 10.97 this application the sum of all weights without echo cancellation is 15.6. Therefore 511 taps can be used for a total of 98.9.

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2.4 Interfaces

This section describes the interfaces of the PSB 4860. The PSB 4860 supports both an IOM ® -2 interface with single and double clock mode and a strobed serial data interface (SSDI). However, these two interfaces cannot be used simultaneously as they share some pins. Both interfaces are for data transfer only and cannot be used for programming the PSB 4860. Table 70 lists the features of the two alternative interfaces. ® -2 Interface The data stream is partitioned into packets called frames. Each frame is divided into a fixed number of timeslots. Each timeslot is used to transfer 8 bits. Figure 41 shows a commonly used terminal mode (three channels ch0, ch1 and ch2 with four timeslots each). The first timeslot (in figure 41: B1) is denoted by number 0, the second one (B2) by 1 and so on. Figure 41 IOM® -2 Interface - Frame Structure The signal FSC is used to indicate the start of a frame. Figure 42 shows as an example two valid FSC-signals (FSC, FSC*) which both indicate the same clock cycle as the first clock cycle of a new frame (T1). Note: Any timeslot (including M0, CI0, ...) can be used for data transfer. However, programming is not supported via the monitor channels. Table 70 SSDI vs. IOM® -2 Interface IOM ® -2 SSDI Signals 4 6 Channels (bidirectional) 2 1 Code linear PCM, A-law, µ-law linear PCM Synchronization within frame by timeslot (programmable) by signal (DXST, DRST) B1 M0 B2 FSC DD/DU ch0 ch1 ch2 125 µs CI0 IC1 M1IC2 CI1

Semiconductor Group 88 10.97 Figure 44 IOM® -2 Interface - Double Clock Mode The PSB 4860 supports up to two channels simultaneously for data transfer. Both the coding (PCM or linear) and the data direction (DD/DU assignment for transmit/receive) can be programmed individually for each channel. Table 71 shows the registers used for configuration of the IOM ® -2 interface. In A-law or µ-law mode, only 8 bits are transferred and therefore only one timeslot is needed for a channel. In linear mode, 16 bits are needed for a single channel. In this mode, two consecutive timeslots are used for data transfer. Bits 8 to 15 are transferred Table 71 IOM ® -2 Interface Registers Register # of Bits Name Comment SDCONF 1 EN Interface enable SDCONF 1 DCL Selection of clock mode SDCONF 6 NTS Number of timeslots within frame SDCHN1 1 EN Channel 1 enable SDCHN1 6 TS First timeslot (channel 1) SDCHN1 1 DD Data Direction (channel 1) SDCHN1 1 PCM 8 bit code or 16 bit linear PCM (channel 1) SDCHN1 1 PCD 8 bit code (A-law or µ-law, channel 1) SDCHN2 1 EN Channel 2 enable SDCHN2 6 TS First timeslot (channel 2) SDCHN2 1 DD Data Direction (channel 2) SDCHN2 1 PCM 8 bit code or 16 bit linear PCM (channel 2) SDCHN2 1 PCD 8 bit code (A-law or µ-law, channel 2) DCL DD/DR DU/DX bit 0 bit 1 bit 2 bit 0 bit 1 T2 T3 T4 T5

Semiconductor Group 89 10.97 within the first timeslot and bits 0 to 7 are transferred within the next timeslot. The first timeslot must have an even number. The most significant bit is always transmitted first.

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2.4.2 SSDI Interface

The SSDI interface is intended for seamless connection to low-cost burst mode controllers (e.g. PMB 27251) and supports a single channel in each direction. The data stream is partitioned into frames. Within each frame one 16 bit value can be sent and received by the PSB 4860. The start of a frame is indicated by the rising edge of FSC. Data is always sampled at the falling edge of DCL and shifted out with the rising edge of DCL. The SSDI transmitter and receiver are operating independently of each other except that both use the same FSC and DCL signal.

2.4.2.1 SSDI Interface - Transmitter

The PSB 4860 indicates outgoing data (on signal DX) by activating DXST for 16 clocks. The signal DXST is activated with the same rising edge of DCL that is used to send the first bit (Bit 15) of the data. DXST is deactivated with the first rising edge of DCL after the last bit has been transferred. The PSB 4860 drives the signal DX only when DXST is activated. Figure 45 shows the timing for the transmitter. Figure 45 SSDI Interface - Transmitter Timing

2.4.2.2 SSDI Interface - Receiver

Valid data is indicated by an active DRST pulse. Each DRST pulse must last for exactly 16 DCL clocks. As there may be more than one DRST pulses within a single frame the PSB 4860 can be programmed to listen to the n-th pulse with n ranging from 1 to 16. In order to detect the first pulse properly, DRST must not be active at the rising edge of FSC. In figure 46 the PSB 4860 is listening to the third DRST pulse (n=3). FSC 125 µs DXST DCL DU/DX bit 15 bit 14 bit 1 bit 0

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2.4.3 Analog Front End Interface

The PSB 4860 uses a four wire interface similar to the IOM® -2 interface to exchange information with the analog front end (PSB 4851). The main difference is that all timeslots and the channel assignments are fixed as shown in figure 48. Figure 48 Analog Front End Interface - Frame Structure Voice data is transferred in 16 bit linear coding in two bidirectional channels C1 and C2. An auxiliary channel C3 is used to transfer the current setting of the loudspeaker amplifier ALS to the PSB 4860. The remaining bits are fixed to zero. In the other direction C 3 transfers an override value for ALS from the PSB 4860 to the PSB 4851. An additional override bit OV determines if the currently transmitted value should override the AOAR:LSC 1) setting. The AOAR:LSC setting is not affected by C3:ALS override. Table 73 shows the source control of the gain for the ALS amplifier. Furthermore the AFE interface can be enabled or disabled according to table 74. 1) See specification of PSB 4851, automatically set by the PSB 4860 in loudhearing mode. Table 73 Control of ALS Amplifier AOPR:OVRE C 3:OV Gain of ALS amplifier 0 - AOAR:LSC 1 0 AOAR:LSC 11 C 3:ALS Table 74 Analog Front End Interface Register Register # of Bits Name Comment AFECTL 1 EN Interface enable Channel C1 Channel C3Channel C2 AFEFS AFEDD 125 µs ALS AFEDU unused

000 O V

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2.4.4 Serial Control Interface

The serial control interface (SCI) uses four lines: SDR, SDX, SCLK and CS. Data is transferred by the lines SDR and SDX at the rate given by SCLK. The falling edge of CS indicates the beginning of an access. Data is sampled by the PSB 4860 at the rising edge of SCLK and shifted out at the falling edge of SCLK. Each access must be terminated by a rising edge of CS. The accesses to the PSB 4860 can be divided into three classes: 1. Configuration Read/Write 2. Status/Data Read 3. Register Read/Write If the PSB 4860 is in power down mode, a read access to the status register does not deliver valid data with the exception of the RDY bit. After the status has been read the access can be either terminated or extended to read data from the PSB 4860. A register read/write access can only be performed when the PSB 4860 is ready. The RDY bit in the status register provides this information. Any access to the PSB 4860 starts with the transfer of 16 bits to the PSB 4860 over line SDR. This first word specifies the access class, access type (read or write) and, if necessary, the register accessed. If a configuration register is written, the first word also includes the data and the access is terminated. Likewise, if a register read is issued, the access is terminated after the first word. All other accesses continue by the transfer of the status register from the PSB 4860 over line SDX. If a register (excluding configuration) is to be written, the next 16 bits containing the data are transferred over line SDR and the access is terminated. Figures 51 to 54 show the timing diagrams for the different access classes and types to the PSB 4860. Figure 51 Status Register Read Access CS SCLK SDR c 15 c14 c1 c0 s15 s14 s1 s0SDX c15,..,c0: s15,..,s0: command word for status register read : status register: INT

Semiconductor Group 97 10.97 In case of a configuration register write, W determines which configuration register is to be written (table 77): In case of a configuration register read, R determines which pair of configuration registers is to be read (table 78): Note: Reading any register except the status register or a hardware configuration register requires at least two accesses. The first access is a register read command (figure 55). With this access the register address is transferred to the. After that access data read accesses (figure 52) must be executed. The first data read access with STATUS:RDY=1 delivers the value of the register. Table 76 Command Words for Register Access 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Read Status Register or Data Read Access 001100000000 0000 R e a d R e g i s t e r 0101 R E G W r i t e R e g i s t e r 0100 R E G Read Configuration Reg.011100R000000000 Write Configuration Reg.011000 W D A T A Table 77 Address Field W for Configuration Register Write 9 8 Register 0 0 HWCONFIG 0 0 1 HWCONFIG 1 1 0 HWCONFIG 2 1 1 HWCONFIG 3 Table 78 Address Field R for Configuration Register Read

9 Register pair

0 HWCONFIG 0 / HWCONFIG 1

1 HWCONFIG 2 / HWCONFIG 3

Semiconductor Group 98 10.97

2.4.5 Memory Interface

The PSB 4860 supports either Flash Memory or ARAM/DRAM as external memory for storing messages. If ARAM/DRAM is used, an EPROM can be added optionally to support read-only messages (e.g. voice prompts). Table 79 summarizes the different configurations supported. If ARAM/DRAM is used, the total amount of memory must be a power of two and all devices must be of the same type. The pin FRDY must be tied high. For flash devices, the PSB 4860 supports in-circuit programming of voice prompts by releasing the control lines during reset and (optionally) power down. Instead of actively driving the lines FCS , FOE, FWE, FCLE and ALE these lines are pulled high by a weak pullup during reset and (optionally) power down. Table 79 Supported Memory Configurations Mbit Type Bank 0 (D 0-D3) Bank 1 (D4-D7) Comment

1 ARAM/DRAM 256kx4 -

2 ARAM/DRAM 256kx4 256kx4

4 ARAM/DRAM 1Mx4 -

4 ARAM/DRAM 512kx8

8 ARAM/DRAM 1Mx4 1Mx4

16 ARAM/DRAM 4Mx4 - 2k or 4k refresh

16 ARAM/DRAM 2Mx8 2k refresh

32 ARAM/DRAM 4Mx4 4Mx4 2k or 4k refresh

32 ARAM/DRAM 2x2Mx8 2k refresh

64 ARAM/DRAM 16Mx4 - 4k or 8k refresh

64 ARAM/DRAM 8Mx8 4k or 8k refresh

128 ARAM/DRAM 16Mx4 16Mx4 4k or 8k refresh

4-128 FLASH 512kx8 devices KM29N040 16-128 FLASH 2Mx8 devices KM29N16000

Semiconductor Group 99 10.97

2.4.5.1 ARAM/DRAM Interface

The PSB 4860 supports up to two banks of memory which may be 4 bit or 8 bit wide (Figure 56). If both banks are used they must be populated identically. Figure 56 ARAM/DRAM Interface - Connection Diagram MA 0-MA 15 MD 0-MD 3 RAS CAS 0 W A0-A12 D 0-D3 RAS CAS W OE MA 0-MA 15 MD 0-MD 3 RAS CAS 0 W A0-A12 D 0-D7 RAS CAS W OE single 4 bit bank single 8 bit bank MA 0-MA 15 MD 0-MD 7 RAS CAS 0 W A0-A12 D 0-D3 RAS CAS W OE A0-A12 D 0-D3 RAS CAS W OE MD 4-MD 7 CAS 1 two 4 bit banks MA 0-MA 15 MD 0-MD 7 RAS CAS 0 W A0-A12 D 0-D7 RAS CAS W OE A0-A12 D 0-D7 RAS CAS W OE CAS 1 two 8 bit banks PSB 4860 PSB 4860 PSB 4860 PSB 4860

Semiconductor Group 100 10.97 The PSB 4860 also supports different internal organizations of ARAM/DRAM chips. Table 80 shows the necessary connections on the address bus. The timing of the ARAM/DRAM interface is shown in figures 57 to 59. The timing is derived form the internal memory clock MCLK* which runs at a quarter of the system clock. Figure 57 ARAM/DRAM Interface - Read Cycle Timing 1) see chip control register CCTL Table 80 Address Line Usage (ARAM/DRAM Mode) ARAM/DRAM CS9 1) MA 0-MA 8 MA 9 MA 10 MA 11 MA 12 MA 13 256k x4 1 A 0-A8 512k x8 1 A 0-A8 A9 1M x4 0 A 0-A8 A9 4M x4 (2k refresh) 0 A 0-A8 A9 A10 4M x4 (4k refresh) 0 A 0-A8 A9 A10 A11 2M x8 0 A 0-A8 A9 A10 16M x4 (4k refresh) 0 A 0-A8 A9 A10 A11 16M x4 (8k refresh) 0 A 0-A8 A9 A10 A11 A12 8M x8 (4k refresh) 0 A 0-A8 A9 A10 A11 8M x8 (8k refresh) 0 A 0-A8 A9 A10 A11 A12 MCLK* MA 0-MA 13 MD 0-MD 7 CAS 0,CAS1 RAS row addr. col. addr.

Semiconductor Group 102 10.97

2.4.5.2 EPROM Interface

The PSB 4860 supports an EPROM in parallel with ARAM/DRAM. This interface is always 8 Bits wide and supports a maximum of 256 kB. Figure 60 shows a connection diagram and figure 61 the timing. This interface supports read cycles only. Figure 60 EPROM Interface - Connection Diagram Figure 61 EPROM Interface - Read Cycle Timing Note: In order to access more than 64 kB the pins SPS0 and SPS1 can be programmed to provide the address lines A16 and A17. In this mode A16 and A17 remain stable during the whole read cycle. See the register SPSCTL for programming information. MA 0-MA 15 MD 0-MD 7 VPRD A0-A15 D 0-D7 CE OEPSB 4860 A16 A17SPS 1 SPS 0 VPRD MD 0-MD 7 MCLK* MA 0-MA 15

Semiconductor Group 103 10.97

2.4.5.3 Flash Memory Interface

The PSB 4860 has special support for the KM29N040 and KM29N16000 or equivalent devices. No external components are required for up to four KM29N040. Figure 62 shows the connection diagram for a single device. Figure 62 Flash Memory Interface - Connection Diagram Table 82 shows the signals output during a device access on the MA-lines. The address bits can used by an external decoder. Up to four KM29N040 are supported directly by the decoded select signals FCS0-FCS3. Table 82 Address Line Usage (Samsung Mode) MA 11 MA 10 MA 9 MA 8 MA 7 MA 6 MA 5 MA 4 MA 3 MA 2 MA 1 MA 0 FCS 3 FCS 2 FCS 1 FCS 0 A23 A22 A21 A20 A19 A18 A17 A16 D 0-D7 CE RE WE CLE MD 0-MD 7 FCS FOE FWR FCLE ALE ALE +5V R/BFRDY WPPSB 4860

Semiconductor Group 107 10.97

2.4.6 Auxiliary Parallel Port

The PSB 4860 provides an auxiliary parallel port if the memory interface is in Samsung mode and only one device is used. In this case the lines MA0 to MA15 are not needed for the memory interface and can therefore be used for an auxiliary parallel port. This port has two modes: static mode and multiplex mode.

2.4.6.1 Static Mode

In static mode all pins of the auxiliary parallel port interface have identical functionality. Any pin can be configured as an output or an input. Pins configured as outputs provide a static signal as programmed by the controller. Pins configured as inputs are monitoring the signal continuously without latching. The controller always reads the current value. Table 84 shows the registers used for static mode.

2.4.6.2 Multiplex Mode

In multiplex mode, the PSB 4860 uses MA 12-MA 15 to distinguish four timeslots. Each timeslot has a duration of approximately 2 ms. The timeslots are separated by a gap of approximately 125 µs in which none of the signals at MA12-MA 15 are active. The PSB 4860 multiplexes three more output registers to MA0-MA 11 in timeslots 0, 1 and 2. In timeslot 3 the direction of the pins can be programmed. For input pins, the signal is latched at the falling edge of MA15. Table 85 shows the registers used for multiplex mode. This mode is useful for scanning keys or controlling seven segment LED displays. Table 84 Static Mode Registers Register # of bits Comment DOUT3 16 Output signals (for pins configured as outputs) DIN 16 Input signals (for pins configured as inputs) DDIR 16 Pin direction Table 85 Multiplex Mode Registers Register # of bits Comment DOUT0 12 Output signals on MA 0-MA 11 while MA15=1 DOUT1 12 Output signals on MA 0-MA 11 while MA14=1 DOUT2 12 Output signals on MA 0-MA 11 while MA13=1 DOUT3 12 Output signals (for pins configured as outputs) while MA12=1 DIN 12 Input signals (for pins configured as inputs) at falling edge of MA12 DDIR 12 Pin direction during MA 12=1

Detailed Register Description Semiconductor Group 109 10.97

3 Detailed Register Description

The PSB 4860 has a single status register (read only) and an array of data registers (read/write). The purpose of the status register is to inform the external microcontroller of important status changes of the PSB 4860 and to provide a handshake mechanism for data register reading or writing. If the PSB 4860 generates an interrupt, the status register contains the reason of the interrupt.

3.1 Status Register

0: The last command (if any) is still in progress. 1: The last command has been executed. ABT Abort 0: No exception during operation 1: Some exception other than reset caused the PSB 4860 to abort any operation currently in progress. The external microcontroller should reinitialize the PSB 4860 to ensure proper operation. The ABT bit is cleared by writing any value to register REV. No other command is accepted by the PSB 4860 while ABT is set. CIA Caller ID Available 0: No new data for caller ID 1: New caller ID byte available CD Carrier Detect 0: No carrier detected 1: Carrier detected 1) undefined 15 0 RDY ABT 0 0 CIA CD CPT CNG SD ERR BSY DTV ATV - 1) -1) -1)

Detailed Register Description Semiconductor Group 110 10.97 CPT Call Progress Tone 0: Currently no call progress tone detected or pause detected (raw mode) 1: Currently a call progress is detected CNG Fax Calling Tone 0: Currently no fax calling tone detected 1: Currently a fax calling tone is detected SD Speech Detected 0: No speech detected 1: Speech signal at input of coder ERR Error (File Command) 0: No error 1: Last file command resulted in an error BSY Busy (File Command) 0: File system idle 1: File system still busy (also set during encoding/decoding) DTV DTMF Tone Valid 0: No new DTMF code available 1: New DTMF code available in DDCTL ATV Alert Tone Valid 0: No new alert tone code available 1: New alert tone code available in ADCTL0

Detailed Register Description Semiconductor Group 111 10.97

3.2 Hardware Configuration Registers

HWCONFIG 0 - Hardware Configuration Register 0 PPSDX Push/Pull for SDX 0: The SDX pin has open-drain characteristic 1: The SDX pin has push/pull characteristic PPINT Push/Pull for INT 0: The INT pin has open-drain characteristic 1: The INT pin has push/pull characteristic PFRDY Pullup for FRDY 0: The internal pullup resistor of pin FRDY is enabled 1: The internal pullup resistor of FRDY is disabled PPSDI Push/Pull for SDI interface 0: The DU and DD pins have open-drain characteristic 1: The DU and DD pins have push/pull characteristic OSC Enable Auxiliary Oscillator 0: The auxiliary oscillator (OSC1, OSC2) is disabled 1: The auxiliary oscillator (OSC1, OSC2) is enabled RTC Enable Real Time Clock 0: The real time clock is disabled 1: The real time clock (RTC) is enabled. ACS AFE Clock Source 0: AFECLK is derived from the main oscillator 1: AFECLK is derived from the CLK input PD Power Down (read only) 0: The PSB 4860 is in active mode 1: The PSB 4860 is in power down mode 7 0 PD ACS RTC OSC PPSDI PFRDY PPINT PPSDX

Detailed Register Description Semiconductor Group 112 10.97 HWCONFIG 1 - Hardware Configuration Register 1 APP Auxiliary Parallel Port ACT AFE Clock Tracking 0: AFECLK tracking disabled 1: AFECLK tracking enabled ADS AFE Double Speed 0: 8 kHz AFEFSC 1: 16 kHz AFEFSC MFS Master Frame Sync Selection 0: AFEFSC 1: FSC XTAL XTAL Frequency SSDI SSDI Interface Selection 0: IOM® -2 Interface 1: SSDI Interface 1) The factor p is needed to calculate the clock frequency at AFECLK. 7 0 APP ACT ADS MFS XTAL SSDI 7 6 Description 0 0 normal (ARAM/DRAM, Intel type flash, voice prompt EPROM) 0 1 APP static mode 1 0 APP multiplex mode 1 1 reserved 2 1 Factor p 1) Description 0 0 reserved reserved 0 1 4.5 31.104 MHz 1 0 reserved reserved 1 1 reserved reserved

Detailed Register Description Semiconductor Group 113 10.97 HWCONFIG 2 - Hardware Configuration Register 2 PPM Push/Pull for Memory Interface (reset, power down) 0: The signals for the memory interface have push/pull characteristic 1: The signals for the memory interface have pullup/pulldown characteristic ESDX Edge Select for DX 0: DX is transmitted with the rising edge of DCL 1: DX is transmitted with the falling edge of DCL ESDR Edge Select for DR 0: DR is latched with the falling edge of DCL 1: DR is latched with the rising edge of DCL CSEL Codec Selection for AFE interface 0: Interface to PSB 4851 1: Interface to AK 4510 CHS Channel Select (AK 4510 only) RSEL Refresh Select 7 0 PPM ESDX ESDR CSEL CHS RSEL 3 2 Description 0 0 left channel of AK 4510 0 1 right channel of AK4510 1 0 left and right channel 1 1 reserved 1 0 Description 0 0 64 kHz refresh frequency 0 1 32 kHz refresh frequency 1 0 16 kHz refresh frequency 1 1 8 kHz refresh frequency

Detailed Register Description Semiconductor Group 114 10.97 HWCONFIG 3 - Hardware Configuration Register 3 7 0 00000000

Detailed Register Description Semiconductor Group 115 10.97

3.3 Read/Write Registers

The following sections contains all read/write registers of the PSB 4860. The register addresses are given as hexadecimal values. Registers marked with an R are affected by reset or a wake up after power down. All other registers retain their previous value. No access must be made to addresses other than those associated with a read/write register.

3.3.1 Register Table

Address. Name Long Name Page

Detailed Register Description Semiconductor Group 116 10.97

Detailed Register Description Semiconductor Group 117 10.97 Note: Registers CCTL, FCTL, FCMD, FDATA, FPTR, RTC1, RTC2, DOUT0, DOUT1, DOUT2, DOUT3 and DDIR are only affected by reset, not by wakeup. For register SPSCTL see the register description for the exact behaviour.

3.3.2 Register Naming Conventions

Several registers contain one or more fields for input signal selection. All fields labelled I1 (I2, I3) are five bits wide and use the same coding as shown in table 86. Table 86 Signal Encoding 4 3 2 1 0 Signal Description

00000 S 0 Silence

00001 S 1 Analog line input (channel 1 of PSB 4851 interface)

Detailed Register Description Semiconductor Group 118 10.97

00010 S 2 Analog line output (channel 1 of PSB 4851 interface)

00011 S 3 Microphone input (channel 2 of PSB 4851 interface)

00100 S 4 Loudspeaker/Handset output (channel 2 of PSB

4851 interface)

00101 S 5 Serial interface input, channel 1

00110 S 6 Serial interface output, channel 1

00111 S 7 Serial interface input, channel 2

01000 S 8 Serial interface output, channel 2

01001 S 9 DTMF generator output

01010 S 10 DTMF generator auxiliary output

01011 S 11 Speakerphone output (acoustic side)

01100 S 12 Speakerphone output (line side)

01101 S 13 Speech decoder output

01110 S 14 Universal attenuator output

01111 S 15 Line echo canceller output

10000 S 16 AGC unit output (after AGC)

10001 S 17 AGC unit output (before AGC)

10010 S 18 Equalizer output

4 3 2 1 0 Signal Description

Detailed Register Description Semiconductor Group 119 10.97 00h REV Revision The revision register can only be read. For the PSB 4860, V2.1, all bits except bit 12 are zero. Note: A write access to the revision register does not alter its content. It does, however, reset the ABT bit of the STATUS register. 15 0 0001000000000000

Detailed Register Description Semiconductor Group 120 10.97 01h R CCTL Chip Control MV Voice Prompt Directory 0: not available 1: available (within EPROM or Flash) PD Power Down 0: PSB 4860 is in active mode 1: enter power-down mode MQ Memory Quality 0: ARAM 1: DRAM MT Memory Type CS9 CAS selection 0: other memory 1: 256kx4 or 512kx8 memory SAS Split Address Space 0: other ARAM/DRAM 1: two 2Mx8 devices 15 0

0000 M V 00 P D 000 M Q M T C S 9 S A S

Detailed Register Description Semiconductor Group 121 10.97 02h R INTM Interrupt Mask Register If a bit of this register is reset (set to 0), the corresponding bit of the status register does not generate an interrupt. If a bit is set (set to 1), an external interrupt can be generated by the corresponding bit of the status register. 15 0 RDY 1 0 0 CIA CD CPT CNG SD ERR BSY DTV ATV 0 0 0 Reset Value 0100000000000000

Detailed Register Description Semiconductor Group 122 10.97 03h R AFECTL Analog Front End Interface Control ALS Loudspeaker Amplification This value is transferred on channel C3 of the AFE interface. If the PSB 4851 is used it represents the amplification of the loudspeaker amplifier. EN Interface Enable 0: AFE interface disabled 1: AFE interface enabled 15 0

0000 A L S 0000000 E N

Detailed Register Description Semiconductor Group 123 10.97 04h R IFS1 Interface Select 1 The signal selection fields I1, I2 and I3 of IFS1 determine the outgoing signal of channel 1 of the analog interface. For the PSB 4851 this is usually the line out signal. The HP bit enables a high-pass for the incoming signal of channel 1 of the analog interface. For the PSB 4851 this is usually the line in signal. HP High-Pass for S 1 0: Disabled 1: Enabled I1 Input signal 1 for IG2 I2 Input signal 2 for IG2 I3 Input signal 3 for IG2 Note: As all sources are always active, unused sources must be set to 0 (S0). 15 0 HP I1 I2 I3 Reset Value 00 0 0

Detailed Register Description Semiconductor Group 124 10.97 05h R IFG1 Interface Gain 1 IFG1 is associated with the incoming signal of channel 1 of the analog interface. For the PSB 4851 this is usually the line in signal. IG1 In order to obtain a gain G the parameter IG1 can be calculated by the following formula: 15 0 0I G 1 Reset Value 0 8192 (0 dB) IG1 32768 G 12.04 dB–() 20 dB⁄×10=

Detailed Register Description Semiconductor Group 125 10.97 06h R IFG2 Interface Gain 2 IFG2 is associated with the outgoing signal of channel 1 of the analog interface. For the PSB 4851 this is usually the line out signal. IG2 Gain of Amplifier IG2 In order to obtain a gain G the parameter IG2 can be calculated by the following formula: 15 0 0I G 2 Reset Value 0 8192 (0 dB) IG2 32768 G 12.04 dB–() 20 dB⁄×10=

Detailed Register Description Semiconductor Group 126 10.97 07h R IFS2 Interface Select 2 The signal selection fields I1, I2 and I3 of IFS2 determine the outgoing signal of channel 2 of the analog interface. For the PSB 4851 this is usually the loudspeaker signal. The HP bit enables a high-pass for the incoming signal of channel 2 of the analog interface. For the PSB 4851 this is usually the microphone signal. HP High-Pass for S 3 0: Disabled 1: Enabled I1 Input signal 1 for IG4 I2 Input signal 2 for IG4 I3 Input signal 3 for IG4 Note: As all sources are always active, unused sources must be set to 0 (S0). 15 0 HP I1 I2 I3 Reset Value 00 0 0

Detailed Register Description Semiconductor Group 127 10.97 08h R IFG3 Interface Gain 3 IFG3 is associated with the incoming signal of channel 2 of the analog interface. For the PSB 4851 this is usually the microphone signal. IG3 Gain of Amplifier IG3 In order to obtain a gain G the parameter IG3 can be calculated by the following formula: 15 0 0I G 3 Reset Value 0 8192 (0 dB) IG3 32768 G 12.04 dB–() 20 dB⁄×10=

Detailed Register Description Semiconductor Group 128 10.97 09h R IFG4 Interface Gain 4 IFG4 is associated with the outgoing signal of channel 2 of the analog interface. For the PSB 4851 this is usually the loudspeaker signal. IG4 Gain of Amplifier IG4 In order to obtain a gain G the parameter IG4 can be calculated by the following formula: 15 0 0I G 4 Reset Value 0 8192 (0 dB) IG4 32768 G 12.04 dB–() 20 dB⁄×10=

Detailed Register Description Semiconductor Group 129 10.97 0A h R SDCONF Serial Data Interface Configuration NTS Number of Timeslots DCL Double Clock Mode 0: Single Clock Mode 1: Double Clock Mode EN Enable Interface 0: Interface is disabled (both channels) 1: Interface is enabled (depending on separate channel enable bits) 15 0

00 N T S 00000 D C L 0 E N

13 12 11 10 9 8 Description 000000 1 000001 2 111111 6 4

Detailed Register Description Semiconductor Group 130 10.97 0B h R SDCHN1 Serial Data Interface Channel 1 NAS Number of active DRST strobe (SSDI interface mode) PCD PCM Code 0: A-law 1: µ-law EN Enable Interface 0: Interface is disabled 1: Interface is enabled if SDCONF:EN=1 PCM PCM Mode 0: 16 Bit Linear Coding (two timeslots) 1: 8 Bit PCM Coding (one timeslot) DD Data Direction 0: DD: Data Downstream, DU: Data Upstream 1: DD: Data Upstream, DU: Data Downstream TS Timeslot for Channel 1 15 0 NAS 0 0 PCD EN PCM DD TS Reset Value 0 000000 0 15 14 13 12 Description 0000 1 1111 1 6

543210 D e s c r i p t i o n

Detailed Register Description Semiconductor Group 131 10.97 Note: If PCM=0 then TS denotes the first timeslot of the two consecutive timeslots used. Only even timeslots are allowed in this case.

Detailed Register Description Semiconductor Group 132 10.97 0C h R IFS3 Interface Select 3 The signal selection fields I1, I2 and I3 of IFS3 determine the outgoing signal of channel 1 of the IOM/SSDI-interface. The HP bit enables a high-pass for the incoming signal of channel 1 of the analog IOM/ SSDI-interface. HP High-Pass for S 6 0: Disabled 1: Enabled I1 Input signal 1 for S5 I2 Input signal 2 for S5 I3 Input signal 3 for S5 Note: As all sources are always active, unused sources must be set to 0 (S0). 15 0 HP I1 I2 I3 Reset Value 00 0 0

Detailed Register Description Semiconductor Group 133 10.97 0D h R SDCHN2 Serial Data Interface Channel 2 PCD PCM Code 0: A-law 1: µ-law EN Enable Interface 0: Interface is disabled 1: Interface is enabled if SDCONF:EN=1 PCM PCM Mode 0: 16 Bit Linear Coding (two timeslots) 1: 8 Bit PCM Coding (one timeslot) DD Data Direction 0: DD: Data Downstream, DU: Data Upstream 1: DD: Data Upstream, DD: Data Downstream TS Timeslot for Channel 2 Note: If PCM=0 then TS denotes the first timeslot of the two consecutive timeslots used. Only even timeslots are allowed in this case. 15 0

000000 P C D E N P C M D D T S

Detailed Register Description Semiconductor Group 134 10.97 0Eh R IFS4 Interface Select 4 The signal selection fields I1, I2 and I3 of IFS4 determine the outgoing signal of channel 2 of the IOM/SSDI-interface. The HP bit enables a high-pass for the incoming signal of channel 2. HP High-Pass for S 0: Disabled 1: Enabled I1 Input signal 1 for S8 I2 Input signal 2 for S8 I3 Input signal 3 for S8 As all sources are always active, unused sources must be set to 0 (S0). 15 0 HP I1 I2 I3 Reset Value 00 0 0

Detailed Register Description Semiconductor Group 135 10.97 0Fh R IFG5 Interface Gain 5 ATT1 Attenuation for I3 (Channel 1) In order to obtain an attenuation A the parameter ATT1 can be calculated by the following formula: ATT2 Attenuation for I3 (Channel 2) In order to obtain an attenuation A the parameter ATT2 can be calculated by the following formula: 15 0 ATT1 ATT2 Reset Value 255 (0 dB) 255 (0 dB) ATT1 256 A2 0 d B⁄×10= ATT2 256 A2 0 d B⁄×10=

Detailed Register Description Semiconductor Group 136 10.97 10h R UA Universal Attenuator ATT Attenuation for UA For a given attenuation A [dB] the parameter ATT can be calculated by the following formula: I1 Input Selection for UA 15 0 A T T 000 I 1 Reset Value 0 (-100 dB) 0 0 0 0 ATT 256 A2 0 d B⁄×10=

Detailed Register Description Semiconductor Group 137 10.97 11h R DGCTL DTMF Generator Control EN Generator Enable 0: Disabled 1: Enabled MD Mode 0: raw 1: cooked DTC Dial Tone Code (cooked mode) 15 0 E N M D 0000000000 D T C Reset Value 000000000000 0 3 2 1 0 Digit Frequency 0 0 0 0 1 697/1209 0 0 0 1 2 697/1336 0 0 1 0 3 697/1477 0 0 1 1 A 697/1633 0 1 0 0 4 770/1209 0 1 0 1 5 770/1336 0 1 1 0 6 770/1477 0 1 1 1 B 770/1633 1 0 0 0 7 852/1209 1 0 0 1 8 852/1336 1 0 1 0 9 852/1477 1 0 1 1 C 852/1633 1 1 0 0 * 941/1209 1 1 0 1 0 941/1336 1 1 1 0 # 941/1477 1 1 1 1 D 941/1633

Detailed Register Description Semiconductor Group 138 10.97 12h DGF1 DTMF Generator Frequency 1 FRQ Frequency of Generator 1 The parameter FRQ for a given frequency f[Hz] can be calculated by the following formula: 15 0

0 FRQ

Detailed Register Description Semiconductor Group 139 10.97 13h DGF2 DTMF Generator Frequency 2 FRQ Frequency of Generator 2 he parameter FRQ for a given frequency f[Hz] can be calculated by the following formula: 15 0 0F R Q FRQ 32768 f

Detailed Register Description Semiconductor Group 140 10.97 14h DGL DTMF Generator Level LEV2 Signal Level of Generator 2 In order to obtain a signal level L (relative to the PCM maximum value) for generator 2 the value of LEV2 can be calculated according to the following formula: LEV1 Signal Level of Generator 1 In order to obtain a signal level L (relative to the PCM maximum value) for generator 1 the value of LEV1 can be calculated according to the following formula: 15 0

0 LEV2 0 LEV1

LEV2 128 L2 0 d B⁄×10= LEV1 128 L2 0 d B⁄×10=

Detailed Register Description Semiconductor Group 141 10.97 15h DGATT DTMF Generator Attenuation ATT2 Attenuation of Signal S10 In order to obtain attenuation A the parameter ATT2 can be calculated by the formula: ATT1 Attenuation of Signal S9 In order to obtain attenuation A the parameter ATT1 can be calculated by the formula: 15 0 ATT2 ATT1 ATT2 128 1024 A2 0 d B⁄×10+A 1 8 1 d B ,>;

128 A2 0 d B⁄×10 A 18 1 dB ,<;

A2 0 d B⁄×10+A 1 8 1 d B ,>;

Detailed Register Description Semiconductor Group 142 10.97 16h R CNGCTL Calling Tone Control EN Enable 0: CNG unit disabled 1: CNG unit enabled I1 Input Selection for Calling Tone Detector 15 0 E N 0000000000 I 1 Reset Value 00000000000 0

Detailed Register Description Semiconductor Group 143 10.97 17h CNGBT CNG Burst Time TIME Minimum Time for Calling Tone In order to obtain the parameter TIME for a minimum time t the following formula can be used: 15 0

0 TIME

TIME t 0.125 ms⁄=

Detailed Register Description Semiconductor Group 144 10.97 18h CNGLEV CNG Minimal Signal Level MIN Minimum Signal Level for Calling Tone In order to obtain the parameter MIN for a minimum signal level L the following formula can be used: 15 0

00 M I N

MIN 16384 L2 0 d B⁄×10=

Detailed Register Description Semiconductor Group 145 10.97 19h CNGRES CNG Signal Resolution RES Signal Resolution The parameter RES depends on the noise level L as follows: 15 0

1111 R E S

RES 4096– L2 0 d B⁄×10=

Detailed Register Description Semiconductor Group 146 10.97 1A h R ATDCTL0 Alert Tone Detection 0 EN Enable alert tone detection 0: The alert tone detection is disabled 1: The alert tone detection is enabled I1 Input signal selection ATC Alert Tone Code 1) undefined 15 0 E N 00 I 1 000000 A T C Reset Value 000 0 000000 - 1) 1 0 Description 0 0 no tone 0 1 2130 1 0 2750 1 1 2130/2750

Detailed Register Description Semiconductor Group 147 10.97 1B h ATDCTL1 Alert Tone Detection 1 MD Alert tone detection mode 0: Only dual tones will be detected 1: Either dual or single tones will be detected DEV Maximum frequency deviation for alert tone 0: 0.5% 1: 1.1% MIN Minimum level of alert tone signal For a minimum signal level min the parameter MIN is given by the following formula: 15 0 M D 00 D E V 0000 M I N MIN 2560 min 20 dB⁄×10=

Detailed Register Description Semiconductor Group 148 10.97 1C h R CIDCTL0 Caller ID Control 0 EN CID Enable 0: Disabled 1: Enabled I1 Input signal selection DATA Last received data byte 15 0 EN 0 0 I1 DATA Reset Value 000 0 0

Detailed Register Description Semiconductor Group 149 10.97 1D h CIDCTL1 Caller ID Control 1 NMB Minimum Number of Mark Bits NMSS Minimum Number of Mark/Space Sequences MIN Minimum Signal Level for CID Decoder For a minimum signal level min the parameter MIN is given by the following formula: 15 0 NMB NMSS MIN 15 14 13 12 11 10 Description 000000 0 000 1 1 0 111111 6 3 0 9 8 7 6 5 Description 00000 1 00001 1 1 11111 3 1 1 MIN 640 min 20 dB⁄×10=

Detailed Register Description Semiconductor Group 150 10.97 20h R CPTCTL Call Progress Tone Control EN CPT Detector Enable 0: Disabled 1: Enabled MD CPT Mode 0: raw 1: cooked I1 Input signal selection 15 0 E N M D 000000000 I 1 Reset Value 00000000000 0

Detailed Register Description Semiconductor Group 151 10.97 21h CPTTR Call Progress Tone Thresholds NUM Number of Cycles SN Minimal Signal-to-Noise Ratio MIN Minimum Signal Level for CPT Detector 15 0 NUM 0 SN MIN 15 14 13 cooked mode raw mode 0 0 0 reserved 0 0 0 1 2 reserved 1 1 1 8 reserved 11 10 9 8 Description 1111 9 d B 1000 1 2 d B 0100 1 5 d B 0010 1 8 d B 0000 2 2 d B Value Description h -40 dB 85h -42 dB 80h -44 dB 9Ah -46 dB 95h -48 dB 90h -50 dB

Detailed Register Description Semiconductor Group 152 10.97 22h CPTMN CPT Minimum Times MINB Minimum Time for CPT Burst The parameter MINB for a minimal burst time TBmin can be calculated by the following formula: MING Minimum Time for CPT Gap The parameter MING for a minimal burst time TGmin can be calculated by the following formula: 15 0 MINB MING MINB TBmin 32 ms– MING TGmin 32 ms–

Detailed Register Description Semiconductor Group 153 10.97 23h CPTMX CPT Maximum Times MAXB Maximum Time for CPT Burst The parameter MAXB for a maximal burst time of TBmax can be calculated by the following formula: MAXG Maximum Time for CPT Gap The parameter MAXG for a maximal burst time of TGmax can be calculated by the following formula: 15 0 MAXB MAXG MAXB TBmax TBmin– MAXG TGmax TGmin–

Detailed Register Description Semiconductor Group 154 10.97 24h CPTDT CPT Delta Times DIFB Maximum Time Difference between consecutive Bursts The parameter DIFB for a maximal difference of tms of two burst durations can be calculated by the following formula: DIFG Maximum Time Difference between consecutive Gaps The parameter DIFG for a maximal difference of tms of two gap durations can be calculated by the following formula: 15 0 DIFB DIFG DIFB t DIFG t

Detailed Register Description Semiconductor Group 155 10.97 25h R LECCTL Line Echo Cancellation Control EN Enable 0: Disabled 1: Enabled MD Mode 0: Normal 1: Extended I1 Input signal selection for I I2 Input signal selection for I2 15 0 E N M D 0000 I 1 I 2 Reset Value 000000 0 0

Detailed Register Description Semiconductor Group 156 10.97 26h LECLEV Minimal Signal Level for Line Echo Cancellation MIN The parameter MIN for a minimal signal level L (dB) can be calculated by the following formula: 15 0 0M I N MIN 512 96.3 L+()×

Detailed Register Description Semiconductor Group 157 10.97 27h LECATT Externally Provided Attenuation ATT The parameter ATT for an externally provided attenuation A (dB) can be calculated by the following formula: 15 0 0A T T ATT 512 A×

Detailed Register Description Semiconductor Group 158 10.97 28h LECMGN Margin for Double Talk Detection MGN The parameter MGN for a margin of L (dB) can be calculated by the following formula: 15 0 0M G N MGN 512 L×

Detailed Register Description Semiconductor Group 159 10.97 29h R DDCTL DTMF Detector Control EN Enable DTMF tone detection 0: The DTMF detection is disabled 1: The DTMF detection is enabled I1 Input signal selection DTC DTMF Tone Code 1) undefined 15 0 E N 00 I 1 000 D T C Reset Value 0 0 000 0 0 - 1) 4 3 2 1 0 Frequency Digit 1 0 0 0 0 941 / 1633 D 1 0 0 0 1 697 / 1209 1 1 0 0 1 0 697 / 1336 2 1 0 0 1 1 697 / 1477 3 1 0 1 0 0 770 / 1209 4 1 0 1 0 1 770 / 1336 5 1 0 1 1 0 770 / 1477 6 1 0 1 1 1 852 / 1209 7 1 1 0 0 0 852 / 1336 8 1 1 0 0 1 852 / 1477 9 1 1 0 1 0 941 / 1336 0 1 1 0 1 1 941 / 1209 * 1 1 1 0 0 941 / 1477 # 1 1 1 0 1 697 / 1633 A 1 1 1 1 0 770 / 1633 B 1 1 1 1 1 852 / 1633 C

Detailed Register Description Semiconductor Group 160 10.97 2A h DDTW DTMF Detector Signal Twist TWIST Signal twist for DTMF tone In order to obtain a minimal signal twist T the parameter TWIST can be calculated by the following formula: Note: TWIST must be in the range [4096,20480] 15 0 0T W I S T TWIST 32768 0.5 dB T–() 10 dB⁄×10=

Detailed Register Description Semiconductor Group 161 10.97 2B h DDLEV DTMF Detector Minimum Signal Level MIN Minimum Signal Level Note: Values outside the given range are reserved and must not be used. 15 0

1111111111 M I N

Detailed Register Description Semiconductor Group 162 10.97 2Eh R FCFCTL Equalizer Control EN Enable equalizer 0: The equalizer is disabled 1: The equalizer is enabled ADR Coefficient address 15 0 E N 0 A D R 000 I Reset Value 00 0 000 0 13 12 11 10 9 8 Coefficient

000000 A 1

000001 A 2

000010 A 3

000011 A 4

000100 A 5

000101 A 6

000110 A 7

000111 A 8

001000 A 9

001001 B 2

001010 B 3

001011 B 4

001100 B 5

001101 B 6

001111 B 8

010000 B 9

010001 C 1

010010 D 1

010011 D 2

010100 D 3

010101 D 4

Detailed Register Description Semiconductor Group 163 10.97 I1 Input signal selection

010111 D 6

011000 D 7

011001 D 8

011010 D 9

011011 D 1 0

011100 D 1 1

011101 D 1 2

011111 D 1 4

100000 D 1 5

100001 D 1 6

100010 D 1 7

100011 C 2

13 12 11 10 9 8 Coefficient

Detailed Register Description Semiconductor Group 164 10.97 2Fh FCFCOF Equalizer Coefficient Data V Coefficient value For the coefficient A1-A9, B2-B9 and D1-D17 the following formula can be used to calculate V for a coefficient c: For the coefficients C1 and C2 the following formula can be used to calculate V for a coefficient c: 15 0 V V 32768 c ×=; - 1 c 1 <≤ V1 2 8 c×= ; 1 c 256 <≤

Detailed Register Description Semiconductor Group 165 10.97 30h R SCCTL Speech Coder Control EN Enable 0: Disabled 1: Enabled HQ High Quality Mode 0: Long Play Mode 1: High Quality Mode VC Voice Controlled Start of Recording 0: Disabled 1: Enabled I1 Input signal selection (first input) I2 Input signal selection (second input) 15 0 EN HQ VC 0 0 0 I1 I2 Reset Value 000000 0 0

Detailed Register Description Semiconductor Group 166 10.97 31h SCCT2 Speech Coder Control 2 TIME The parameter TIME for a time t ([ms]) can be calculated by the following formula: MIN The parameter MIN for a signal level L ([dB]) can be calculated by the following formula: 15 0 TIME MIN TIME t MIN 16384 L ×10=

Detailed Register Description Semiconductor Group 167 10.97 32h SCCT3 Speech Coder Control 3 LP The parameter LP for a time constant of t ([ms]) can be calculated by the following formula: 15 0

0 L P 00000000

Detailed Register Description Semiconductor Group 168 10.97 34h R SDCTL Speech Decoder Control EN Enable 0: Disabled 1: Enabled SPEED Playback Speed 15 0 E N 000000000000 S P E E D Reset Value 00000000000000 0 1 0 Description 0 0 normal speed 0 1 0.5 times normal speed 1 0 1.5 times normal speed 1 1 2.0 times normal speed

Detailed Register Description Semiconductor Group 169 10.97 38h R AGCCTL AGC Control EN Enable 0: Disabled 1: Enabled I1 Input signal selection for I1 I2 Input signal selection for I2 15 0 E N 00000 I 1 I 2 Reset Value 000000 0 0

Detailed Register Description Semiconductor Group 170 10.97 39h R AGCATT Automatic Gain Control Attenuation ATT The parameter ATT for an attenuation A ([dB]) can be calculated by the following formula: 15 0 ATT Reset Value 0 (-100 dB) ATT 32768 A ×10=

Detailed Register Description Semiconductor Group 171 10.97 3A h AGC1 Automatic Gain Control 1 COM The parameter COM for a signal level L ([dB]) can be calculated by the following formula: AG_INIT In order to obtain an initial gain G ([db]) the parameter AG_INIT can be calculated by the following formula: 15 0 COM AG_INIT COM 128 10+ L6 6 2 2,+ L -42,14 dB<; L4 2 1 4,+ L -42,14 dB>; AG_INIT 128 10+ G1 8 0 6,+ G 6 02 dB,<; G6 0 2,– G 6 02 dB,>;

Detailed Register Description Semiconductor Group 172 10.97 3B h AGC2 Automatic Gain Control 2 SPEEDL The parameter SPEEDL for a multiplication factor M is given by the following formula: SPEEDH The parameter SPEEDH for a multiplication factor M is given by the following formula: 15 0 SPEEDL SPEEDH SPEEDL M SPEEDH M

Detailed Register Description Semiconductor Group 173 10.97 3C h AGC3 Automatic Gain Control 3 MIN The parameter MIN for a gain G ([dB]) can be calculated by the following formula: MAX The parameter MAX for an attenuation A ([dB]) can be calculated by the following formula: 15 0 MIN MAX MIN 128 10+ G1 8 0 6,+ G 6 02 dB,<; G6 0 2,– G 6 02 dB,>; MAX 10 A4 2 1 4,+

Detailed Register Description Semiconductor Group 174 10.97 3D h AGC4 Automatic Gain Control 4 DEC The parameter DEC for a time constant t ([1/ms]) is given by the following formula: LIM The parameter LIM for a signal level L ([dB]) can be calculated by the following formula: 15 0 DEC LIM DEC 256 LIM 128 10+ L9 0 3,+ L 66,22 dB<; L6 6 2 2,+ L 66,22 dB>;

Detailed Register Description Semiconductor Group 175 10.97 3Eh AGC5 Automatic Gain Control 5 LP The parameter LP for a time constant t ([1/ms]) is given by the following formula: 15 0

000000001 L P

Detailed Register Description Semiconductor Group 176 10.97 40h R FCTL File Control MD Mode 0: Audio Mode 1: Binary Mode MS Memory Space 0: R/W Memory 1: Voice Prompt Directory TS Time Stamp 0: no update of RTC1/RTC2 entry of file descriptor 1: RTC1/RTC2 entries are updated by content of RTC1/RTC2 registers. FNO File Number 15 0

0 M D M S T S 0000 F N O

Detailed Register Description Semiconductor Group 177 10.97 41h R FCMD File Command IN Initialize 0: no 1: yes (if CMD=1111) RD Remap Directory 0: no 1: yes ABT Abort Command 0: no 1: abort recompress EIE Enable Immediate Execution 0: disabled (default, always possible) 1: enabled (restricted to certain commands and operating modes) CMD File Command 15 0

0 I N R D 00000 A B T E I E 0 C M D

00001 A c t i v a t e

00011 C u t F i l e

00101 W r i t e D a t a

0 1 0 0 0 Read File Descriptor - User 0 1 0 0 1 Write File Descriptor - User

Detailed Register Description Semiconductor Group 178 10.97 0 1 0 1 0 Read File Descriptor - RTC1 0 1 0 1 1 Read File Descriptor - RTC2 0 1 1 0 0 Read File Descriptor - LEN 0 1 1 0 1 Garbage Collection 0 1 1 1 0 Open Next Free File 0 1 1 1 1 Initialize

10000 D M A R e a d

Detailed Register Description Semiconductor Group 179 10.97 42h R FDATA File Data The FDATA register contains the following information after a memory status command: FREE Free Blocks Number of blocks (1 kByte) currently usable for recording. 15 0 FREE Reset Value

Detailed Register Description Semiconductor Group 180 10.97 43h R FPTR File Pointer 15 0 File Pointer 0 0 0 0 0 Phrase selector Reset Value

Detailed Register Description Semiconductor Group 181 10.97 47h R SPSCTL SPS Control POS Position of Status Register Window MODE Mode of SPS Interface SP1 Direct Control for SPS1 0: SPS 1 set to 0 1: SPS 1 set to 1 SP0 Direct Control for SPS0 0: SPS 0 set to 0 1: SPS 0 set to 1 Note: If mode 1 has been selected prior to power-down, both mode 1 and the values of SP1 and SP0 are retained during power-down and wake-up. Other modes are reset to 0 during power down. 1) undefined 15 0 POS 0 0 0 0 0 0 0 MODE SP1 SP0 Reset Value 0 0000000 0 - 1) -1) 15 14 13 12 SPS 0 SPS 1 0 0 0 0 Bit 0 Bit 1 0 0 0 1 Bit 1 Bit 2 1 1 1 0 Bit 14 Bit 15 4 3 2 Description 0 0 0 Disabled (SPS 0 and SPS1 zero) 0 0 1 Output of SP1 and SP0 1 0 0 Output of speakerphone state 1 0 1 Expanded address output 1 1 0 Output of STATUS register

Detailed Register Description Semiconductor Group 182 10.97 48h R RTC1 Real Time Clock 1 MIN Minutes Number of minutes elapsed in the current hour (0-59). SEC Seconds Number of seconds elapsed in the current minute (0-59). 15 0

0000 M I N S E C

Detailed Register Description Semiconductor Group 183 10.97 49h R RTC2 Real Time Clock 2 DAY Days Number of days elapsed since last reset (0-2047). HR Hours Number of hours elapsed in the current day (0-23). 15 0 DAY HR Reset Value

Detailed Register Description Semiconductor Group 184 10.97 4A h R DOUT0 Data Out (Timeslot 0) DATA Output Data Output data for pins MA0-MA 11 while MA12=1 (only if HWCONFIG1:APP=10). Note: This register cannot be read. 15 0

0000 D A T A

Detailed Register Description Semiconductor Group 185 10.97 4B h R DOUT1 Data Out (Timeslot 1) DATA Output Data Output data for pins MA0-MA 11 while MA13=1 (only if HWCONFIG1:APP=10). Note: This register cannot be read. 15 0

Detailed Register Description Semiconductor Group 186 10.97 4C h R DOUT2 Data Out (Timeslot 2) DATA Output Data Output data for pins MA0-MA 11 while MA14=1 (only if HWCONFIG1:APP=10). Note: This register cannot be read. 15 0

Detailed Register Description Semiconductor Group 187 10.97 4D h R DOUT3 Data Out (Timeslot 3 or Static Mode) DATA Output Data Output data for pins MA0-MA 11 while MA15=1 (only if HWCONFIG1:APP=10). Output data for pins MA0-MA 15 (only if HWCONFIG1:APP=01) Note: This register cannot be read. 15 0 DATA Reset Value

Detailed Register Description Semiconductor Group 188 10.97 4Eh DIN Data In (Timeslot 3 or Static Mode) DATA Input Data Input data for pins MA0-MA 11 at falling edge of MA12 (only if HWCONFIG1:APP=10). Input data for pins MA0-MA 15 (only if HWCONFIG1:APP=01) 15 0 DATA

Detailed Register Description Semiconductor Group 189 10.97 4Fh R DDIR Data Direction (Timeslot 3 or Static Mode) DIR Port Direction Port direction during MA12=1 or in static mode. 0: input 1: output Note: This register cannot be read. 15 0 DIR Reset Value 0 (all inputs)

Detailed Register Description Semiconductor Group 190 10.97 60h R SCTL Speakerphone Control ENS Enable Echo Suppression 0: The echo suppression unit is disabled 1: The echo suppression unit is enabled ENC Enable Echo Cancellation 0: The echo cancellation unit is disabled 1: The echo cancellation unit is enabled MD Mode 0: Speakerphone mode 1: Loudhearing mode SDR Signal Source of SDR 0: after AGCR 1: before AGCR SDX Signal Source of SDX 0: after AGCX 1: before AGCX AGR AGCR Enable 0: AGCR disabled 1: AGCR enabled AGX AGCX Enable 0: AGCX disabled 1: AGCX enabled 15 0 E N S E N C 000000 M D S D R S D X 00 A G R A G X 0 Reset Value 0000000000000000

Detailed Register Description Semiconductor Group 191 10.97 62h R SSRC1 Speakerphone Source 1 I1 Input Signal Selection (Acoustic Source 1) I2 Input Signal Selection (Acoustic Source 2) 15 0

000000 I 1 I 2

Detailed Register Description Semiconductor Group 192 10.97 63h R SSRC2 Speakerphone Source 2 I3 Input Signal Selection (Line Source 1) I4 Input Signal Selection (Line Source 2) 15 0

000000 I 3 I 4

Detailed Register Description Semiconductor Group 193 10.97 64h SSDX1 Speech Detector (Transmit) 1 LP2L The parameter LP2L for a saturation level L (dB) can be calculated by the following formula: LIM The parameter LIM for a minimum signal level L (dB, relative to PCM max. value) can be calculated by the following formula: 15 0

0 LP2L 0 LIM

LP2L 2L× LIM 29 6 . 3 L+()×

Detailed Register Description Semiconductor Group 194 10.97 65h SSDX2 Speech Detector (Transmit) 2 LP1 The parameter LP1 for a time t (ms) can be calculated by the following formula: OFF The parameter OFF for a level offset of O (dB) can be calculated by the following formula: 15 0 LP1 0 OFF LP1 64 t⁄ 0.5 t 64<<; 128 2048 t⁄+ 16.2 t 2048 <<; OFF 2O×

Detailed Register Description Semiconductor Group 195 10.97 66h SSDX3 Speech Detector (Transmit) 3 PDN The parameter PDN for a time t (ms) can be calculated by the following formula: LP2N The parameter LP2N for a time t (ms) can be calculated by the following formula: 15 0 PDN LP2N PDN 64 t⁄ 0.5 t 64<<; 128 2048 t⁄+ 16.2 t 2048 <<; LP2N 64 t⁄ 0.5 t 64<<; 128 2048 t⁄+ 16.2 t 2048 <<;

Detailed Register Description Semiconductor Group 196 10.97 67h SSDX4 Speech Detector (Transmit) 4 PDS The parameter PDS for a time t (ms) can be calculated by the following formula: LP2S The parameter LP2S for a time t (ms) can be calculated by the following formula: 15 0 PDS 0 LP2S PDS 64 t⁄ 0.5 t 64<<; 128 2048 t⁄+ 16.2 t 2048 <<; LP2S 262144

Detailed Register Description Semiconductor Group 197 10.97 68h SSDR1 Speech Detector (Receive) 1 LP2L The parameter LP2L for a saturation level L (dB) can be calculated by the following formula: LIM The parameter LIM for a minimum signal level L (dB, relative to PCM max. value) can be calculated by the following formula: 15 0 LP2L 2L× LIM 29 6 . 3 L+()×

Detailed Register Description Semiconductor Group 198 10.97 69h SSDR2 Speech Detector (Receive) 2 LP1 The parameter LP1 for a time t (ms) can be calculated by the following formula: OFF The parameter OFF for a level offset of O (dB) can be calculated by the following formula: 15 0 LP1 0 OFF LP1 64 t⁄ 0.5 t 64<<; 128 2048 t⁄+ 16.2 t 2048 <<; OFF 2O×

Detailed Register Description Semiconductor Group 199 10.97 6A h SSDR3 Speech Detector (Receive) 3 PDN The parameter PDN for a time t (ms) can be calculated by the following formula: LP2N The parameter LP2N for a time t (ms) can be calculated by the following formula: 15 0 PDN LP2N PDN 64 t⁄ 0.5 t 64<<; 128 2048 t⁄+ 16.2 t 2048 <<; LP2N 64 t⁄ 0.5 t 64<<; 128 2048 t⁄+ 16.2 t 2048 <<;

Detailed Register Description Semiconductor Group 200 10.97 6B h SSDR4 Speech Detector (Receive) 4 PDS The parameter PDS for a time t (ms) can be calculated by the following formula: LP2S The parameter LP2S for a time t (ms) can be calculated by the following formula: 15 0 PDS 0 LP2S PDS 64 t⁄ 0.5 t 64<<; 128 2048 t⁄+ 16.2 t 2048 <<; LP2S 262144

Detailed Register Description Semiconductor Group 201 10.97 6C h SSCAS1 Speech Comparator (Acoustic Side) 1 G The parameter G for a gain A (dB) can be calculated by the following formula: Note:The parameter G is interpreted in two’s complement. ET The parameter ET for a time t (ms) can be calculated by the following formula: 15 0 GE T G 2A× ET t 4---=

Detailed Register Description Semiconductor Group 202 10.97 6D h SSCAS2 Speech Comparator (Acoustic Side) 2 GDN The parameter GDN for a gain G (dB) can be calculated by the following formula: PDN The parameter PDN for a decay rate R (ms/dB) can be calculated by the following formula: 15 0 0G D N P D N GDN 4G× PDN 64 R×

Detailed Register Description Semiconductor Group 203 10.97 6Eh SSCAS3 Speech Comparator (Acoustic Side) 3 GDS The parameter GDS for a gain G (dB) can be calculated by the following formula: PDS The parameter PDS for a decay rate R (ms/dB) can be calculated by the following formula: 15 0

0 GDS PDS

GDS 4G× PDS 64 R×

Detailed Register Description Semiconductor Group 204 10.97 6Fh SSCLS1 Speech Comparator (Line Side) 1 G The parameter G for a gain A (dB) can be calculated by the following formula: Note:The parameter G is interpreted in two’s complement. ET The parameter ET for a time t (ms) can be calculated by the following formula: 15 0 GE T G 2A× ET t 4---=

Detailed Register Description Semiconductor Group 205 10.97 70h SSCLS2 Speech Comparator (Line Side) 2 GDN The parameter GDN for a gain G (dB) can be calculated by the following formula: PDN The parameter PDN for a decay rate R (ms/dB) can be calculated by the following formula: 15 0

0 GDN PDN

GDN 4G× PDN 64 R×

Detailed Register Description Semiconductor Group 206 10.97 71h SSCLS3 Speech Comparator (Line Side) 3 GDS The parameter GDS for a gain G (dB) can be calculated by the following formula: PDS The parameter PDS for a decay rate R (ms/dB) can be calculated by the following formula: 15 0 0G D S P D S GDS 4G× PDS 64 R×

Detailed Register Description Semiconductor Group 207 10.97 72h SATT1 Attenuation Unit 1 ATT The parameter ATT for an attenuation A (dB) can be calculated by the following formula: SW The parameter SW for a switching rate R (ms/dB) can be calculated by the following formula: 15 0 0A T T S W ATT 2A× SW 128 1

Detailed Register Description Semiconductor Group 208 10.97 73h SATT2 Attenuation Unit 2 TW The parameter TW for a time t (ms) can be calculated by the following formula: DS The parameter DS for a decay rate R (ms/dB) can be calculated by the following formula: 15 0 TW DS TW t DS 5l o g 2× R1–×

Detailed Register Description Semiconductor Group 209 10.97 74h SAGX1 Automatic Gain Control (Transmit) 1 AG_INIT The parameter AG_INIT for a gain G (dB) can be calculated by the following formula: This parameter is interpreted in two’s complement. COM The threshold COM for a level L (dB) can be calculated by the following formula: 15 0 AG_INIT 0 COM AG_INIT 2–G × COM 29 6 . 3 L+()×

Detailed Register Description Semiconductor Group 210 10.97 75h SAGX2 Automatic Gain Control (Transmit) 2 AG_ATT The parameter AG_ATT for a gain G (dB) can be calculated by the following formula: SPEEDH The parameter SPEEDH for the regulation speed R (ms/dB) can be calculated by the following formula: The variable D denotes the aberration (dB). 15 0

0 AG_ATT SPEEDH

AG_ATT 2–G × SPEEDH 4096

Detailed Register Description Semiconductor Group 211 10.97 76h SAGX3 Automatic Gain Control (Transmit) 3 AG_GAIN The parameter AG_GAIN for a gain G (dB) can be calculated by the following formula: SPEEDL The parameter COM for a gain G (dB) can be calculated by the following formula: The variable D denotes the aberration (dB). 15 0 AG_GAIN SPEEDL AG_GAIN 2–G × COM 29 6 . 3 G+()×

Detailed Register Description Semiconductor Group 212 10.97 77h SAGX4 Automatic Gain Control (Transmit) 4 NOIS The parameter NOIS for a threshold level L (dB) can be calculated by the following formula: LPA The parameter LPA for a low pass time constant T (mS) can be calculated by the following formula: 15 0

0 NOIS 0 LPA

COM 29 6 . 3 L+()× LPA 16

Detailed Register Description Semiconductor Group 213 10.97 78h SAGX5 Automatic Gain Control (Transmit) 5 AG_CUR The current gain G of the AGC can be derived from the parameter Parameter AG_CUR by the following formula: AG_CUR is interpreted in two’s complement. 15 0 A G _ C U R 00000000 G 5– log2 AG_CUR××

Detailed Register Description Semiconductor Group 214 10.97 79h SAGR1 Automatic Gain Control (Receive) 1 AG_INIT The parameter AG_INIT for a gain G (dB) can be calculated by the following formula: This parameter is interpreted in two’s complement. COM The parameter COM for a threshold L (dB) can be calculated by the following formula: 15 0 AG_INIT 0 COM AG_INIT 2–G × COM 29 6 . 3 L+()×

Detailed Register Description Semiconductor Group 215 10.97 7A h SAGR2 Automatic Gain Control (Receive) 2 AG_ATT The parameter AG_ATT for a gain G (dB) can be calculated by the following formula: SPEEDH The parameter SPEEDH for the regulation speed R (ms/dB) can be calculated by the following formula: The variable D denotes the aberration (dB). 15 0 AG_ATT 2–G × SPEEDH 4096

Detailed Register Description Semiconductor Group 216 10.97 7B h SAGR3 Automatic Gain Control (Receive) 3 AG_GAIN The parameter AG_GAIN for a gain G (dB) can be calculated by the following formula: SPEEDL The parameter SPEEDL for the regulation speed R (ms/dB) can be calculated by the following formula: The variable D denotes the aberration (dB). 15 0 AG_GAIN SPEEDL AG_GAIN 2–G × SPEEDL 4096

Detailed Register Description Semiconductor Group 217 10.97 7C h SAGR4 Automatic Gain Control (Receive) 4 NOIS The parameter NOIS for a threshold level L (dB) can be calculated by the following formula: LPA The parameter LPA for a low pass time constant T (mS) can be calculated by the following formula: 15 0 COM 29 6 . 3 L+()× LPA 16

Detailed Register Description Semiconductor Group 218 10.97 7D h SAGR5 Automatic Gain Control (Receive) 5 AG_CUR The current gain G of the AGC can be derived from the parameter Parameter AG_CUR by the following formula: AG_CUR is interpreted in two’s complement. 15 0 A G _ C U R 00000000 G 5– log2 AG_CUR××

Detailed Register Description Semiconductor Group 219 10.97 7Eh SLGA Line Gain LGAR The parameter LGAR for a gain G (dB) is given by the following formula: LGAX The parameter LGAX for a gain G (dB) is given by the following formula: 15 0

0 LGAR 0 LGAX

LGAR 128 G1 2–() 20⁄×10= LGAX 128 G1 2–() 20⁄×10=

Detailed Register Description Semiconductor Group 220 10.97 80h SAELEN Acoustic Echo Cancellation Length LEN LEN denotes the number of FIR-taps used. 15 0

0000000 L E N

Detailed Register Description Semiconductor Group 221 10.97 81h SAEATT Acoustic Echo Cancellation Double Talk Attenuation ATT The parameter ATT for an attenuation A (dB) is given by the following formula: 15 0 0A T T ATT 512 A×

Detailed Register Description Semiconductor Group 222 10.97 82h SAEGS Acoustic Echo Cancellation Global Scale GS All coefficients of the FIR filter are scaled by a factor C. This factor is given by the following equation: 15 0

0000000000000 G S

C2 GS=

Detailed Register Description Semiconductor Group 223 10.97 83h SAEPS1 Acoustic Echo Cancellation Partial Scale PS The additional scaling coefficient AC is given by the following formula: 15 0

0000000000000 P S

AC 2 PS=

Detailed Register Description Semiconductor Group 224 10.97 84h SAEPS2 Acoustic Echo Cancellation First Block FB The parameter FB denotes the first block that is affected by the partial scaling coefficient. If the partial coefficient is one, FB is disregarded. 15 0

0000000000000 F B

Semiconductor Group 225 10.97

4 Electrical Characteristics

Electrical CharacteristicsElectrical Characteristics

4.1 Absolute Maximum Ratings

ESD integrity (according MIL-Std. 883D, method 3015.7): 2 kV Exception: The pins INT, SDX, DU/DX, DD/DR, SPS0, SPS1 and MD 0-MD 7 are not protected against voltage stress >1 kV. Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

4.2 DC Characteristics

Parameter Symbol Limit Values Unit Ambient temperature under bias TA -20 to 85 °C Storage temperature TSTG – 65 to125 °C Supply Voltage VDD -0.5 to 4.2 V Supply Voltage VDDA -0.5 to 4.2 V Supply Voltage VDDP -0.5 to 6 V Voltage of pin with respect to ground: XTAL 1, XTAL2 VS 0 to VDDA V Voltage on any pin with respect to ground VS If VDDP < 3 V: – 0.4 to VDD + 0.5 If VDDP > 3 V: – 0.4 to VDDP + 0.5 V VDD /VDDA = 3.3 V ± 0.3 V; VDDP = 5 V ± 10%; VSS /VSSA = 0 V; TA = 0 to 70 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max. Input leakage current IIL – 1.0 1.0 µA0 V ≤ VIN ≤ VDD H-input level (except MA0-MA 15, XTAL 1,OSC 1) VIH1 2.0 VDDP + 0.3 V H-input level (OSC1) VIH2 0.8 VDD VDDA + 0.3 V H-input level (MA0-MA 15, MCTL1)) VIH3 2.0 VDD V L-input level (except pins XTAL 1,OSC 1) VIL1 – 0.3 0.8 V

Semiconductor Group 226 10.97 1) MCTL signals are (W /FWE , VPRD/FCLE, RAS/FOE, CAS0/ALE, CAS1/FCS) L-input level (OSC1) VIL2 – 0.3 0.2 VDDA V H-output level (except DU/DX, DD/DR, MA 0-MA 15, SPS0, SPS1, MD 0-MD 7) VOH1 VDD – 0.45 V IO = 2 mA H-output level (SPS0, SPS1, MD0- MD 7, SDX, INT) VOH2 VDD – 0.6 V IO = 2 mA H-output level (MA0-MA 15) VOH3 VDD – 0.45 V IO = 5 mA H-output level (DU/DX, DD/DR)VOH4 VDD – 0.6 V IO = 7 mA L-output level (except DU/DX, DD/DR, MA 0-MA 15) VOL1 0.45 V IO = – 2 mA L-output level (MA0-MA 15) (address mode or APP output) VOL2 0.45 V IO = – 5 mA L-output current (MA0-MA 15) (after reset) ILO 50 150 240 µAR S T = 1 H-output current (MCTL1)) IHO 25 65 120 µAR S T = 1 L-output level (pins DU/DX, DD/ DR) VOL3 0.45 V IO = – 7 mA Internal pullup current (FRDY) ILI 350 750 1300 µA Input capacitance C I 10 pF Output capacitance C O 15 pF VDD supply current (power down, no refresh, no RTC) IDDS1 10 50 µA VDD supply current (power down, refresh, RTC) IDDS2 20 70 µA VDD supply current operating IDDO 55 70 mA VDD = 3.3 V VDDP supply current IDDP 11 0 µA VDD /VDDA = 3.3 V ± 0.3 V; VDDP = 5 V ± 10%; VSS /VSSA = 0 V; TA = 0 to 70 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 227 10.97

4.3 AC Characteristics

Digital inputs are driven to 2.4 V for a logical “1” and to 0.45 V for a logical “0”. Timing measurements are made at 2.0 V for a logical “1” and 0.8 V for a logical “0”. The AC- testing input/output waveforms are shown below. Figure 69 Input/Output Waveforms for AC-Tests

Semiconductor Group 228 10.97 DTMF Detector Parameter Symbol Limit Values Unit Test Condition min. typ. max. Frequency deviation accept -1.5 1.5 % Frequency deviation reject 3.5 -3.5 % Acceptance level -45 0 dB rel. to max. PCM Rejection level -50 dB rel. to max. PCM Twist deviation accept +/-2 +/-8 dB programmable Noise Tolerance 12 dB Signal duration accept 40 ms Signal duration reject 23 ms Gap duration accept 18 ms CPT Detector Parameter Symbol Limit Values Unit Test Condition min. typ. max. Frequency acceptance range 300 640 Hz Frequency rejection range 800 200 Hz Acceptance level -45 0 dB rel. to max. PCM Rejection level -50 dB rel. to max. PCM Signal duration accept 50 ms programmable Signal duration reject 10 ms Caller ID Decoder Parameter Symbol Limit Values Unit Test Condition min. typ. max. Frequency deviation accept -2 2 % Acceptance level -45 0 dB rel. to max. PCM Transmission rate 1188 1200 1212 baud Noise Tolerance -12 dB

Semiconductor Group 229 10.97 Alert Tone Detector Parameter Symbol Limit Values Unit Test Condition min. typ. max. Frequency deviation accept -0.5 0.5 % ATDCTL1:DEV=0 Frequency deviation accept -1.1 1.1 % ATDCTL1:DEV=1 Frequency deviation reject 3.5 -3.5 % Acceptance level -40 0 dB rel. to max. PCM Rejection level -5 dB rel. to acceptance level Twist deviation accept +/-7 dB Noise Tolerance 20 dB Signal duration accept 75 ms Gap duration accept 40 ms CNG Detector Parameter Symbol Limit Values Unit Test Condition min. typ. max. Frequency deviation accept -40 40 Hz Frequency deviation reject -50 50 Hz Acceptance level -45 0 dB SNR >10 dB Acceptance level -50 0 dB SNR >15 dB Rejection level -3 dB dB rel. to CNGLEV:MIN Signal duration reject -1 % rel. to CNGBT:TIME

Semiconductor Group 230 10.97 Status Register Update Time The individual bits of the STATUS register may change due to an event (like a recognized DTMF tone) or a command. The timing can be divided into four classes With these definitions the timing of the individual bits in the STATUS register can be given as shown in table: 1) one FSC period 1) up to 30 ms if command is either SDCTL:EN=1 or SCCTL:EN=1 Timing Diagrams Table 87 Status Register Update Timing Class Timing Comment Min. Max. I 0 0 Immediately after command has been issued A 0 125 µs1) Command has been accepted D1 2 5 µS 250 µs Deactivation time after command has been issued E - - Associated event has happened Bit RDY ABT CIA CD CPT CNG SD ERR BSY DTV ATV 0->1 AEEEEEEE A 1) EE 1->0 I A A,D E,D E,D D E,D A E E,D E,D

Semiconductor Group 231 10.97 Figure 70 Oscillator Circuits Recommended Values Oscillator Circuits Value Unit Min Typ Max Load CL1 40 pF Static capacitance X1 5p F Motional capacitance X1 17 fF Resonance resistor X1 60 Ω Load CL2 30 pF Static Capacitance X2 1.7 pF Motional capacitance X2 3.5 fF Resonance resistor X2 18 40 k Ω Frequency deviation 100 ppm XTAL 1 XTAL 2 C L1 C L1 OSC 1 OSC 2 C L2 C L2

Semiconductor Group 233 10.97 Input data hold t5 20 ns Output data from high impedance to active (FSC high or other than first timeslot) t6 30 ns Output data from active to high impedancet7 30 ns Output data delay from clock t8 30 ns FSC setup t9 40 ns FSC hold t10 40 ns FSC jitter (deviation per frame) -200 200 ns Parameter SSDI/IOM® -2 Interface Symbol Limit values Unit Min Max

Semiconductor Group 234 10.97 Figure 73 SSDI Interface - Strobe Timing Parameter SSDI Interface Symbol Limit values Unit Min Max DXST delay t1 20 ns DRST inactive setup t2 20 ns DRST inactive hold t3 20 ns DRST active setup t4 20 ns DRST active hold t5 20 ns FSC setup t6 8 DCL cycles FSC hold t7 40 ns DRST DCL t4 t5t2 t3 FSC t6 t7 DXST

Semiconductor Group 235 10.97 Figure 74 Serial Control Interface Parameter SCI Interface Symbol Limit values Unit Min Max SCLK cycle time t1 500 ns SCLK high time t2 100 ns SCLK low time t3 100 ns CS setup time t4 40 ns CS hold time t5 10 ns SDR setup time t6 40 ns SDR hold time t7 40 ns SDX data out delay t8 80 ns CS high to SDX tristate t9 40 ns SCLK to SDX active t10 80 ns SCLK to SDX tristate t11 40 ns CS to INT delay t12 80 ns CS SCLK SDR SDX INT t4 t2 t3 t12 t10 t11 t6 t7

Semiconductor Group 236 10.97 Figure 75 Analog Front End Interface Parameter AFE Interface Symbol Limit values Unit Min Max AFECLK period t1 125 165 ns AFECLK high t2 21 / f XTAL AFECLK low t3 21 / f XTAL AFEDU setup t4 20 ns AFEDU hold t5 20 ns AFEDD output delay t6 30 ns AFEFS output delay t7 30 ns AFEDU AFECLK AFEDD bit n bit n+1 AFEFS t7t7

Semiconductor Group 237 10.97 Figure 76 Memory Interface - DRAM Read Access Parameter Memory Interface - DRAM Read Access Symbol Limit values Unit Min Max row address setup time t1 50 ns row address hold time t2 50 ns column address setup time t3 50 ns RAS precharge time t4 110 ns RAS to CAS delay t5 110 2000 ns CAS pulse width t6 110 2000 ns Data input setup time t7 40 ns Data input hold time t8 0n s MA 0-MA 13 MD 0-MD 7 CAS 0,CAS1 RAS row addr. col. addr. t1 t2 t7 t8

Semiconductor Group 238 10.97 Figure 77 Memory Interface - DRAM Write Access Parameter Memory Interface - DRAM Write Access Symbol Limit values Unit Min Max row address setup time t1 50 ns row address hold time t2 50 ns column address setup time t3 50 ns RAS precharge time t4 110 ns RAS to CAS delay t5 110 2000 ns CAS pulse width t6 110 2000 ns Data output setup time t7 100 ns Data output hold time t8 50 ns RAS to W delay t9 50 ns W to CAS setup t10 50 ns MA 0-MA 13 MD 0-MD 7 CAS 0,CAS1 RAS row addr. col. addr. t1 t2 t7 t8 W t9 t10

Semiconductor Group 239 10.97 Figure 78 Memory Interface - DRAM Refresh Cycle Note: The frequency of the DRAM refresh cycle depends on the selected mode. In active mode or normal refresh mode (during power down) the minimal frequency is 64 kHz. In battery backup mode, the refresh frequency is 8 kHz. Parameter Memory Interface - DRAM Refresh Cycle Symbol Limit values Unit Min Max RAS precharge time t1 100 ns RAS low time t2 200 5000 ns CAS setup t3 100 ns CAS hold t4 100 ns CAS 0,CAS1 RAS t1 t2

Semiconductor Group 240 10.97 Figure 79 Memory Interface - EPROM Read Parameter Memory Interface - EPROM Read Symbol Limit values Unit Min Max Address setup before VPRD t1 110 ns VPRD low time t2 500 ns Data setup time t3 40 ns Data hold time t4 0n s MA 0-MA 15 MD 0-MD 7 VPRD linear address t1 t2 t3 t4

Semiconductor Group 241 10.97 Figure 80 Memory Interface - Samsung Command Write Note: FCS stays low if other cycles follow for the same access. Parameter Memory Interface - Samsung Command Write Symbol Limit values Unit Min Max Address setup before FCS, FCLE t1 100 ns FCS low time, FCLE high time t2 400 ns FWR hold after FCLE rising t3 100 ns FWR low time t4 200 ns FWR setup before FCLE falling t5 100 ns Data setup time t6 200 ns Data hold time t7 50 ns MA 0-MA 11 MD 0-MD 7 FCS (FCS0-FCS3) A16-A23 and FCS0-FCS3 FWR FCLE t3 t4 t5 t6 t7

Semiconductor Group 242 10.97 Figure 81 Memory Interface - Samsung Address Write Parameter Memory Interface - Samsung Address Write Symbol Limit values Unit Min Max ALE high time t1 400 ns FWR hold after ALE rising t2 100 ns FWR low time t3 200 ns FWR setup before ALE falling t4 100 ns Data setup time t5 200 ns Data hold time t6 50 ns MD 0-MD 7 FWR ALE t2 t3 t4 t5 t6

Semiconductor Group 243 10.97 Figure 82 Memory Interface - Samsung Data Write Parameter Memory Interface - Samsung Data Write Symbol Limit values Unit Min Max FWR low time t1 200 ns Data setup time t2 200 ns Data hold time t3 50 ns MD 0-MD 7 FWR t2 t3

Semiconductor Group 244 10.97 Figure 83 Memory Interface - Samsung Data Read Parameter Memory Interface - Samsung Data Read Symbol Limit values Unit Min Max FOE low time t1 200 ns Data setup time t2 40 ns Data hold time t3 0n s MD 0-MD 7 FOE t2 t3

Semiconductor Group 245 10.97 Figure 84 Auxiliary Parallel Port - Multiplex Mode Parameter Auxiliary Port Interface - Multiplex Mode Symbol Limit values Unit Min Typ Max Active time (MA0-MA 15) t1 2m s Gap time (MA0-MA 15) t2 125 µs Data setup time t3 50 ns Data hold time t4 0n s MA 0-MA 11 MA 12 t3 t4 t1 t2 MA 13

Semiconductor Group 246 10.97 Figure 85 Reset Timing Parameter Reset Timing Symbol Limit values Unit Min Max VDD /VDDP /VDDA rise time 5%-95% t1 20 ms Supply voltages stable to RST high t2 0n s Supply voltages stable to RST low t3 0.1 ms RST high time t4 1000 ns RST VDD /VDDP t2 t4

Semiconductor Group 247 10.97

5 Package Outlines

Plastic Package, P-MQFP-80 (SMD) (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device

Semiconductor Group 248 10.97 PSB 4860 Index A Abort Clearing Event 82, 119 Functional Description 81 Status Bit 109 Alert Tone Detector Electrical Characteristics 229 Functional Description 46 Registers 146–147 Status Bit 110 Analog Front End Interface Electrical Characteristics 236 Functional Description 55 Registers 122–128 Timing 92 ARAM see Memory Interface Automatic Gain Control Functional Description 59 Registers 169–175 Auxiliary Parallel Port Electrical Characteristics 245 Mode Bits 112 Multiplex Mode 107 Registers 184–189 Static Mode 107 C Caller ID Decoder Electrical Characteristics 228 Functional Description 49 Registers 148–149 Status Bits 109 CNG Detector Electrical Characteristics 229 Functional Description 45 Registers 142–145 Status Bit 110 CPT Detector Electrical Characteristics 228 Functional Description 47 Registers 150–154 Status Bit 110 D Digital Interface Functional Description 56 Mode Bits 112 Registers 129–135 DRAM see Memory Interface DTMF Detector Electrical Characteristics 228 Functional Description 44 Registers 159–161 Status Bit 110 DTMF Generator Functional Description 51 Registers 137–141 E EPROM see Memory Interface Equalizer Functional Description 61 Registers 162–164 Execution Times File Commands 77 F File Commands Access File Descriptor 72 Compress 71 Create Next New 69 Delete 71

Semiconductor Group 249 10.97 PSB 4860 Index Execution Times 77 New File 69 Open 69 Read Binary Data 73 Registers 176–180 Restrictions 78 Seek 70 Status Bits 110 Tailcut 71 Write Binary Data 74 Type Audio 64 Binary 64 Phrase 65 User Data Word 66 Flash Memory see Memory Interface G Group Listening 38 H Hardware Configuration Functional Description 82 Registers 111 I Interrupt Functional Description 80 Pin Configuration 111 Register 121 IOM®-2 Interface Electrical Characteristics 232–233 Functional Description 86 see also: Digital Interface L Line Echo Canceller Functional Description 42 Registers 155–158 Loudhearing 38 M Memory Interface ARAM/DRAM Connection Diagram 99 Electrical Characteristics 237–239 Refresh 101, 113 Timing 100 EPROM Connection Diagram 102 Electrical Characteristics 240 Timing 102 Flash Connection Diagram 103 Electrical Characteristics 241–244 In-Circuit Programming 98, 113 Multiple Devices 104 Timing 105 Register 120 Supported Devices 98 Memory Management Activation 68 Directories 63 ExecutionTimes 77 Files 64 Garbage Collection 72 Initialization 67 Memory Status 72 Overview 63 Status 65 O Oscillator Electrical Characteristics 231 Mode Bits 112 P Power Down Functional Description 79

Semiconductor Group 250 10.97 PSB 4860 Index Status Bit 111 R Real Time Clock Configuration Bits 111 Functional Description 79 Oscillator 231 Registers 182–183 Recompression 71 Reset Electrical Characteristics 246 Functional Description 79 Register Values 115 Restrictions File Commands 78 Modules 83 Revision Functional Description 82 Register 119 S Serial Control Interface Command Opcodes 97 Electrical Characteristics 235 Functional Description 94 Signals Encoding 117 Reference Table 117 Speakerphone Functional Description Automatic Gain Control 38 Control 37 Echo Cancellation 28 Echo Suppression 30 Overview 27 Speech Comparator 35 Speech Detector 32 Registers 190–223 Speech Coder Functional Description 52 Registers 165–167 Speech Decoder Functional Description 54 Register 168 SPS Outputs Functional Description 38, 79 Register 181 SSDI Interface Electrical Characteristics 232–234 Functional Description 90 see also: Digital Interface Status Register Definition 109 Update Timing 230 U Universal Attenuator Functional Description 58 Register 136