PSB2120

PSB2120 SIEMENS | Alldatasheet

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Technical content

Features

l Switched mode DC/DC-converter l Switched mode DC/DC-converter l CCITT (I.430) ISDN compatible l Integrated 200 V power FET (only PSB 2120-P in P-DIP-22) l Low power dissipation l Supply voltage range 10 V to 60 V l Input undervoltage detection l Programmable overcurrent protection l Soft start l Control circuit to achieve minimum start-up current l Power housekeeping input l Oscillator synchronization input/output l Polarity reversal detection l High voltage CMOS-technology 60 V Semiconductor Group 3 12.92

(top view) PSB 2120

Pin Definitions and Functions Pin No. P-DSO Pin No. P-DIP Symbol Input (I) Output (O) Definition Function 1 1 SYNC I/O Synchronization Input for synchronization of the oscillator to an external frequency, or output to synchronize multiple devices. 2 2 RC I RC-Oscillator The external timing components of the ramp generator are attached to this pin. 3 3 COMP O Compensation Error amplifier output and Pulse W idthM odulator (PWM) input for loop stabilization network. VP I Positive Voltage Sense Non-inverting input of the error amplifier.

55 VN I Negative Voltage

Inverting input of the error amplifier.

66 C SS I Soft Start

The capacitor at this pin determines the soft-start characteristic.

77 EME O Emergency A low input voltage at POL will

activate the outputEME. 8 8 POL I Polarity Detection POL is the input to a non inverting Schmitt-trigger. 11 9 GA O Gate Output of the FET-driver. N.C. 10 DR O Drain Drain connection of the power FET. N.C. 11 SO O Source Source connection of the power FET. 14 12 C IN I Input Capacitor C IN has to be connected to the input buffer-capacitor and a current limiting charging-resistor.

Pin Definitions and Functions (cont’d) Pin No. P-DSO Pin No. P-DIP Symbol Input (I) Output (O) Definition Function 15 13 ENA I Enable A high input voltage at this pin will stop the IRPC-function. 16 14 CO O Comparator output Connections of the universal usable comparator. 17 15 CN I Comparator neg. input 18 16 CP I Comparator pos. input 19 17 GND I Ground All analog and digital signals are referred to this pin. 20 18 VEXT I/O External supply Output of the internal CMOS-supply. ViaVEXT the internal CMOS-circuits can be supplied from an external DC-supply in order to reduce chip power dissipation. 21 19 IN I Negative current sense When the voltage difference between these two pins exceeds 100 mV, the digital current limiting becomes active. 22 20 IP I Positive current sense 23 21 VREF O Reference voltage Output of the 4.0 V reference voltage. 24 22 VS I Supply voltage VBAT is the positive input voltage. PSB 2120

The reference provides a 4.0 V voltage for the regulation loop. A high gain error amplifier compares the reference voltage with the switch mode supply output voltage. The output of the error amplifier is compared with a periodic linear ramp, which is generated by the sawtooth-oscillator circuit. The comparator output is a fixed-frequency, variable pulse width logic signal, which passes through logic circuits to the high voltage power-switching-FET. A digital current limiting device suppresses the PWM logic signal when the voltage difference at the current limit sense input reaches 100 mV. In this case the control logic inhibits double pulses during one oscillator period. Start-Up Procedure Before the switched-mode DC/DC-converter starts, a sequence of several conditions has to be passed in order to avoid any system malfunction. The primary undervoltage detection inhibits the converter function. This insures that all control functions have stabilized in the proper state when the turn on voltage (ca. 10 V) is reached, and it prevents start-up glitches. In case of connecting the TE to powered lines or if a line is powered up, the charge current of the primary buffer capacitor is limited by an external resistor (figure 2). This resistor is short-circuited by the PSB 2120 when the voltage drop across it falls below approximately 2.0 V. The residual resistance of this short-circuit is about 3 W. In case of a primary undervoltage detection the short-circuit will be always deactivated. So, the DC/DC-converter does not start until the charging of the primary buffer capacitor is completed, and the maximum line input voltage is reached. If this feature is not desired, C IN has to be connected to GND. In this case the primary current measuring circuit turns off, to reduce chip-power dissipation from 9 mW to 6 mW. In order to avoid high current peaks during the charging of the secondary capacitors or line capacitors in case of supplying an S-interface, a soft start circuit is implemented in the PSB 2120. This circuit requires an external capacitor, connected between C SS and GND. In addition, the enable input (ENA) allows an external switch-on/switch-off control. If the DC/DC- converter is disabled viaENA, the soft-start-capacitor at pinC SS is discharged. This input can also be used for several other functions, e.g. secondary overvoltage protection. PSB 2120

The PSB 2120 contains a SIPMOS-transistor for power handling. Non-isolated and isolated SMPS- configurations are possible. Logic and analog circuits are implemented in CMOS in order to achieve low power dissipation. The error amplifier compares the sensed voltage with a reference attached to VP and thus controls the Pulse Width Modulator (PWM). The conversion frequency is generated by a sawtooth oscillator which can be controlled by external RC-components (figure 4) or by an external synchronization signal. The PSB 2120 is synchronized by the rising edge of the sync signal, whose frequency must be 10 % higher than the free run frequency, determined by the RC-components. The SYNC-pin can also be used as a trigger-output. As long as the capacitor of the sawtooth oscillator is discharged, SYNC is high. The output of the PWM is processed by the control logic and fed to the SIPMOS-transistor. The control logic suppresses higher oscillations of the regulation loop caused e.g. in case of current limit detection.

Emergency conditions are signaled to the TE by the reversed polarity of the line feeding voltage. When polarity reversal is detected via pin POL of the PSB 2120, emergency conditions are signaled to the microprocessor via pin EME, which should shut down all activity except simple telephony functions to minimize power dissipation. The polarity detection circuit can also be used for other detection or protection-functions, e.g. programmable primary undervoltage detection. Power Housekeeping An integrated 6 V linear voltage regulator supplies the internal circuits during the start-up phase. Power dissipation of this regulator can be reduced, if an auxiliary winding of the transformer or an external supply is used for that purpose by connecting it to VEXT . If the input voltage atVEXT reaches 6.2 V the internal linear voltage regulator turns off and the internal circuits are fed from this external voltage. In this case the input current at VEXT is approx. 0.5 mA. Note: An internal 7.5 V Zener-diode protects theVEXT input against overvoltages. The maximum Zener-current is 2 mA! If the external supply isn’t stabilized, the input current must be limited (e.g. by a resistor)! Interface to Microprocessor The PSB 2120 offers two TTL-compatible signals: EME and CO. The EME (Emergency-output) becomes active, if polarity reversal is detected. CO is the output of a universal usable comparator; e.g.: to generate a microprocessor-reset signal. PSB 2120

Switching Frequency as a Function ofR T andC T Switching Frequency

PSB 2120 Minimum Configuration PSB 2120

Advanced IRPC-Application with Power Housekeeping and Polarity Reversal Detection

Generation of amP-Reset Signal with the PSB 2120 According to the application infigure 5 and an output power of 500 mW, t1 will be 400 ms andt2 50 ms. PSB 2120

PSB 2120 in Flyback Configuration with Transformer Isolation

PSB 2120 in Flyback Configuration with Opto Isolation PSB 2120

Absolute Maximum Ratings (All pin references made for P-DIP-22) MOS-Handling: The integrated SIPMOS-transistor (pin 9, 10 and 11) has to be protected against electrostatic charges. The input gate-source (pin 9 and pin 11) must be protected against– 10 V. DC Characteristics TA = 0 to 70 ˚C,VS = 11 to 60 V Parameter Symbol Limit Values Unit Supply voltage DR (pin 10) referred to S0 (pin 11)VS 200 V Continuous drain current (pin 10) IDR 350 mA Supply voltageVBAT (pin 22) referred to GND VBAT 60 V Analog/digital input voltage referred to GND VI A/D 6V Reference output current (pin 21) IO REF – 5 mA VEXT input Z-current II Z 2m A VEXT output current IO – 5 mA SYNC-output current (pin 1) IO SYNC – 5 mA Driver output current (pin 9) IO DR – 5 mA Ambient temperature under bias TA – 25 to 85 ˚C Storage temperature Tstg – 40 to 125 ˚C Thermal resistance junction – ambient Tj 50 K/W Parameter Symbol Limit Values Unit Test Condition min. typ. max. ReferenceV REF TA = 25 ˚C Output voltage VREF O 3.92 4.0 4.08 V IL = 0 mA, VS = 40 V Line regulation VREF Line 60 mV VS = 20 to 60 V, IL = 0 mA, Load regulation VREF Load 20 40 mV IL = 0.1 to 0.3 mA, VS = 40 V Temperature stability VREF TS 25 mV Load current IREF Load 0.5 mA

DC Characteristics (cont’d) Parameter Symbol Limit Values Unit Test Condition min. typ. max. Oscillator SYNC(pin1), RC(pin 2) fOSC = 20 kHz,R T 39 kW– 1 %,C T= 1 nF– 1 %,TA = 25 ˚C Initial accuracy – 10 % Voltage stability offOSC 13% Temperature stability offOSC 5% Max. frequency fmax 180 250 kHz RT = 27 kW C T = 39 pF H-sawtooth voltage VH 3.0 3.2 3.4 V L-sawtooth voltage VL 1.6 1.8 2.0 V H-sync output level VOH 2.4 3.5 5.25 V IL = 0.5 mA VS EXT £ 6.3 V L-sync output level VOL 0.2 0.8 V IL = 20mA Error Amplifier COMP (pin 3),V P (pin 4),V N (pin 5) Input offset voltage VIO 31 0 m V VCM = 3.0 V Input current II 02 5 n A Common mode range VC 1.8 4.0 V VOFFSET = – 15 mV DC open loop gain G VO 60 70 dB Common mode rejection kCMR 60 70 dB Unit gain bandwidth f 0.5 1 MHz C L (pin) 10 pF Supply voltage rejection 60 70 dB H-output voltage VOH 4 5.5 V IL = 100mA L-output voltage VOL 0.02 V IL = 10mA Current Limit ComparatorIP (pin 20),IN (pin 19) TA = 25 ˚C Sense voltage VSense 85 100 115 mV VS = 40 V Input current II 0 100 nA Input voltage range VI 01 V Response time to signal at GA (pin 9) tRes 12 ms IN = 0 V IP = 0 fi 200 mV PSB 2120

DC Characteristics (cont’d) Parameter Symbol Limit Values Unit Test Condition min. typ. max. Pulse Width Modulator Duty cycle td 05 0 % Undervoltage Detection Start-up threshold VUV St 8.1 10 11 V Threshold hysteresis VUV Hy 0.3 V Soft StartC SS (pin 6) Charging current IC 248 mA Output Driver GA(pin 9) TA = 25 ˚C,C L =C GS – Power FET H-output voltage VOH 4.5 V ISource = 5 mA H-output voltage VOH V EXT V ISource = 0 mA L-output voltage VOL 0.3 0.4 V ISink = 5 mA Rise time tr 130 200 ns V EXT = 6.3 V Fall time tf 70 200 ns V EXT = 6.3 V Output current IO 5m A External SupplyV EXT (pin 18) Output voltage VO 5.8 V Output current IO 2m A Input voltage VI 6.0 7.5 V Z-current IZ 2m A Enable InputENA (pin 13) H-input voltage VIH 2.0 5.25 V L-input voltage VIL 0.8 V Response time to signal at GA (pin 9) tRes 0.5 1 ms TA = 25 ˚C H-input current IIH 0.2 2.5 20 mA

DC Characteristics (cont’d) Parameter Symbol Limit Values Unit Test Condition min. typ. max. Comparator CN (pin 15), CP (pin 16),TA = 25 ˚C Input offset voltage VIO 31 0 m V VCM = 3 V Input bias current II 02 5 n A Input voltage range VI 1.8 4.5 V Response time to signal at CO (pin 14) tRes 0.2 1 ms Short CircuitG I (pin 12),TA = 25 ˚C Sense voltage VSense 123V (VS – VCIN) RDS (on) 34 W Polarity Detection POL(pin 8),EME (pin 7) H-input voltage VIH 2.0 5.25 V L-input voltage VIL 0.8 V H-input current IIH 0.1 1 10 mA Response time to signal atEME (pin 7) tRes 0.2 1 ms Digital OutputsEME (pin 7),CO (pin 14) IOUT = 0.5 mA H-output voltage VOH 2.4 3.5 5.25 V V EXT £ 6.3 V L-input voltage VIL 0.2 0.4 V Power FET GA (pin 9), DR (pin 10), SO (pin 11) RDS (on) 46 W ID = 300 mA ton td (on) 55 150 ns toff td (off) 110 200 ns Leakage current ILeak 200 nA VDS = 110 V Power consumption Ptot 91 0 m A VS = 40 V fOSC = 20 kHz V EXT = 6.3 – 6.7 V C GS 200 pF PSB 2120