PSB2110 SIEMENS | Alldatasheet
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ISDN Terminal Adapter Circuit PSB 2110 (ITAC®)
1 Features CMOS IC
‘© Support of async and sync interfaces (X21, X.21 bis, V.24, RS232C, V.35) ‘@ Modem control lines @ Programmable baud rates Protocol Support ue fs © Bit rate adaptation according to X.30, V.110, VPC 05102 ECMA.102 @ USART and HDLC controller to support V.120 PL-CC-44 and DMI applications ‘@ Support of V.120 protocol sensetive and bit transparent mode O @ Hayes modem protocol support sy @ in-band parameter exchange and signaling support oe. mit Synchronous Network Interface Ge 1 i a i © Supports SSI- and IOM®-2-interface for Basic INS5 Rate applications 1 ‘© Supports time-slot oriented interface Yro osees (up to64-time slots) P-DIP-40 @ Supports PCM30- and PCM24-interface for Primary Rate applications @ 1OM-2 MONITOR channel controller Microprocessor Interface @ Siemens/Intel multiplexed microprocessor interface ‘@ DMA support for USART or HDLC controller Power Supply @ Single +5 V supply @ Low power CMOS technology @ Power down (standby) mode Type Version Ordering Code Package PSB 2110-N {V2.2 Q67100-H6293 P-LCC-44 (SMD) pSBa0P |v22 |[Q67100-H6294 | P-DIP-40. 7 03.92
Features
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a 1.1. Pin Definitions and Functions Pin No. |Pin No. Symbol Input (1) ~ | Function P-LCC | P-DIP ‘Output (0) ee ee ae ‘Open Drain (OD) 14 13 ADO vO Multiplexed Address/Data Bus. 13 12 AD1 vo Transfers addresses and data be-
12 Bal AD2 vO tween the microprocessor and the
W 10 AD3 vO ITAC. 10 9 AD4 vo g 8 ADS vo 8 7 AD6 vO | 7 6 AD7 vo 16 cs 1 [Chip Select. A low level on this line selects the ITAC for a read/ | write operation. 19 17 I Write. A low level on this line indi- cates a write operation to the (TAC. 18 16 RD I Read. A low level on this line indi- | cates a read operation from the ee ee ___| Tae. 21 19 INT oD Interrupt Request. This signal is active (low) while the ITAC indi- jcates an interrupt to the micropro- cessor. It is an open drain output —fandtevel active. 20 ALE I Address Latch Enable. A transi- tion from high to low latches the contents of the AD1-AD6 lines and | use them as the address. 6 pMiR. |O. | DMA Input Request. A high level on this line indicates a request for | a DMA transfer from memory to the | ITAG. It is released by a write oper- ation to one of the corresponding | FIFO-addresses. 5 4 | DMOR fe) DMA Output Request. A high level on this line indicates a re- | quest for a DMA transfer from the ITAC to memory. It is released by a | read operation to one of the corre- L sponding FIFO-addresses. Siemens Aktiengeselischaft 9
Pin Definitions and Functions (cont'd) Pin No. |PinNo. |Symbot Input (1) Function P-LCC |P-DIP Output (0) Open Drain (OD) 2 2 BACKT T DMA Input Acknowledge. A low level on this line indicates an ac- knowledgement to a DMA Input Re- | quest. It will select the correspond- ing FIFO address-space. It will also return the DMIR output to a low level. 1 1 DACKO: I DMA Output Acknowledge. A low llevel on this line indicates an ac- knowledgement to a DMA Output Request. It will select the corre- sponding FIFO address-space. It will also return the DMOR output to a low level. 3 3 EODR fe) End of DMA Request. A low level on this line indicates the end of a DMA transfer. It will go active only for HDLC reception after the last . byte of a frame has been read. 15 14 RST I Reset. A low level of at least 2 us will reset the ITAC.
27 SDX/DU o/oD Synchronous Data Transmit/
Data Upstream. Transmit data out- _ put to the network interface.
25 SDR/DD I Synchronous Data Receive/Data
Downstream. Receive data input from the network interface. 24 CLK/DCL |I Clock/Data Clock. Clock signal on the network interface. 23 FSC I Frame Syne. 8-kHz signal which indicates the start of a new frame on the network interface. 37 34 TxD I Transmit Data from the Termi- nal. This line is the data input to the LITAC. 38 35 RxD fe) Receive Data to the Terminal. This line is the data output from the ITAC. ‘Siemens Aktiengeselischatt 10
Pin Definitions and Functions (cont'd) PinNo. |PinNo. [Symbol |input()—*([Function = P-LCC |P-DIP Output (0) Open Drain (OD) 36 33 Ss o/0D S Clock. Bit element timing for the synchronous DCE interface. Data is clocked off on the RxD pin on the | falling edge of S. Data on the TxD | pin is latched on the rising edge of | S. It is tristate for async DCE inter- 34 \\31 DTRIC I Data Terminal Ready/Control. | Data Terminal Ready (108) inter- change circuit if V.24 interface is selected. Control interchange cir- _louitt x21 interface is selected.
29 DCD/I o/0D Data Channel Received Line Sig-
nal Detector Carrier Detect/Indi- cate. DCD (109) interchange cir- cuit if V.24 interface is selected. In- |cicate interchange fine if X.21 interface is selected. ee 40 RTS 1 Request to Send. RTS (105) inter- change circuit if V.24 interface is ee selected. _ ae 35 32 cts o/OoD Clear to Send. CTS (106) inter- change circuit if V.24 interface is = _ _ ee | 28 25 DSR o/0D Data Set Ready. DSR (107) inter- change circuit if V.24 interface is _ selected. 43, 39 Mit Multifunctional Input 1-3. General 42 38 Mi2 purpose inputs if V.24 interface is 4 37 MI3 selected. _ 32 o/oD Multifunctional Output 1-2. 33 o/oD General purpose outputs if V.24 in- __| terface is selected, 31 28 XTAL1 I Crystal 1. Connection for the exter- jral crystal or input for external a ___etock generator, Siemens Aktiengesellschaft 1
Pin Definitions and Functions (cont'd) . Pin No. |Pin No. Input (1) Function P-LCC |P-DIP Output (0) Open Drain (OD) 30 27 XTAL2 Crystal 2. Connection for the ex- ternal crystal. Not connected when external clock generator is used. 22 20 Vss I Power supply ground (GND) Siemens Aktiengeselischaft 12
1.2 Functional Description
4.2.1 General Functions and Device Architecture
Figure 1 shows the block diagram of the ITAC. Figure 1 Block Diagram User Injermediate hw Rote Role Asyre Intermediote Bearer Fe} synchron: Red H Syne Rate Role fous Sox/oU s R Converter Converter Converter] Network ore/c asc Re BRC Interface s0R/00 veo «| SNI | RTS be cuK/ocL. cs e 1on® -2 Li r] : Mw im ‘Status and i wor C] Registers 02 1 TALI inermediate 1 Fo Weer | Xe iro | | FiFo | | FiFo | | Firo User 7
3 Byte] | Byte] [9 Byte] J9 Byte] Rale xTAL2
It fi iy ti 10.752 MHz [~~ Wierocomputer/0MA Interface FSET FET TTP ETT TTT ST wronass TS ST GRCKO HHL
00 WR AE DOR DMR EOOR
| Siemens Aktiengeselischaft 13
The ITAC has three interfaces. The DCE interface provides all necessary data, inter- change and clock signals to form a V.- or X.-series interface. The Synchronous Network Interface is a PCM compatible interface which consists of four lines. It can be configured as |OM-2 compatible and offers additionaly communication paths via the MONITOR chan- nel. The microprocessor interface is compatible to multiplexed bus systems like Siemens/ Intel CPUs. Control lines may be used to synchronize the data transfer between the serial controllers and the memory via DMA. Bit Rate Adaptation Three blocks of the ITAC perform the bit rate adaptation according to the V.110, X.30 or ECMA.102 specification. The first block is the Async/Sync Converter (ASC). It corre- sponds to the RAO block and converts an asynchronous data stream received at the user rate into a synchronous data stream at the network rate. It handles overspeed and under- speed conditions and provides support for flow control. The Intermediate Rate Converter (IRC) corresponds to the RA1 block and converts the synchronous data stream into the V.110 frame. The IRC outputs the V.110 frame at the intermediate rate. The Bearer Rate Converter (BRC) corresponds to the RA2 block and converts the data between the IRC and the Synchronous Network Interface (SNI). Serial Communications Logic The serial communications logic consists of an USART transmitter, receiver and an HDLC transmitter and receiver plus a programmable counter. The data path for the receivers and transmitters are selected independently. They connect to the DCE interface or the IRC. Each receiver/transmitter has a 9 byte FIFO which reduces the response time of the microcontroller. The data transfer between the FIFOs and memory is performed by the microprocessor or by a DMA controller. The USART is used for in-band signaling (X.21, V.25, Hayes), speed conversion and flag-stuffing adaptation protocols (V.120, DMI). The HDLC controller is also used for flag-stuffing protocols and for general HDLC transfer over the B channels. Clock Generation All internal clock signals are derived from a DPLL inside the ITAC. The clock source for the DPLL is the internal oscillator which requires a 10.752-MHz crystal. The DPLL gener- ates the intermediate rate, the network rate and the user rate. The network rate specifies the speed at which the IRC operates while the user rate determines the speed at the DCE interface. 1OM®-2 Handler The 1OM-2 mode, the ITAC supports access to both B channels or the intercommunication channels (IC) for transfering user data. Additionally it can control the MONITOR channel and two C/I bits of the second IOM channel. Siemens Aktiengesellschaft 14
The ITAC provides three test loops. Two loop back the data of the IRC at the network side. The third test loop loops the data of the IRC or ASC at the terminal (DCE) side.
1.3 Operating Modes
The ITAC distinguishes between two basic operating modes. In transparent mode the V.110 framing is done autonomously. Therefore the user rate and the network rate have to be the same. In non-transparent modes the elements of the Serial Communications Logic ({USART, HDLC controller) are switched into the data path. The user rate and the network rate may be different.
1.34 Transparent Mode
In the transparent mode, the ASC (in case of an asynchronous DCE interface), the IRC and the BRC operate autonomously. The microprocessor supervises the status of the IRC and will react only in case of synchronization loss or a disconnect request. To support in- band signaling like the Hayes modem protocol, the USART receiver may be used to moni- tor the terminal data while the counter is used to supervise the guard time. The transparent mode is selected by setting the network rate equal te the user rate. Figure 2 shows the data path for the transparent mode. Figure 2 Transparent Mode. User Rate = Network Rate Terminal] ) POE Network vie02594 Siemens Aktiengesellschaft 15
13.2 Non- Transparent Modes
All non-transparent modes are characterized by the fact that the user rate and the network rate are not the same or the data source or destination is in memory and ‘net the DCE inter- face. Applications for non-transparent modes are: — V.110 Adaptation of terminals with unequal speeds — In-band signaling — V.120 or DMI Terminal adapters — Data transfer from or to the local memory
1.3.2.1 Terminal Adapter for Unequal Speeds
Figure 3 shows the data path for a terminal adapter which can handle unequal data rates. Figure 3 Terminal Adapter for Unequal Speeds User Network Rat Rate Terminaif | OCE_ |" ° Network Inter - rases Siemens Aktiengeselischaft 16
In this figure the user rate is higher than the network rate. In the data path from the lower to the higher data rate, the ASC will add stop bits between the characters to fill the gaps. In the opposite ‘deka path, the USART receiver and transmitter are used to convert the data rates. ‘rorn the DCE interface is received by the USART teceiver and transfered to memory. The data from memory is than written to the USART transmitter and sent to the IRC at the lower data rate. Flow contro! between both ends is performed by interchange circuits or by using flow con- trol characters. To detect these flow control characters (e.g. XON/XOFF) the ASC can compare each received character with two register values. If a match occurs, an interrupt is generated and the character may be deleted from the data stream. Siemens Aktiengesellschaft 7
1.3.2.2 In-Band Signaling
Another non-transparent mode is the handling of in-band signaling information (e.g. X.21, Hayes modem protocol). The USART receiver and transmitter are used during local mode to transfer signaling information between the terminal and the terminal adapter. Figure 4 shows the data path for in-band signaling. Figure 4 Data Path for In-Band Signaling (e.g. Hayes modem protocol) Dee Terminal} | [SE Network face ASC IRC BRC py SN > 1om®—2] COUNTER USAR USAT HOLCR HOLCT Handler i rre0ns9s All data from the terminal is received by the USART receiver and transfered to the micro- Processor. The microprocessor interprets the data and transmits responses to the terminal using the USART transmitter. If the microprocessor which operates with the ITAC is differ- ent from the one which performs the LAPD signaling protocol, the MONITOR channel 1 of the IOM-2 interface can be used for intercommunication. Siemens Aktiengesellschaft 18
1.3.2.3 Terminal Adapter for V.120 or DMI ‘A terminal adapter for V.120 or DMI will also use the non-transparent mode. Figure 5 shows the data path. Figure 5 Terminal Adapter for V.120 or DMI User Network Rate Rate Terminal] PCE Network — al ala ee vre02ss7 All data from the terminal is received by the USART receiver and transfered to memory. The microprocessor adds the V.120 control elements and writes the data to the HDLC transmitter. The HDLC transmitter formats the HDLC frame and sends it to the IRC. In re- ceive direction, the HDLC receiver receives a frame and transfers the data to memory. The microprocessor extracts the user data and writes it to the USART transmitter FIFO. The USART transmitter sends the characters to the terminal. Depending on the selected network rate, 7 bits (restricted 56 kbit/s) or 8 bits (64 kbit/s) of the B channel are used to transfer the HDLC information. ‘Siemens Aktiengesellschatt 19
1.3.2.4 Data Transfer from or to the Local Memory
if the data which has to be transfered over the network doesn't originate from the DCE in- terface but from local memory, another non-transparent mode is used. Figure 6 shows the data path. Figure 6 Data Transfer from or to the Local Memory OcE Inter- face ASC ry orc BRC SHI q }Pli ; t----| ' i 1 t } | 1rB02598 The data from memory is written to the USART transmitter which sends it to the IRC. The IRC adapts the data and outputs it to the SNI. The data from the network is received by the IRC. The user data is forwarded to the USART receiver and transfered to memory. The same data path may be selected for the HDLC blocks to transfer HDLC frames formatted in V.110 frames or transparent over the B channel. Siemens Aktiengeselischaft 20
1.4 System Integration
The ITAC may be used in a number of applications, where terminals with V- or X-series in- terfaces are connected to an ISDN. These applications are: — V- or X- series terminal adapters for basic access — V- or X- series terminal adapter add-on modules to feature phones — PC add-on cards as terminal adapters or basis for ISDN terminals — V- or X- series terminal adapters in exchanges — Modem pools
1.4.1 Terminal Adapter for ISDN Basic Access
A typical implementation of an ISDN basic access for a conventional X- or V- series termi- nal using the ITAC is shown in figure 7. Figure 7 Terminal Adapter for ISDN Basic Access R-Inlerface (X or V series) S-Intertace ® iow ®-2 » CI ‘ Tac? sac ®-s epike| as. FS PSB 2110 ssl PEB 2085 1 avA U 11800558 | Siemens Aktiengesellschaft 21
The ITAC can be connected via a serial synchronous interface (e.g. IOM-2, SSI) to an ISDN basic access transceiver/LAPD controller (in this case, the ISDN Subscriber Access Controller for the S interface, ISAC® -S). These two devices, together with a microcontroller, convert V- and X-series interface characteristics to the functional and procedural interface characteristics required by an ISDN at reference point S. in this configuration, the [TAC will do the rate adaptation according to V.110, X.30 or ECMA.102 autonomously. The ITAC together with the microcontroller is used to receive and transmit signaling information between the terminal and the terminal adapter. The microcontroller together with the ISAC-S will convert the signaling data and transfer them using LAPD on S-interface. In V.120 and DMI terminal adapters the ITAC together with the microprocessor will perform the rate adaptation. Siemens Aktiengeselischaft 22
a
4.4.2 Terminal Adapter Add-On Modules for Feature Phones
A modular design of a feature phone may contain of a basic voice board with a microcon- troller and an S-interface circuitry. Via the IOM-2 interface additional modules like en- cryption modules, card readers or terminal adapter modules may be added. Such a con- figuration is shown in figure 8. Figure 8 Feature Phone Plus Terminal Adapter Add-On Module Based on 1om®-2 tei _ ® \\ > irac® ARCOFI arcori® -SP } i 8 S-interface i uP = os (e.g. Hoyes- SK isac®-s Protocol) é WL Ss pP (Lapo) TA Add-On Module Feature Phone 17802600 The microcontroller on the feature phone performs the telephone functions plus the pro- cessing of signaling information according to the LAPD protocol. The microcontroller on the TA add-on module performs the DTE signaling protocol (V.25 bis, Hayes) and controls the ITAC. Data between both microcontrollers is ‘exchanged via the MONITOR channel 1. This data includes telephone numbers, call status information as well as B-channel as- signment. Siemens Aktiengesellschaft 23
14.3 PC Add-On Cards
Add-on cards for IBM PCs or compatibles based on the ITAC are not just simple terminal adapters but turn the PC into an ISDN terminal. A standard design is shown in figure 9. Figure 9 Add-On Cards for PCs I— KS arcori® | 16450 —_ . com- © ver PtH KOS — ; HJ = Ko) sac ®-s a Dual-Port Memory uP Memory 11302601 Universal programs use the COM-Port to transfer data. The ITAC operates just like a termi- nal adapter. For card-specific application programs the Dual-Port Memory is used to transfer data between the PC Bus and the ISDN card. The ISDN card will transfer this data using the build-in communications controllers of the ITAC. A card like this is able to adapt the COM-Port according to the standards V.110, V.120 or DMI mode II. Additionally it can be used to access X.25 packet data services and it can transfer group IV facsimile data. Siemens Aktiengesellschatt 24
1.4.4 Modem Pools
The ITAC supports V.110 subchannel multiplexing. This means that the 64 kbit/s bearer channel is shared by up to eight independent terminals. This is illustrated in figure 10. Figure 10 Sharing of Bearer Channel Among Serveral Independent DTEs B-Channe! S-Interface aie sac ®-s CT TT) a on en en an ae / smp02602 16 kbit/s 32 kbit/s 8 kbit/s 8 kbit/s R-Reference Point Terminal 1 Terminal 2 Terminal 3. Terminal 4 9600 baud 19200 baud 1200 baud 4800 baud
1.4.5 Other Applications
The synchronous network interface of the ITAC is compatible to most PCM systems using programmable time slots. Consequently, the circuit in association with all IOM-2 com- patible circuits, is ideally suited for applications on PABX line cards and concentrators/ multiplexers. Other applications of the ITAC include: host computer multiple line communication couplers, primary access/DMI peripheral boards, and Interworking Units (IWUs) between ISDN and analog PSTN. Siemens Aktiengesellschaft 25
2 Operational Description
24 Microprocessor/DMA Interface
The microprocessor interface of the ITAC is designed for multiplexed address/data bus systems. The contents of the address/data lines is latched on the falling edge of ALE to form the register address. After chip select (CS) becomes active, the read or write control line specifies the register access. If read becomes active, the contents of the selected reg- ister is output on the address/data lines. If write becomes active, the contents of the ad- dress/data lines is latched into the selected register. The address decoder uses address lines AD1 to AD6. Address fine ADO is not evaluated to allow a direct interface to 16-bit microprocessors like the SAB 80C186. The SAB 80C186 accesses the ITAC registers via even addresses. Address line AD7 is also not evaluated so that the occupied address space ranges from 00H to 7FH and another de- vice may use the address space from 80H to FFH. The DMA acknowledge inputs have to be connected to Voo if they are not used. Figure 11 shows the connection of an ITAC to a SAB 80C188/80C31 microprocessor without DMA support. Figure 11 Connecting the ITAC® to SAB 80C188/80C31 apo-7 |<" ano-7 ALE “oy ALE ® SAB 80C188 = — Tac sap goc31 PSO cs psa 2110 | [I] mt |] WR wR DACKO RES — > RST DACKI | T+ note 1 7302603 from Reset Logic * Note 1: if DMA acknowledge inputs not used Siemens Aktiengesellschaft 26
The ITAC supports data transfer between the FIFOs and memory via DMA (Direct Mem- ory Access). If the ITAC requires a data transfer, it will indicate this to the DMA controller via a DMA request signal (DMIR, DMOR). The DMA controller will than signal to the CPU that it requires the control over the address and data bus. After the CPU responded by is- suing an acknowledge signal, the DMA controller starts to transfer data. DMA requests generated by the ITAC are acknowledged by the proper read or write oper- ation to the FIFO. The read or write operation can be performed in two ways. The first way is to perform a standard CPU cycle on one of the FIFO addresses. In this case, both DMA acknowledge inputs have to be connected to Vo. The second way uses the DMA acknowledge inputs to select the FIFO address instead of a C&-signal. The RD or WR control signal together with the proper DMA acknowledge input selects the data bus operation. This allows single cycle V/O to memory transfers. Both possible acknowledgements are shown in table 1. Table 1 DMA Acknowledgements Request Acknowledgement | Operation DMIR DACKI e WR DMA transfer from memory to ITAC FIFO. or CS (FIFO) e WR DMOR |DACKO eAD _| DMA transfer from ITAC FIFO to memory or CS (FIFO) @ RD The EODR output indicates that the last byte of a frame has been transtered by the DMA controller. It reflects the inverted status of the RME bit if the DMA interface is connected to the HDLC controller. The generation of DMOR requests is blocked until the RME status bit has been acknowl- edged regardless whether the RME interrupt enable bit is set or cleared. Siemens Aktiengeselischaft 27
22 DCE Interface
The DCE interface consists of 13 lines in total. The number of available signals and their meaning depends on the selected clock mode (synchron or asynchron) and on the se- lected interchange configuration. The DCE interface may either operate synchron or asynchron. The selection is done by the ‘ASY' bit in the General Configuration Register (GCR).
2.2.1 Operating Modes
Synchronous Operation (GCR:ASY = 0) During the synchronous operation, the clock signal which synchronizes the data transfer is outputed on the S-line. The data rate is equal to the selected user rate (BRS:URO-3). The data on RxD is clocked off on the falling edges of the S-clock while data on TxD is latched on the rising edge of S. The ASC is inactive. Asynchronous Operation (GCR:ASY = 1) No clock signal is available on the S-line during asynchronous operation. In receive di- rection, the internal clock (16 * user rate) is synchronized on every falling edge of a start bit or every falling edge of the received data stream (bit transparent mode). The TxD is sampled in the middle of each bit (after 8 internal clocks). Data on RxD is transmitted with no synchronization to the received data stream. The ASC is active. Siemens Aktiengeselischatt 28
2.2.2 Interchange Circuits
The meaning of the interchange circuits and the corresponding status detection logic de- pends on the selected interface type. If the X.21 interface is selected, only C (Control) and | (indicate) interchange lines are available. The status detection logic reports the rec- ognized combination of local (TxD,C). If a non-X.21 interface (V-series interface) is se- lected, 10 interchange circuits are available. Their current status can be read from or writ- ten into registers, or controlled by the S-bits of the V.110 frame. X.21 Interchange Circuits (GCR:V24 = 0) The status detect logic samples the received data on TxD and the status of the control line (C). It reports the current status combination via the LDS (Local DTE Status) and the ELDS (Extended Local DTE Status) registers. A change in the LDS register is indicated by the LDC bit in the IST (Interrupt Status) register. A change in the ELDS register is indicated by the ELDC bit in the IST register. Both bits may generate an interrupt if their corresponding bit in the ISEN (Interrupt Status Enable) register is set to one. The status detection logic is in no-state after reset. 'No state’ is indicated by a value of zero in both status registers (LDS, ELDS). The status detection logic starts to sample the TxD and C line on every rising edge of the S-clock signal. The sampled values are com- pared against the different possibilities after 16 samples were taken. If a match is detected, the LDS and ELDS register change to the new value and set the corresponding LDC or ELDC bit to ‘1'. This may generate an interrupt. If a status is detected, which is different from LONX or LOFX, the status detection logic will sample four bits before the pattern is varified. If the status is no longer true, the LDS and ELDS registers change to ‘no-state’ (00) and the corresponding LDC or ELDC bit will be set. The next status will be indicated after another 16 bits have been sampled. If LONX or LOFX or no valid status is detected after 16 samples, the status detection logic will check its last 16 samples after every clock cycle. The valid status are shown in table 2. Siemens Aktiengesellschaft 29
DTE Status Logic Indications Status | Status Name Sampled Data Register Bit LONO = | Local (0, ON) TxD 00000000 00000000 LDS : Bit7 Cc 00000000 00000000 LOFO1 [Local (0101,OFF) |TxD 01010101 01010101 LOS : Bit6 C 11141111 111919111 LL3 Local Loop 3 TxD 00001111 00001111 LDS : Bit5 Cc 00000000 00000000 LONX | Local (X, ON) TxD XXXXXXXK XXXXXXXX ELDS : Bit7 Cc 00000000 00000000 LOFX Local (X, OFF) TxD XXXXXXXX XXXXXXXK ELDS : Bit6 C11111114 11191111 LON1 Local (1, ON) TxD 11111111 11111111 ELDS : Bit5 C 00000000 00000000 LOF1 | Local (1, OFF) TxD 111111991 11111111 ELDS : Bit 4 | C 11111411 41111111 LOFO Local (0, OFF) TxD 00000000 00000000 ELDS : Bit3 C114111147 11191111 LL2 Local Loop2 TxD 00110011 00110011 ELDS : Bit 2 C1141111419 11991111 Note: X =Oor1 The value of the | interchange circuit depends on the setting of the RCS bit in the DPCR register. If the RCS bit is ‘0’, the value of the | interchange circuit is controlled by the DCD/ L-bit in the LDR register. If the RCS bit is '1', the value of the interchange circuit is con- trolled by the received S(SA)-bits. Siemens Aktiengesellschaft 30
V-Series Interchange Circuits (GCR:V24 = 1) The configuration of the DCE interchange circuit in V.24 mode are shown in figure 12. Figure 12 DCE Interchange Circuits (GCR:V24 = 1) b — wir ——— - F | RTS. <b | ee |g gg 1 to IRC f b | — tio t eles User Rate ts “ FI L4 wor — I<] jo o | “lL : | cts —— <q osk — |<] EE © fram IRC | | = |. sB i} 0 1. . GeeelbLH GCR:DOE User Rate DPCR:RSC LOR se2s0e Siemens Aktiengesellschaft Ka)
The level of the CTS, MO1 and MO2 output is always controlled by the corresponding bits in the LDR register. The level of the DCD and DSR output may be controlled by the corresponding bits of the LDR register. This. ia selected if tha RCS bit in the BPCR register is get to, 0. The level of tha DCD output is controlled by the received SA bits. and the level: of the DR output is controlled by the received SB bit if the, RCS bit ig set to 1. The input levels are sampled with the user rate period, The. sampled value can always be read from, the LDS, register and may be forwarded te the S-hits. A change on at least one of the controt tines wilk genexate. am LDC, interrupt. This interrupt is, delayed by half a user rate period. 2.2.3. DCE Output and Input Characteristics Output Drivers All output drivers of the DCE interface are tri-state drivers. The enable function of the drivers is controlled by the DOE bit in the GCR register. If GCR:DOE (DCE Output Enable) = 0, all output lines are tri-state. If GCR:DOE = 1 all output drivers are active. If it is re- quired to set all output lines to a defined state while DOE = 0, external pull-up resistors must be connected to all output pins. Connection of Open Inputs All available input pins of the DCE interface must be set to a defined state in order to avoid interrupts. Unused inputs may be connected to an external pull-up resistor or to GND. Siemens Aktiengesellschaft 32
2.3 Synchronous Network Interface
The Synchronous Network Interface (SNI) consists of four lines. Two lines transfer the data signals, one line receives the bit clock signal while the last line receives the frame start signal. The SDX/DU line is used to transmit data to the network side, while SDR/DD line is used to receive data from the network. The bit clock signal (one clock cycle per bit) or the data clock signal (two clock cycles per bit) is connected to the CLK/DCL input. The frame start signal (8 kHz) is connected to the FSC input.
2.3.1 Operating Modes:
PCM Interface (single bit clock) Single bit clock operation is selected, if SCR:DCL = 0. This means that there is one clock cycle per data bit. The transmitted data is clocked off the SDX/DU line by the rising edge of the CLK signal while the received data on the SDR/DD line is latched with the falling edge of the CLK signal. Figure 13 PCM Interface (single bit clock) 125s | eS - it ul il CLK/DCL i i I ' in spR/0D ——> fo the mac® il i Y i in in ; Time Slot (IS) 0 | si 1 LIS et 1s0 ~ |= H - Frame with n Time Slots Next eT =! Frame rnpo26a5 Siemens Aktiengesellschaft 33
1OM®-2 Interface Double bit clock operation is selected, if SCR:DCL = 1. This means that there are two clock cycles per data bit. The transmitted data is clocked off the SDX/DU line by the first rising edge of the CLK/DCL signal while the received data on the SDR/DD line is latched at the falling edge of the second cycle of the CLK/DCL signal. Figure 14 10M®-2 Interface (double bit clock) 1254s | in i i CLK/DCE J ! in i | in ———_ SbR/0D I i —__ SOx/DU J I I Time Slot (TS) 0 TS) HTS n= TSO fo me SEIS ge Frame with n Time Slots Next ee nt Tn 17002606 ‘SNI Clock Characteristics In both cases the FSC signal has to fulfill a short setup and hold time. The signal on CLK/ DCL may not be symetrical. The data rate on the SNI has to be more or equal to twice the maximum intermediate rate. To transfer 64, 56, 48 or 38.4 kbit/s the minimum data rate on the SNI is 128 kbit/s. ‘SNI Output Driver Characteristics The output driver of the SDX/DU line can be programmed to a push-pull output (SCR:OD = 0) or to an open-drain output (SCR:OD = 1). The output driver is only active during the transmission of the selected bits on the time-slot and tri-state during the other bits of the frame. Siemens Aktiengesellschaft 34
a If the output driver is set to open-drain output, an external pull-up resistor is required. The value of the resistor depends on the length of the line and the number of connected devices. The minimum value for the resistor is 720 0. 2.3.2 1OM°.2 Interface Support The ITAC offers additional support for the 1OM-2 interface mode. This include the protocol support for the MONITOR channel 1 and the control of the CI5 and CIé bits in the up- stream Cl1-channel. It is enabled by setting the MOCR:1OM2 bit to "1". Figure 15 10M®-2 Interface Support 1om® CHO iom® -cHt tom® ~cH2 owe -cH9 _,_e o Lebo eee 1 TT Tre] s ee ~ PT EE) Le TEE D clo [RIX cht IPL PREX oo sfebips — — = ——s 1 v 0 1 Tronsier of V.110 Data EE controties ty Register Bits FE1 Contraties by the MONITOR-Chonne! Handler Siemens Aktiengesellschaft 35
Selection of the V.110/X.30 Data Stream The V.110/X.30 formated data can be transfered over all time slots of the IOM-2 interface by programming the TSR register. But only four settings are recommended. They are listed in table 3 and show the programming for B1, B2 and IC1, IC2. Table 3 - Selection of Time -Slots in tom®-2 Mode - 1OM Channel TSR Value BI O0000XXX B2 00001 XXX Ic1 00100XXX Ic2 00101XXX MONITOR Channel Support The IOM-2 handler of the ITAC includes a MONITOR channel handler for the MONITOR channel 1. The access is hardwired to time slot 7 for the MONITOR data byte and time slot 8 for evaluation of the MR, MX bits. The MONITOR channel handler performs the MONITOR channel protocol. It provides a receive and transmit register for the MONITOR channel data byte plus control and status bits. Since the ITAC requires a microprocessor interface for operation, there is no auto- matic comparison of the MONITOR channel address byte. The begin of all MONITOR channel messages is received and the microcontroller accepts a message by setting the MRC control bit to '1". More information about the MONITOR channel protocol is available in the IOM-2 ref- erence guide. (Order-No: B1 15-H6397-X-X-7600) Siemens Aktiengesellschaft 36
Control of the MONITOR Channel Handier The MONITOR channel handler is controlled by four bits of the MONITOR Channel Con- trol Register (MOCR). They are listed in table 4. Table 4 MONITOR Channel Control Bits BitName [Bit No. Function MXC 0 MONITOR Channel Transmit Control Controls the operation of the transmitter. If set to '0', the MX-bit stays 'l' and MOX1 transmits 'FF' (idle). If set to '1', data written into the MOX) register will be transfered according to the MONITOR channel protocol. MIE MONITOR Channel Interrupt Enable When set to '1', the status bits MDA, MER and MAB may gener- ate an interrupt. Otherwise, the interrupts are masked. MRC 12 MONITOR Channel Receive Control Controls the operation of the receiver. When set to '0', MDR status changes are blocked except for the first byte of a mess- age. When set to '1', received bytes will be acknowledged auto- matically after they have been read from the MOR1 register. MRE 3 MONITOR Channel Receive Enable | When set to ‘0’, the generation of MDR status changes is dis- | abled including the first byte of a message. When set to ‘1’, the MDR status is set for each MONITOR address byte (if MCR = 0) |or for each received byte (MRC = 1). Siemens Aktiengesellschaft 37
Indications of the MONITOR Channel Handler Changes in the MONITOR channel handler are indicated by four status bits in the MONI- TOR Channel Status Register (MOSR). There meaning is shown in table 5. Table 5 MONITOR Channel Indications BitName | Bit No. Meaning MAB MONITOR Channel Abort If set to '1', the opposite receiver has aborted the transmission. MDA 1 MONITOR Channel Data Acknowledge If set to '1', the opposite receiver has acknowledge the data transfer. A new byte may be entered into the MOX1 register or ___|the MXC-bit may be cleared to indicate the end of message. MER 2 MONITOR Channel End of Receiption If set to '1', the local receiver has detected an end of message condition. The MCR-bit may be cleared to indicate the end of transmission. MDR 3 MONITOR Channel Data Received If set to '1', the local receiver has received a new byte. It can be read from the MOR? register, which will automatically gener- _ H ate the acknowledgement if MCR = 1. __ Cl-Channel Control The IOM-2 handler of the ITAC allows the control of bit 5 and 6 in the upstream direction of Command/Indicate (Cl)- Channel 1. The inverted value is written into the CIXS and CIX6 bits of the MOCR register. Software Awake In order to activate a deactivated 1OM-2 interface, the SDX/DU pin can be controlled via the SAW-bit. If set to '1', the SDX/DU output is forced to '0' while the following condition is true: FSC*IOM2*SAW=1. Since the FSC signal is high during the first |OM-2 channel and low during the remaining period, MONITOR channel 1 is available to indicate the active condition of the IOM-2 interface and to indicate that the SAW-bit can be reset. Siemens Aktiengeselischaft 38
24 Clock Generation
The ITAC derives all its clock signal from the on-chip oscillator which requires a 10.752- MHz crystal. The oscillator is controlled by the power-up bit (PU) in the GCR register and in case of an asynchronous interface also from the DTR input. Oscillator If a synchronous interface is selected (GCR:ASY=0), the oscillator stops if GCR:PU = 0 and starts if GCR:PU = 1. If an asynchronous interface is selected (GCR:ASY=1), the oscillator stops if GCR:PU = 0 and the level on the DTR input is high (OFF). It is started when either GCR:PU is set to 1 or the level on DTR changes to low (ON). This will automatically set the GCR:PU bit to '1". The oscillator needs a maximum period of 10 ms to generate a stable clock signal. The external crystal is connected between the XTAL1 and XTAL2 pin. XTAL1 is the oscil- lator input and XTAL2 its output. If an external clock source is used to generate the 10.752-MHz clock, its signal is connected to XTAL1. Figure 16 Connection of Clock Sources Cw __ 10.752 MHz from XTALT ion XTALI- + sciiator imac ® c= 10.752 MHz tac ® XTAL2 lH xTALZ Not Connected Cw 71507608 Note: Value of Cio is determined by the XTAL-specification. Two or more ITAC on the same board may share one crystal. This crystal is connected to XTAL1 and XTAL2 of one ITAC. The XTAL1 input of the other ITACs are connected to the XTAL2 output of the crystal. The XTAL2 output of the other ITACs are left open. The load capacity of both crystal pins should be same. On XTAL1, there is just the input capacity of one ITAC. On XTALZ, there is the sum of one output capacity plus the input capacity of the other ITACs and the capacities of the line. To calculate the resulting capa- cities, each input capacity has a maximum value of 7 pF. Please note that the power up bit (GCR:PU) of the ITAC to which the crystal is connected has to be '1’ in order to provide a clock signal on XTAL2. Siemens Aktiengesellschaft 39
Driving Two ITAC® Oscillators by One Crystal Cw xTatt (aon tac® =} 10.752 MHz XTAL2 (oon Cine XTALT rac® XTAL2 Nol Connected 17502609 Operation of the DPLL The DPLL generates four clock signals which are synchronized to the 8-kHz clock on the FSC input. The four clock signals are the user rate, which specifies the speed of the DCE interface and the DCE side of the ASC, the network rate, which specifies the speed of the IRC and the IRC side of the ASC, the intermediate rate, which specifies the speed be- tween the IRC and the BRC and the 8-kHz reference signal for the DPLL. Siemens Aktiengesellschaft 40
Selection of the User Rate, Network Rate and Intermediate Rate The user rate and the network rate are programmed in the BRS register. The intermediate rate is automatically selected by the value of the network rate. Table 6 shows the possible settings for the network rate. Table 6 Network Rates NR3 NR2 NR1 NRO | Network Intermediate | Number of Bits | Remarks Rate Rate per time-slot te) 0 0 0 - - - reserved tC) 0 [) 1 600 bit/s | 8 kbit/s 1 4x80 bit framing tC) bY) 1 t) 1200 bit/s | 8 kbit/s 1 2x80 bit framing ) te) 1 1 2400 bit/s | 8 kbit/s 1 80 bit framing i} 1 QO i} 4800 bit/s | 8 kbit/s 1 80 bit framing ) 1 0 1 9600 bit’s | 16 kbit/s 2 80 bit framing VY) 1 1 O 19200 bits | 32 kbit/s 4 80 bit framing ) 1 1 1 38400 bit/s | 64 kbit/s 8 80 bit framing 1 oO 0 0 48000 bit/s | 64 kbit/s 8 32 bit framing 1 i) ) 1 56000 bit’s | 56/64 kbit/s | 7/8 7 bit framing 8 bit framing 64 bit framing 1 0 1 O 64000 bit/s | 64 kbit/s 8 8 bit transparent 1 0 1 1 - - - reserved 1 1 x x |- - - reserved The selectable user rates depend on the selected DCE interface type. If an asynchronous interface (GCR:ASY = 1) is selected, the user rate can be set between 300 and 38400 baud. The user rate may range between 600 and 64000 bit/s if a synchronous interface is selected (GCR:ASY = 0). Siemens Aktiengeselischaft 42
UR3 UR2 UR1 URO |Sync.DataRate [Async.DataRate | Remarks ooo o | | soobts [| | oo o 1 | 600 bit/s 600 bis 0 0 1 0 1200 bits 1200 bit/s oo 1 1 | 2400 bit's | 2400 bit’s o 41 oO 0 | 4800 bits | 4800 bit/s o 1 0 1 | 9600 bits | 9600 bit/s o 1 14 0 | 19200 bits | 19200 bit’s o 1 4 4 | 38400 bit/s | 38400 bit/s 1 0 0 Oo | 48000 bis if 1 0 0 1 }56000 bits \\- 1 0 14 © — |64000 bit’s |. 1 ° 1 1 - | - reserved 1 1 x x - |- reserved Siemens Aktiengeselischaft 43
25 Async/Sync Converter (ASC)
The Async/Sync Converter transforms a stream of Start/Stop bit formatted characters at the user rate into a synchronous bit stream at the network rate and vice versa. It is active if the DCE interface is set to asynchronous operation (GCR:ASY = 1). Functions of the ASC in Transmit Direction (to the network) The ASC block diagram of the transmitter is shown in figure 20. Figure 20 ASC Transmitter Asyne / Syne Converter User Rote Network Rote viso26i2 In transmit direction the ASC will frame the incoming characters (from the DCE interface) and transfer them to the IRC at the network rate. If the user rate is less than the network rate, the gaps between characters are padded by stop bits. The ASC will not operate properly if the user rate is higher than the network rate. If the actual data rate at the DCE in- terface is higher than the nominal user rate, stop bits will be deleted within the limits of the selected tolerance range. If AICR:TR = 0 the tolerance range is 12.5 %. This means that every eighth stop bit may be deleted. If AICR:TR = 1 the tolerance range is set to 25 %. This means that every fourth stop bit may be deleted. The ASC will also recognize a break signal. The break signal is detected when at least M bits of start polarity have been re- ceived. M denotes the number of bits per character in the selected format including start and stop bits. If the ASC detects a break condition from the DCE interface, it will transmit at least 2M+1 start bits towards the IRC. Siemens Aktiengeselischaft 44
Functions of the ASC in Receive Direction (from the network) The ASC receiver is shown in figure 21. Figure 21 ASC Receiver S02613 In receive direction the ASC receives the synchronous bit stream at the network rate and transfers it into a character stream at the user rate which is transmitted to the DCE inter- face. If the network rate is less than the user rate, the gaps between characters are padded by stop bits. The receive direction will not operate properly if the network rate is higher than the user rate. If a missing stop element is detected in the data stream, the length of the stop bits transmitted to the DCE interface is reduced according to the se- lected tolerance range. Siemens Aktiengeselischaft 45
Recognition of Special Characters (flow control) Two programmable characters can be specified for each direction. If a character is re- ceived from the DCE interface, which matches the value of LCAR1 or LCAR2 the corre- sponding status bit is set in the Special Condition Status register (SCS). If the Local Char- acter Stop bit in the Special Configuration register (SCR:LCS) is set to '1', the received character bits are substituted by stop bits. Thus the character is deleted from the data stream. The same function is available for the received data from the network. The special character registers are RCAR1 and RCAR2. The Remote Character Stop bit (SCR:RCS) controls the substitution of the character bits. Figure 22 Special Character Recognition ASC ‘ABCD’ SCR:LCS = 0 ‘ABCD’ LCAR1 ='BY SCSLCI = 1 ASC "ABCD" SCR:LCS = 1 ‘ACD LCAR1 ='B' SCS:LC1 =1 This feature may be used to detect and remove flow control characters (KON/XOFF) from the data stream. Siemens Aktiengesellschaft 46
The Character Insert Register INSC allows to insert characters in the receive data stream (from the network). The character which has to be inserted is written into the INSC register and automatically inserted at the next opportunity. The status whether the character has been inserted or not is supervised by the CIS bit in the Status register STR. This feature may be used to add flow control characters in the data stream towards the DCE interface. The character written into the INSC register has to contain a possible parity bit and un- used bits have to be filled with ones. If the ASC receives data while a character has to be inserted, it will insert the character after the current character has been completed and it will reduce the length of the stop bits of the following characters. Thus the received characters are not pertubed. Figure 23 Character Insertion Using INSC ASC "ABCZDEF INSC = 'Z° <—— ‘ABCDEF Siemens Aktiengeselischaft 47
Selecting the character format for the ASC The character format of the ASC is programmed by the AICR and the UMR register. If a parity bit is selected, the format of a character is incremented by one bit. The ASC will not check the parity on the received character. Table 8 Character Format of the ASC Start Character Length Parity Stop AICR:CHL1,0 UMR:PTY AICR:STP AICR _ CHL1 Character Length (Bit) t) 0 Eight 0 1 Seven 1 i) Six 1 1 Five UMR Pry Paty 0 x x no 1 x x yes AICR:STP Number of Stop Bits 0 1 ; 1 2 Siemens Aktiengesellschaft 48
a
2.6 Intermediate Rate Converter
The intermediate rate converter performs the framing according to V.110 or X.30. The source and destination of the D bits may be the DCE interface, the Serial Communications Logic or register bits. The source and destination of the S bits may be the DCE interface or register bits. The source and destination of the X and E bits are always register bits. The operation of the IRC is controlled by the ENFR bit (GCR). Before the ENFR bit is set to +1", the network rate, the V.110/X.30 frame format and the time-slot has to be programmed. If one of the register values needs to be changed, the ENFR bit has to be cleared for one period of the previous intermediate rate. Frame Structures The frame structure depends on the selected network rate. For network rates from 600 to 38400 bit/s a 80-bit frame is used. For a network rate of 48000 bit/s a 32-bit frame is used. For a data rate of 56000 bit/s one of two frame alternatives may be selected. One uses a 8- bit frame while the second one uses a 64-bit frame. If the 8-bit frame is selected and the status of the IRC is masked, a transparent 56 kbit/s channel is available. No framing is per- formed if the network rate is 64000 bits. Table 9 to 16 show the framing for the individual data rates. Table 9 Table 10 Frame Structure for 600 bit/s Frame Structure for 1200 bit/s Octet | Frame Structure Octet | Frame Structure No. |12 3 4 5 6 7 8 No |12 3 4 5 6 7 8B T leo 0 0 0 0 00 + |00 6 6 0 0 0 0 2 1 D1 D1 DI Di Or D1 St 2 4 D1 Df DI Dt b2 D2 SI 3 1 D1 DI v2 D2 D2 D2 xX 38 4 D2 D2 D3 D3 D3 D3 x 4 + D2 D2 D2 D2 D3 03 SB 4 1 DS D4 D4 D4 DS DS 83 5 1 D3 D3 03 D3 D3 03 S4 5 1 D5 DS D& D6 D6 DG S4 6 14 £1 £2 &3 E4 ES &6 ET 6 4 E1 &2 63 E4 5 &6 E7 7 1 D4 D4 D4 D4 D4 DS SE 7 1 07 D7 D7 07 DB DB Sb 8 1 D4 D& DS DS DS D5 X 8B 1 D8 08 D9 D9 D9 Oo xX 9 1 D5 D5 D5 DS D6 D6 SB 9 1 P10 Dio DIO D10 D11 O11 SB 10 1 06 Ds D6 D6 D6 D6 S9 10 1 Di1 D1t D12 O12 D12 O12 $9 *E7 is controlled automatically and transmits 1011. Siemens Aktiengeselischaft 49
Frame Structure for 2400 bit/s. Frame Structure for 4800, 9600, 19200, 38400 bit/s Octet | Frame Structure Octet | Frame Structure No. /1 2 3 4 5 6 7 8 No |/1 2 3 4 5 6 7 8 1 jo 0 0 0 9 0 0 0 1 [o0 0 0 0 0 0 oO 2 1 D1 D1 02 D2 D3 D3 St 2 1 D1 D2 D3 D4 D5 De St 3 1 D4 D4 DS DS Dé DB X 3 1 D7 D8 Ds DIO DI1 DIZx 4 1 D7 D7 D8 Ds D9 D9 Ss 4 1 DIZ _D14 O15 DI6 DI7 DIB Ss 5 1 D10 D10 Dit Dit DI2 DIZS4 5 1 D19 D20 D2 D22 D23 Des S4 6 1 €1 €2 £3 £4 E5 E6 E7 6 1&1 £2 £3 E4 5 E6 E7 7 1 D13 013 DI4 D14 DIS DIS S67 1 025 026 D27 D28 029 D30 Sé 8 1 DI6 DI6 DI7 DI7 DIB DIBX 8 1 31 D32 D33 D34 D035 DI6 x 9 1 D19 D19 020 D20 D21 D21ss 9 1 037 038 D39 D40 D41 p42 SB 10 1 De2 D22 D23 D23 D24 D24s9 10 1 D43 _D44 D45 D46 D47 D48 SO Table 13 Table 14 Frame Structure for 56000 bit/s Frame Structure for 56000 bit/s Frame Alternative 1 _ Frame Alternative 2 _ Octet | Frame Structure Octet | Frame Structure No |1 2 3 4 5 6 7 8 NO |11 2 345 6 7 8 1 [D1 02 03 D4 DS D6 Dy 1 1 Di D2 D3 D4 DS D6 D7 0
2 Ds D9 D10 DI DI2 013 B14 1 2 D8 D9 DIO Dit D12 DIS DI4 x
3 DIS D16 DI7 Di8 D19 020 D211 3 DI5 D16 D17 B18 DI9 O20 D21 SB
4 022 D23 D24 D25 026 O27 D281 4 22 023 D24 D25 026 027 D28 S4 5 029 030 D31 D32 033 D34 035 1 5 D29 D380 D31 032 D33 34 D351 6 036 037 D38 039 D40 D41 D421 6 036 D37 D38 039 D40 D41 D42 1
7 D43 44 D45 D46 D47 048 D491 7 D43-D44 D45 DAG D47 D4B DAD 1
8 D50 D51 O52 D53 DS4 055 D561 8 050 DS1 052 D538 D54 055 D56 1
Frame Structure for 48000 bit/s Frame Structure for 64000 bit/s Octet | Frame Structure Octet | Frame Structure No. |12 3 4 5 6 7 8 No |1 2 3 4 5 678 1 1 D1 D2 D3 D4 DS D6 St 1 Di D2 D3 D4 D5 D6 D7 DB 2 0 D7 De D9 DIO D1 DI2 x TE 3 1 D13 _DI4 DIS DIE DI7 DIB $3 4 1_D19 D20 Dai p22 D23 O24 S4 Siemens Aktiengeselischaft 50
Explanation of the Frame Elements All frames consist of five basic elements. The first element is the frame synchronization pat- tern. The other four are the D-bits, the S-, X- and E-bits. Frame Synchronization Pattern The frame synchronization pattem are shown in table17 to 20. The frame synchronization pattern for a network rate of 600 bit/s uses E7 for super frame synchronization. Network rates of 48000 bit/s or 56000 bit/s use the octet alignment pro- vided by the B channel. Bit 1 of each ‘octet is tested at 48000 bit/s while bit 8 is used at 56000 bit/s. Table 17 Table 18 Frame Synchronization Pattern for Net- Frame Synchronization Pattern for a Net- work Rates 600 ... 38400 bit/s work Rate of 48000 bits ee Octet | Frame Structure Octet | Frame Structure No |12 3 4 5 6 78 No |1 2 3 4 5 6 7 8 7 loo o 0 0 000 1 1 2 i 2 ° 3 1 3 1 4 1 a oi 5 1 i 6 7 «e7)" 8 \\1 9 in fo Table 19 Table 20 Frame Synchronization Pattern for a Frame Synchronization Pattern for a Net- Network Rate of 56000 bit/s work Rate of 56000 bit/s Frame Alternative? Frame Alternative2 Octet | Frame Structure Octet | Frame Structure No \\12 3 4 5 6 7 8 No |1 2 3 4 5 6 7 8 1 ee ee 2 1 2 3 | 1 3 4 | 104 5 1°65 1 6 1 6 1 7 107 1 rr ! *E7 is controlled automatically at 600 bit/s. Siemens Aktiengesellschaft 51
The D-bit positions (D1 ... D48) are used to transfer the data stream between both ends. The data stream includes all character, parity, start and ‘Stop bits. If the network rate is less or equal to 4800 bit/s each bit of the data stream is transmitted twice, four or eight times to match the intermediate rate. S-Bits The S-bits are used to transfer the state of interchange circuits. In a V.110 frame, two S-bit groups SA and SB are available. SA transmits the state of the DTR/C interchange circuit (108) to the DSR interchange circuit (107). SB transmits the state of the RTS interchange circuit (105) to the DCD/\\ interchange circuit (109). In an X.30 frame all S-bits are used to transfer the state of the C/DTR (108) interchange cir- cuit onto the /DCD (109) interchange circuit. The selection between both S-bit alternatives is done by the V110 bit in the General Con- figuration Register. If GCR:V110 = 0, the X.30 frame is selected. GCR:V110 = 1 selects the V.110 frame. V.110 frame (GCR:V110 = '1') X.30 frame (GCR:V110 = 0’) DTR/C (108) +» SA - DSR (107) DTR/C (108) > S - DCDA(109) RTS (105) > SB + DCD/A(109) A A Note: SA=S1,S3, S6, S8 SB = S4,S9 X-Bits The X-bits are used to perform flow control between both terminal adapters. E-Bits The E-bits are used to transfer information between both terminal adapters. In a V.110 frame, E1 to E3 are used to identify the user rate. E7 is automatically controlled if the net- work rate is set to 600 bit/s. Siemens Aktiengesellschaft 52
Sample Points of the S-Bits The coordination between the sampling of the D- and S-bits for a synchronous DCE inter- face (GCR:ASY = 0) is shown in table 22. Table 22 Sample points of the S-Bits SBit DBit OctetNo, [BitNo. st 2 (308) TO s3 3 4(D16) 84 4 7 (024) S6 7 3 (D32) $8 8 5 (D40) s9 9 7 (D48) If the DCE interface is asynchronous (GCR:ASY = 1), the S bits are sampled while the stop bit of the character is received. If no character is received, the S-bits are sampled during D8, D16, D24, D32, D40 and D48. During a break condition, the S-bits are not sampled for version VA1, VB1. The version V2.2 samples the S bits every eight D-bits during a break condition. Function of the Transmitter The IRC-transmitter is enabled by setting the ENFR bit to 1’. The transmitter part of the IRC will format the required frame. Therefore it will generate the frame synchronization pattern and insert the D-, S-, X- and E-bits. The source of the D- bits can either be the DCE interface, the Serial Communications Logic or the register bit XD. The source of the S-bits can either be the DCE interface control lines or the register bits S/SA and SB. The source of the X- and E-bits will always be the register bits. Figure 24 illustrates the possible data paths. Siemens Aktiengeselischatt 53
1] D Bits +] § Bits X Bits > BRC l E Bits i s ETEPePepeveve eb Tefeleb} EE EEETGT] RDR XER
0 Bit Switeh
Y Sor TD _, oO — D Bits A SC 10 of PORIOCO ¢ Bite
00 X Bits
4 E Bits
oTR/I >—1o 0 Bits > a ia > ‘SA Bits ‘ 0 RIS ro! — > | SB Bits o! ! | Spoaxse SORVIIO X Bits E Bits [de] Jo JoJo [oo] SA mso2614 ROR Siemens Aktiengeselischaft 54
a Function of the Receiver The IRC receiver is enabled by setting the ENFR bit to ‘1’. The receiver part of the IRC will search for the frame synchronization pattern. A status register tells the actual status of the receiver. The receiver also extracts the D-, S-, X- and E-bits and forwards them to their programmed destination. The received D-bits may be transmitted to the DCE interface. They are always transmitted to the Serial Communication Logic. The received S-bits may also be transmitted to the DCE interface. They are always transmitted to the SXS Status register. An interrupt is generated on every status change. The received X-bits are always transmitted to the SXS Status register and E-bits to the ES register. An interrupt is gener- ated on every X- or E-bit change. Figure 25 IRC Receiver Network Rate Intermediate Rate a <— IRC Receiver pee mux PO staus | S Bits BRC Detection ——| x Bits * Logic £ Bits h I 1 | $s RET RE] RE] REY RET RET RE FS] RS] RS (GEE GEEEEEED RDS SxS ES SYS | | | { IST:ROC EXIR:SXC EXIR:ESC IST:SYC rrso2615 Siemens Aktiengeselischaft 55
The IRC receiver reports its frame synchronization status in the SYS register. The most sig- nificant three bits are used. Table 23 shows the indicated states. Table 23 States of the IRC Receiver sys Fst _[Rs! |RSS |Status 1 No synchronization is achieved. Status while ENFR = 0 or after 1 or 3 incorrect frames. 1 1 0 Resynchronization impossible. Status after the number of frames specified in the NFR register were counted down without gaining synchronization. Oo 0 0 Synchronization achieved. Status after one correct frame has been received. If the IRC is enabled, it will always search for the synchronization pattern regardless of its actual state. If it finds the synchronization pattern it will change to RSS. Figure 25 illus- trates the state machine of the IRC receiver. Figure 26 Synchronization State Machine y—* Correct Frame SSS C@ 3 or 1 Incorrect Frame Incorrect Frame (up to NRF-1 frames) Ip, . 4EgN NG. 5 *A\\Ne & INNO & oe \\ &, s Ba\\S g Me rroo2s16 Siemens Aktiengeselischatt 56
Operational Description : a The IRC receiver will always output data even if FSL = 1. Therefore the data path should be selected after RSS has been detected. In case of a network rate of 64 kbit/s, FSL stays '1' and RSI, RSS are '0'. Remote DTE Status Indications The received S/SA- and D bits are evaluated by the remote DTE status logic. The de- tected combinations are reported by the RDS register. Changes in the RDS register set the RDC status bit in the IST register which may activate the INT output. The remote DTE status logic is in ‘no-state’ after reset. 'No-state' is indicate by a value of zero in the RDS register. The remote DTE status logic starts to sample the S/SA- and D- bits after ENFR has been set to '1’, regardless of the current synchronization status of the IRC receiver. The sampled data is compared against different possibilities after 16 D-bit samples were taken. If a match is detected the RDS register changes to the new value and the RDC status bit is set to '1’. If a status is detected which is different from LONX or LOFX, the remote DTE status detection logic will sample four D-bits before the pattern is varified again. If the status is no longer true, the RDS register changes to ‘no-state’ and the RDC status bit is set to ‘1. The next status indication will be indicated after another 16 D-bits have been sampled. If LONX or LOFX or no valid status is detected after 16 samples, the status detection logic will check its last 16 samples after every D-bit. The valid status are shown in table 24. Table 24 Remote DTE Status Indications Status | Status Name Sampled Data Register Bit RONX | Remote (X, ON) D XXXXXXKX XXXXXKXK Bit7 SISA 00000000 00000000 ROFX | Remote (X, OFF) D XXXXXXXX XXXXXXXK Bit6 {es 41199111 111111119 RON1 | Remote (1, ON) D 11111911 11111111 Bits S/SA 00000000 00000000 ROF1 Remote (1, OFF) ip 411177101 11177111 Bit4 S/SA 11111111 11111111 ROFO | Remote (0, OFF) to 00000000 00000000 java S/SA 11111111 11111111 } RL2 Remote Loop 2 Ip 00110011 00110011 [Bee | SISA 00000000 00000000 Siemens Aktiengeselischaft 57
For network rates which do not provide a S-bit (64 kbit/s; 56 kbit/s, F56 = 0), the value of the S/SA-bit in the remote DTE status detection logic is set to ‘1. The RDS register will only indicate ROFX, ROF1, ROFO. The remote DTE status detection may be used to detect the (S/SA = OFF, D = 0) condition which indicates a disconnect request according to V.110. Siemens Aktiengeselischaft 58
27 Bearer Rate Converter
The Bearer Rate Converter BRC transfers the output of the IRC onto the SNI and vice versa. The BRC is programmed to the first bit position on the SNI frame. The delay from the frame sync signal is programmed in a nine bit register, where the eight least significant bits are located in the TSR register and the most significant bit is located in the SCR register. For convenience the nine bit register is devided in the upper six bits which specify the time-slot number (time-slot width = 8 bit) and the least significant three bits specify the clock shift within the time-slot. Figure 27 BRC Transmitler SMI Time=Slot —» sox/DU SpR/DD CLK/OCL BRC Receiver FSC
7 Time-Slot
« LT iO. “I 02617 SOX/OU Number — t $——| Clock Width Shift The number of used bits per SNI frame depends on the programmed network rate and the resulting intermediate rate. Table 25 shows this relationship. Siemens Aktiengesellschaft 59
Number of Bits per Time Slot Network [intermediate | Number of Bit per Time Siot Rate Rate bits kbit/s 600 8 1 1200 8 1 2400 8 1 4800 8 1 9600 16 2 19200 32 4 38400 64 8 48000 |64. 8 56000 | 64. 8 64000 64 8 After the rising edge of the FSC signal has been received, the programmed number of clocks is counted down. During this time, a new edge of the FSC signal will have no effect. Siemens Aktiengesellschaft 60
28 Serial Communications Logic
The Serial Communication Logic (SCL) consists of an USART receiver and transmitter plus an HDLC receiver and transmitter. The data path for both transmitters and receivers can be selected independently. They may either be connected to the DCE interface or to the IRC. Each receiver and transmitter has its 9-byte FIFO to reduce the dynamic load on the microprocessor. Several status bits inform the microprocessor about the FIFO contents and possible errors on the received data. The FIFOs may be cleared or loaded either via the microprocessor or via direct memory access (DMA). The DMA logic may either be connected to the USART block or the HDLC block. A 20-bit counter is connected in paralle! to the USART receiver. It is used to generated periodical interrupts or to supervise the number of contiguous stop bits. This mode is used to supervise the guard time for the hayes modem protocol application. Figure 28 Serial Communication Logic Transmitter Receiver ‘Switch Switch HDLC USART HDLC HDLC Trans- Trans- Receiver Receiver a By aay 9 9B
9 Byte
The USART consists of a transmitter and a receiver block. It may either transfer a syn- chronous data stream (mono or bi-sync), transparent or an asynchronous data stream (start-stop characters). Synchron Operation The synchronous operation of the USART is selected by programming the ASYC bit in the USART mode register (UMR) to ‘0’. All received and transmitted characters have a length of 8 bit including a possible parity bit. The AICR register has to be set to '00'. Siemens Aktiengeselischaft 61
The USART receiver has two modes of operation: transparent mode and hunt mode. In the trafsparent mode, the receiver, when enabled, immediately starts storing received char- acter without regards of octets synchronization. In the hunt mode, the receiver searches for one (mono) or two (bi-sync) programmable synchronization characters before starting to store the received characters. The hunt mode and the transparent mode may be en- tered at any time by issuing the corresponding command in the UCC register. The selection between monosync or bisync operation is done by the SCM bit in the UMR. Table 26 shows the relationship. Table 26 USART Synchronous POperating Modes SCM Operating Mode
0 Bi-Syne
1 Mono-Syne
The synchronization character itself is written to the SYN register. After reset (either hard- ware reset or reset command) the USART receiver will be in hunt mode. The hunt mode is left, after the specified number of sync characters have been received. The following characters will be stored in the URFIFO, regardless whether they are sync characters or different ones. Figure 29 shows the receiver format. Figure 29 Receiver Data Format Synchronous Operation (Bi-Sync) | SYNC | SYNC Bataorsvnc _ f a _——— Oo URFIFO Synchronous Operation (Mono-Sync) SYNC Data or SYNC L H L fl 1 SSS eee URFIFO A parity check may also be performed on the received characters. The parity bit will al- ways be the most significant bit. Siemens Aktiengesellschaft 62
Table 27 shows the possible parity types. Parity check is enabled by setting the PTY bit in the UMR to ‘1. Table 27 Parity Types UMR PY1 _|PYO _|Parity Type 0 0 Fixed ‘0° re oO 1 ODD Parity 1 t) EVEN Parity 1 1 Fixed ‘1° Functions of the Transmitter When the transmitter is enabled, the transmission of any character entered in the UXFIFO is immediately started. All eight bits of the character are transmitted with the LSB first. A parity bit is not generated by the USART transmitter. If the UXFIFO runs empty, the trans- miter will repeatedly transmit the last character. Siemens Aktiengesellschaft 63
The asynchronous operation of the USART is selected by programming the ASYC bit in the USART mode register (UMR) to ‘1’. The character format and the number of stop bits are programmable in the AICR register. Figure 30 shows the asynchronous character for- mat. Figure 30 7 Asynchronous Character Format a Start Character Length Parity Stop Bit (n Bit) Bit Bit(s) (optional) AICR UMR CHL1 |CHLO | Character Length PTY [Py1 |PYo | Parity Bit i} 0 8 0 x x None O 1 7 1 0 0 Fixed ‘0° 1 0 6 1 t) 1 ODD Parity 1 1 5 1 1 t) Even Parity 1 1 1 Fixed "1 AICR:STP |No. of Stop Bits i) 1 . 1 2 The USART receiver will check only the first stop bit. The setting of the STP bit affects just the USART transmitter. The character format will be latched when the USART block is enabled or a reset com- mand has been issued. To change the character format on the fly it is necessary to issue a reset command after changing the AICR or UMR value. There must be no reset command if the total number of bits between the start and the stop bits remain the same (e.g. 8 bit, no parity — 7 bit, odd parity). Siemens Aktiengeselischaft 64
a Function of the Receiver When enabled (UMR:UREN = 1), the receiver searches for valid characters (startbit, char- acter bits, stop bit) and stores the characters in the URFIFO, stripping off the start and stop bit(s). A possible parity bit is stored in the URFIFO if the UFF bit Is set to ‘0’. The parity bit is stored as the bit immediately an the left of tha MSB. Thus the parity bit is transfered to the microprocessor. The parity bit is not avaitable for the microprocessor if the character format is 8 data bits + parity. Table 28 shows the character format in the URFIFO. Table 28 Character Format in URFIFO Character Length [Parity |SCR:UFF | Character Format in URFIFO 5 ne yes 0 0 0 D4 D3 D2 DI DO ves |1 | 0 0 P D4 D3 02 DI DO 6 no x yes 0 0 0 D5 D4 D3 D2 Dt DO _ lyes 1 0 P D5 D4 D3 D2 DI DO 7 no x yes 0 0 D6 D5 D4 D3 D2 D1 DO __ —_fyes [1 _P D6 D5 D4 D3 D2 DI DO 8 no x _ yes |x D7 D6 D5 D4 D3 D2 D1 DO It a parity error or framing error has been detected on a received character, the character is marked internally on the URFIFO. The corresponding status bit is set after the character has been read from the URFIFO. A break signal is received if M contiguous start bits are received if the USART receiver is connected to the DCE interface or after 2M-2 contiguous start bits if the USART receiver is connected to the IRC. The break begin and break end is indicated in two status bits in : the Special Condition Status. Siemens Aktiengesellschaft 65
Function of the Transmitter When the transmitter is enabled (UMR:UXEN = 1), the transmission of any character en- tered in the UXFIFO is immediately started. Characters are transmitted with the LSB first and separated by the selected number of stop bits. Characters may be entered in the UXFIFO even if the transmitter is not enabled. A status bit (USXE) indicates if the transmit- ter is empty. When the transmitter is empty contiguous '1' is transmitted until a new charac- ter is available. Asynchronous Bit Transparent Operation The bit transparent mode of the USART is similar to the transparent mode in the syn- chronous operation. All data is stored as octets without regards of a character format. The programmed character length, parity bit and number of stop bits have no significance. The receive clock is synchronized to every falling edge of the input signal. The bit transparent mode is entered by setting the BTM bit in the UMR register to ‘1'. FIFO Handling URFIFO Handling The USART receive FIFO (URFIFO) controls three status bits. Two additional status bits are used to indicate a framing error or parity error. The status bits and their meaning are shown in figure 31 and table 29. Siemens Aktiengesellschaft 66
URFIFO PER FER = -URD —-URFF_—_UURFO 17502618 Table 29 USART Receive FIFO Indications Status Bit |Register [Acknowledgement |Description OO URD RFS read URFIFO At least one byte is available in the URFIFO. URFF RFS read URFIFO All nine bytes in the URFIFO are occu- pied. A block of nine bytes may read from the URFIFO. URFO. .|SCS write to SCS A character which was completed in the | shift register could not be stored in the URFIFO because the URFIFO is full. PER RFS write to RFS A parity error has been detected on the last byte read from the URFIFO. FER RFS write to RFS A framing error has been detected on the _ ____|lastbyte read fromthe URFIFO. Figure 32 illustrates the URFIFO handling for an asynchronous data format of 7 bit + parity +1 stopbit. The 11th character got lost because the URFIFO was full. The DMA output request line DMOR will only go active if DMA is selected for the USART (GCR:DMA = 1 and GCR:DMH = 0). The DMOR line goes inactive after each read oper- ation to the URFIFO. It will go active again with the next rising edge of the internal data clock, if the read operation occured during the first half of the clock cycle or one clock period later if the read operation occured during the second half of the clock cycle. The DMOR line will not go active while the PER or FER status bit is set and the corresponding interrupt is enabled in the RFIE register. Siemens Aktiengeselischaft 67 :
uRFO i | H Ht Mor i [ H RD (URFIFO) T H (DACKD) i Read 1. Character 12.Character 13.Character vote Input I ET URD URFF URFO PER, FER H DMOR : i RD (URFIFO) T TTiitlt $+ s=CITIiit mczevg (OACKO) 2hor 3. 4 5. 6 7 |B O10 1213, t t Ackn.URFO Ackn. PER, FER Siemens Aktiengesellschaft 68
The USART transmit FIFO (UXFIFO) controls three status bits. The status bits and their meaning are shown in figure 33 and table 30. Figure 33 USART RTransmitter UXEIFO
9 Byle
UXSE -UXFE—UXW UXFIFO rrs02s20 Table 30 USART Transmit FIFO Indications Status Bit | Register | Acknowledgement |Description OO UXW XFS write UXFIFO At least one byte can be written to the UXFIFO. UXFE XFS write UXFIFO The UXFIFO is empty. A block of nine bytes may be entered into the UXFIFO. UXSE XFS write to XFS The USART Transmit Shifter is empty. This bit is set after the last stop bit has been transmitted. Figure 34 illustrates the UXFIFO handling for an asynchronous data format of 7 bit + parity + 1 stopbit. The DMA input request line (DMIR) will only go active after a USART DMA-start command (UDMS) has been issued and DMA is enabled (GCR:DMA = 1 and GCR:DMH = 0). The DMIR line is synchronized to the internal data clock. It will go inactive after a write oper- ation occured. It will go active again with the next clock cycle if the write operation oc- cured in the first half of the clock cycle or one clock cycle later if the write operation oc- cured in the second half of the clock signal. | Siemens Aktiengesellschatt 69
If DMA operation is selected for the USART but only a small number of bytes has to be transfered, it may not be efficient to setup the DMA-controller. In this case, the UDMS. command is also issued but the data is written into the UXFIFO under the control of the microprocessor (block-transfer). The DMA controller is disabled so that no data is trans- fered via DMA. Figure 34 UXFIFO Handling 1.Character 2.Choracter 3.Character Dota input ZZ ZZ ZZZAREZA oto cick FLIPLUA/UUUPUUUIL ULL. uxw i i UXFE | H l i UXSE i H i DMR WR (UXFIFO) ai t UOMS: UDMS (DMA only) sete input ZAR ZAZA EZZZZs i H H uxw Hi i H Hi i i UXFE it | UxSE H ———— OMIR H L WR (UXFIFO) q Wi002621 (DACK!) Siemens Aktiengesellschatt 70
a Counter A programmable counter is connected in parallel to the USART receiver. It is 20 bits wide and has two modes of operation. In the first mode (CTV2:CONT = 1) it will count down the programmed number of clocks regardless of the data signal. This will generate periodical interrupts. In the second mode (CTV2:CONT = 0) it will count down the programmed num- ber of stop bits. It will reload its value if a start bit has been received on the data signal. After the counter underruns (00 > FF) the CTUR status bit is set with the next clock. Thus the programmed value for the CTVO, CTV1, CTV2 registers is equal to the number of clocks — 2. The CTRN bit in the CTV2 registers controls the counter. The counter is active while the CTRN bit is ‘1’. If CTRN = 0, the counter is disabled. Every change from CTRN =0 to CTRN = 1 will reload the counter. Figure 35 Counter Network Rote ———o User Rate = ———9 Counter D Bits ——o Dato HMR:HRLC CTRN CONT EXIR:CTUR riso26z2 HDLC Controller The HDLC controller consists of a transmitter and receiver block. It supports CCITT-CRC (x164x12+x5+1). All data is transfered with the LSB first except for the CRC field. The CRC field is transfered with the MSB first. The input and output of the HDLC controller can be in- verted by setting the HINV bit in the HDLC Mode Register (HMR). Function of the HDLC Receiver The functions performed by the HDLC receiver are: — flag detection — zero deletion — CRC checking — check for abort - check for idle | Siemens Aktiengeselischaft 71
Function of the HDLC Transmitter The functions performed by the HDLC transmitter are: — Flag generation — Zero insertion — CRC generation — Abort sequence generation — Interframe time fill generation When the transmitter is enabled (HMR:HXEN = 1), the transmission of any bytes entered in the HXFIFO is immediately started, preceeded by an opening flag. To indicate the end of a frame, the microprocessor sets a control bit after having entered the last data byte of that frame in the HXFIFO. Every write operation of the bit serves as a frame delimiter. In DMA operation, this bit is controlled internally. The frame will be completed by the CRC- field and the closing flag if a data underrun condition is detected. When no data is available in the HXFIFO and the transmitter is enabled, interframe time fill bits are transmitted. Depending on the ITF bit in the HDLC mode register (HMR) the inter- frame time fill are continuous non-shared flags (HMR:ITF = 1) or continuous ‘1 (HMR:ITF = 0). When no DMA operation is selected and the HXFIFO becomes empty and the end-of- frame command was not issued, the transmitted frame is closed by an abort sequence and the HXDU status bit is set. When DMA operation is selected, the HXDU status bit indicates the end of a frame and the data for the next frame may be entered. Figure 37 Transmit HDLC Frame | Flag CRC Flag HXFIFO } HDLC FIFO Operation Both HDLC transmitter and receiver have a nine byte FIFO. The FIFO for the HDLC trans- miter is called HXFIFO, for the HDLC receiver HRFIFO. The FIFO bytes are not individ- ually addressable. All write operations to any of the XFIFO addresses will be added to the end of the FIFO. All read operations to any of the HRFIFO addresses will read the first byte from the HRFIFO. Siemens Aktiengesellschaft 73
The HDLC receive FIFO (HRFIFO) controls three status bits. Two additional status bits in- dicate the end of a frame. The status bit and their meaning are shown in figure 38 and table 32. Figure 38 HDLC Receiver oa HRFIFO HRFIFO RME HRD HRFF—-HRFO MER mrso2s2s Table 32 HDLC Receive FIFO Indications Status Bits | Register | Acknowledgement | Description HRD RFS read HRFIFO. At least one byte is available in the HRFIFO. HRFF RFS read HRFIFO. All nine bytes in the URFIFO are occu- pied. A block of nine bytes may be read from the HRFIFO. HRFO scs write to SCS The start of a frame could not be stored in the HRFIFO due occupied HAFIFO. Thus at least one entire frame was lost. RMER RFS write to RFS Receive Message End Reception This bit is set after the receiver status byte was written into the HRFIFO. RME RFS write to RFS Receive Message End This bit is set after the last byte of a frame _ _|(RSTA) has been read from the HRFIFO. Siemens Aktiengesellschaft 74
The DMA output request line DMIR will only go active if DMA is selected for the HDLC controller (GCR:HMR = 1 and GCR:DMH = 1). The DMOR line goes inactive after each read operation to the HRFIFO. It will go active again with the next rising edge of the inter- nal data clock if the read operation occured during the second half of the clock cycle. The DMOR line will not go active while the RME status bit is set. The EODR pin will go active if DMA is selected. Siemens Aktiengeselischaft 75
The HDLC transmit FIFO (HXFIFO) controls three status bits. The status bits and their meaning are shown in figure 39 and table 33. Figure 39 HDLC Transmitter HXFIFO ’ ’ HXDU HXFE HXW HXFIFO XME wsoz6ze Table 33 HDLC Transmit FIFO Indications Status Bits | Register | Acknowledgement |Description HXW XFS write HXFIFO At least one byte can be written to the HXFIFO. HXFE XFS write HXFIFO The HXFIFO is empty. A block of nine bytes may be entered into the HXFIFO. HXDU XFS write to XFS non-DMA operation: The HDLC transmitter became empty without an end-of-frame command. The frame was aborted. | DMA operation: { The HDLC transmitter has completed a frame. A new frame may be written to the HXFIFO after entering a HDMS com- | mand. HXDU must be acknowledge before the next HDMS command is issued. Siemens Aktiengesellschaft 76
Data Path Selection for the SCL Each receiver and transmitter block may either be connected to the DCE interface or to the IRC. The selection for the receiver blocks is done by the HMR:HRLC bit. If this bit is set to ‘0’, the USART receiver, including the counter, is connected to the DCE interface. The HDLC receiver is than connected to the IRC receiver. If HMR:HRLC is set to '1', the con- nections are vice versa. Table 34 Receiver Data Path Selection HMR:HRLC | USART Receiver! [bata [Data [HDLC [Data _—| Data Counter ‘Signal Clock Receiver | Signal Clock
0 DCE TxD user IRC received | network
interface rate receiver |'D' bits rate
1 IRC received j|network | DCE TxD user
receiver 'D' bits rate interface rate Figure 40 Data Path for the Receiver Blocks oce 10 > 2 1; -——— <4 Rec. 0 Bits 0o p oO pl 00 »p pl HMR:HRLC USART HOLe Receiver Receiver wso2625 Siemens Aktiengeselischaft 77
A similar switch is used to connect the transmitter blocks. The transmitter blocks are con- trolled by the HMR:HXLC bit. Table 35 Transmitter Data Path Selection HMR:HXLC | USART Data Clock HDLC Data Clock Transmitter Transmitter
0 DCE user rate network rate
Data Path for the Transmitter Blocks RxD MUX User Rate » t D Bit MUX | po Te etwork Rate HMRSHALC f { USART HOLC Transmitter Transmitter Ts07626 Siemens Aktiengesellschatt 78
29 Test Loops
The ITAC provides three test loops. Test loop 3b connects the output of the IRC to its input. No data is output to the SDX/DU line. Data on the SDR/DD input has no effect on test loop 3b. To run test loop 3b it is necessary to have a clock and FSC signal on the SNI and the TSR register must be programmed to a valid time-slot within the frame. Test loop 3b is con- trolled by the TL bit in the DPCR register. Figure 42 Test Loop 3b Intermediate Bearer HL Syne sox/ou Rate Rate Network sor/00 Converter Converter Interface CLK/DCL (IRC) _} (eRc) ] (SNI) Fsc 802627 Test loop 2b connects the output of the ASC (GCR:ASY=1) or the IRC (GCR:ASY=0) to its input. The signal on the RxD output is specified by the RDC1,0 bits of the DPCR register. Test loop 2b loops back the D-bit information of the received data stream. The S-, X-, E- and frame synchronization bits are not looped. Figure 43 Test Loop 2b TxD TxD Asyne/ Intermed. DCE Async/ Intermed. Syne Rote Inter Syne Rate Converter | | Converter face Converter | | Converter RxD (asc) (ike) Rx0 (asc) (IRC) Dotapath Configuration Datapath Configuration 17902828 Test Loop 2b (GCR:ASY=1) Test Loop 2b (GCR:ASY=0) Siemens Aktiengesellschaft 73
Connections of RxD While Test Loop 2 is Active RDC1 RDCO Function 0 0 XD is equal to the value of LOR:RD 0 1 RxD originates from the Serial Gommunication Logic 1 0 RxD transmits the received D bits (which are looped back) A third test loop is available via a bit 0 of the test register 1. While bit 0 is '1', the data of the programmed time-slot received from the SNI is looped back after the BRC. At the same time, the output of the IRC is looped back to its receiver. The BRC receives a continuous data stream from the SNI which has no indication of the Start of the time slot. Thus, an octet aligned loop is not guaranteed. It is recommended to use HDLC formatted data to test this loop. Siemens Aktiengeselischaft 80
2.10 Interrupt Logic
The status of a certain block or control lines are reported to the microprocessor via status registers. A change of any status bit can be used to activate the interrupt output (INT). This indicates to the microprocessor that it has to service the ITAC. The INT output is level ac- tive. If an interrupt is pending, the INT line is low. The INT output is open drain which allows to connect more than one interrupt sources to the input of the microprocessor. Interrupt Structure Figure 44 shows the interrupt structure. The INT output is controlled by the Interrupt status enable register (ISEN). A '1' in a bit position of the ISEN enables the corresponding status bit of the IST to generate an interrupt. The four most significant bits of the IST register are controlled by their own enable regis ters. These bits are only set if a bit in the corresponding status register is active and cleared after the corresponding status bit has been cleared or the interrupt has been dis- abled. Siemens Aktiengesellschatt 81
H H (SEN Ist |_| | | H H H |_| [| im SCEN secs MFIE XFS RFIE RFS Counter |_| ‘STIE H ‘STR | | ae Siemens Aktiengeselischaft 82
Control of Edge -Triggered Interrupt Controllers The INT output is level active. It stays active until all interrupt sources have been ser- viced. If a new status bit is set while an interrupt is serviced, the INT line stays active. This. may cause problems if the ITAC is connected to edge-triggered interrupt controller (figure 45). To avoid these problems, it is recommended to mask all interrupts at the end of the inter- Tupt service program and to enable the interrupts again. This is done by writing ‘00' to the ISEN register and to write back the old value of the ISEN register (figure 46). Figure 45 INT Handling 1 3 \\ ‘ INT | f 5 2 4 1 Astatus bit is set. This causes an interrupt. 2 The microprocessor starts its service routine and reads the status registers. 3 Anewstatus bit is set before the first status bit has been acknowledged. 4 The first status bit is acknowledged.
5 The INT output stays active but the interrupt controller will not serve the
interrupt edge (edge triggered). Siemens Aktiengesellschatt 83
Service Program for Edge -Triggered Interrupt Controllers 1 3 ‘ 1 INT 4 tt tot { 2 45 6 7 8 9 1 to 4 see above. 5 00is written to the ISEN register. This masks all interrupts and returns the INT output to its inactive state. 6 The old value is written to the ISEN register. This will activate the INT output if an interrupt source is still active. 7 The microprocessor starts a new interrupt service program. 8 The last status bit is acknowledged. 9 The INT output is inactive. ‘Siemens Aktiengeselischaft 84
211 Reset State
The ITAC is in the reset state after the application of a reset pulse on RST. The minimum pulse width is 2 microseconds. In the reset state, all configuration registers are zeroed and all interrupts are disabled. The synchronous network interface and the DCE interface outputs are tri-state.
2.12 Standby State
The ITAC may be set in a standby state to save unnecessary power consumption when idle. This is controlled by the power-up bit in the GCR register. It GCR:PU = 1 the ITAC is in normal operation. All blocks are active. If GCR:PU = 0 the ITAC is in standby mode. De- pending on the selected DCE interface mode, two cases are distinguished. The characteristics of the standby status are shown in table 37. Table 37 Standby Status Output or Function __[X21(GCR:v24=0) —[V.24 (GCRV24=1) Microprocessor Interface | Operational Operational Oscillator Disabled Disabled Other Logic Disabled DTR detection enabled RxD Previous state Previous state s Logical 1 or tri-state Logical 1 or tri-state Other DCE outputs Previous state Previous state ‘SDX ee Tri-state _ a Tristate For an X.21 interface, switching between standby and operational is ‘only subject to the state of the control bit PU (Power Up). The oscillator reaches a stable state within 10 ms after the PU bit is set to one. In the V.24 case, standby is reached when PU is set to zero and DTR (108) interchange circuit is OFF. When DTR is switched ON, the standby state is left, an interrupt is gener- ated and the PU bit is set to one by internal logic (figure 47). Siemens Aktiengeselischaft 85
Standby State Diagram (GCR:V24 = 1) GCR:PU=0, OTR(108)=OFF(1) ~ __ rroo2ss0 GCR:PU=1 or DTR(108)=ON(0) Action:GCR:PU=1
213 Initialization
After reset, the user has to write a minimum number of registers to set the ITAC into an operational state. The most important among these are: — General Configuration Register (GCR) — Bit Rate Selection (BRS) — Data Path Selection Register (DPCR) — Local DCE interface Register (LDR) Interrupts are enabled via the ISEN register. The microprocessor may switch the ITAC into operational state at any time, not necessar- ily at initialization - unless a clock is required by the local DTE - but say, upon detecting an incomming data call. Also the automatic wake-up feature can be used in the case of an outgoing call. Note that switching between standby and operational does not affect the contents of the registers. Siemens Aktiengeselischaft 86
2.14 Internal Delays
The delay through the different block of the ITAC depends on there FIFO structures and functions. Table 38 and 39 shows the delays. Table 38 Transmit Delays (DCE — SNI) Block No. of Clock Relevant Clock Rate - ty max. ASC 16 User rate IRC | 9 Network rate BRC | ee le ___| Intermediate rate Table 39 Receive Delays (SNI — IRC) Block LE No.of Clocks _| Relevant Clock Rate BRC 8 Intermediate rate IRC 9 Network rate ASC 2M+16 User rate Siemens Aktiengesellschaft 87
a
3 Detailed Register Description
The parameterization of the ITAC and the transfer of data and control information between the uP and the ITAC is performed through a set of registers. Table 40 to 48 list the address map of the ITAC registers and the summary according to the type of the registers. In order to facilitate a direct connection to 16-bit processors, all registers of the ITAC can be accessed using even or odd microprocessor addresses. Siemens Aktiengesellschaft 88
a Table 40 ITAC Address Map ca “ (hex) ‘ane [Beeipion Na [Osoin 00-0F |HRFIFO | HDLC Receive FIFO HDLC Transmit FIFO 40-1F | URFIFO | USART Receive FIFO UXFIFO | USART Transmit FIFO 20,21 [IST |interuptStatus Register I IST Acknowledge Register 22, 23 JExIR [Extended interupt Register| EXIA | EX Acknowledge Register 24-28 |_| reserved 20, 20 reserved Test Register 2 2E,2F I reserved SS TEST1 | Test Register 1 30, 31 Local DTE Status Register CounterValueOQ 38,39 |SXS | S-and X-Bit Status Register reserved 3A, 38 E-BitStatus Register reserved 30, 3D [RFs | Receiver and RFIFO Status Register | AFSA | RFS Acknowledge Register _ 42,43. |MOSR_ | MONITOR Channel Status Register MOSA | MOS Acknowledge Register 44,45 Staus Register —=—=S=S*~C*S*«*~SSTRAX~_*| STR Acknowledge Register 46, 47 Status Register Interrupt Enable Register - OO 48,49 | ISEN _| intorupt Status Enable Register 4A, 4B Receiver and RFIFO Interrupt Enable Register 46,40 |XFIE | Transmitter and XFIFO Interrupt Enable Register 4€, 4F Special Condition Interrupt Enable Register 52, 53 ‘Special Configuration Register Siemens Aktiengeselischaft 89
Table 40 (cont'd) Address Write (hex) Name |Description Name | Description 84,55 ‘Async. Interface Configuration Register 56,57 [pPcR | Data Path Configuration Register Oo 58,59 [HMR | HDLC Mode Register SA, 5B [uMR | USART Mode Register 5C, 5D [Moc | MONITOR Channel Configuration Register 5E,5F [BRS _|BitRate Select 60, 61 Time-Siot Register 62,63. [NFR | Number of Retry Frames Register 64, 65 LOR Local DCE Control Register 66, 67 [por | Remote DCE Control Register 68, 69 Transmit E-Bit Register cA68 |_| reserved 6C, 6D reserved Hoc — |HOLC Controller Command Register 6E,6F | reserved uce | USART Controller Command Register 70,71 [NSC _| insert Character Register 72,73 [| reserved 74,75 MONITOR Channel Receive Register | MOX1 | MONITOR Channel Transmit | Register 76,77 Synchronization Character Register 78,79 |LCAR1 | Local Character 1 7A,7B —|LCAR2 | Local Character 2 : 7C,7D | RCAR1 | Remote Character 1 7E, 7F RCAR2 | Remote Character 2 Siemens Aktiengesellschaft 90
FIFO and Transfer Register Summary 7 o 00 - oF [ usp tT ts8 | HRFIFO R 00 - OF ps TO Tiss | HxFIFO W \\ ! \\ ! 10-1F feet iss | URFIFO R L \\ \\ \\ \\ \\ 10-4F [we TT isp | UXFIFO W L \\ \\ l nl \\ \\ \\ ! m7 [use FT TS iss} MORI R mi [usp! FFT isp | Moxt = W Siemens Aktiengesellschatt a1
20,21 [| Lc noc | svc | ext | AF | xF | sc | Ist R A A A STA. Ww 22,23 | sxc | esc | mosc | strc | cTuR 1 1 EXIR oR A A A EXIA Ww 30,31 { otr | ats | mi | Miz 1 Los oR (V24=1) 30,31 { LONo | LoFo1| LLs 1 1 los oR (v24=0) 32, 33 | LONX [ tore | ton] LOFt | toro | ue | 1 1 | els AR 34, 35 | RONX | ROFX | RON1 | ROM] nore | iz | ROFO 4 1 | RDS oR 36, 37 | Fst | Rsi | Ass | 0 1 | vwe [| vn1 | wNo | sys A 38,39 |RS/RSA| RSB [™ | 4 1 | 1 1 1 SxS oR 3a,98 [ REt | RE2 | RES | “RES | RES Ree | RE? | 1 | ES R 3c,30 [HRD | URD | HRFF | URFF | RMER| AME | FER | PER | RFS = R A A A A_| RFSA Ww 3e,3F | Hxw | Uxw | HXFE | UxFE | HXDU 1 1 XFS oR A XFSA WW 40,41 | HRFO] URFO|) BAB | BRE | tc | Lc2 | Aci | Rc2 | scs A A A A A A A A A_| ScSA W 42,43 1 | 4 + | + | mor | MeR | MDA | maB | MosR oR A A A A_| MOSA Ww 44,45 {cac | cis | ALA | tole | ACHR | RDB ovs | sTR oR A A A_| STRAW -- RDO | cA | RAB | 0 o | vez | ver | veo | ASTA(HRFIFO) Siemens Aktiengesellschatt 92
a Table 43 Interrupt Enable Register Summary 7 0 46,47 [Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable] STIE = RW cac_| cis | RLA | WLe | ACHR | ADB | XDB | OVS 4a,49 [Enable | Enable | Enable | Enable | Enable | Enabie | Enable | Enable | (SEN RW toe | upc | ADC | svc | ext | AF | xXF | SC 4A,48 | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enabie| AFIE = RW HRO | URO | HRFF | URFF | AMER | AME | FER | PER 4c,40 | Enable | Enabie | Enable | Enable | Enable | Enable XFIE = RWW wxw | uxw | Hxee | uxre | HxDU | UXSE 4e,4F [Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | SCIE RAW “pro | unro | ere | ere | Lor | ice | Rci | Rc2 Table 44 Configuration Register Summary 7 0 50, 51 [ pu | DOE [vp | AsY [err DMA | DMH | GOR RW 52,53 [= Res | F56 | pe. | op | srs | scr RW 58,59 fic | wate HREN | HXEN | HINV | ITF i HMR RAW l 5A.5B | ASYC a | ures UxEN | SCM [ ] pyo | BTM | UMR = RW 56, 5D [ towe | ox | xs | SAW a a | xc | MOCR RWW se.sF | UR3 | uR2 | UR1 | URO | NAS | NR2 | NAY wo | BRS AW 60.61 | Ts4 ] 183 | Ts2 | Ts1 | Tso | Ics2 | cst 1080 | TSR RW 62,63 [” oe] 8 Na | no [| N2 NI No NRF RW i | Siemens Aktiengesellschaft 93
64, 65 [pcr] 5" | cts | ap | mot | mo2 V Lor AW 66,67 ssa] 358 | xX [* ] ~ ROR RW 68,69 | XEt [= | xes | x4 | XES [= [= | | XER RW 32,33 [ons erie | cTit cts | om ow s4a5 [| | CTRN cms on | ore | cre Ww I Table 46 Command Registers 7 0 6c,6D | HAR | HxR | XME | HDMS Hoc w — . L Siemens Aktiengesellschaft 94 F
a Table 47 Constant Registers 7 Oo a TT tsp | SYN RW 78,79 | MSB —T tsp | LcaR1 RW mm {usst | FO TO ise | LcAR2 RW i ! ! wz. fuse! | | TO iss | RCAR1 RW L ! L ve7e [spt SO TT iss | RCAR2 RW Table 48 Test Registers 7 ° 2c, 2D J qv Test2. Ww a ee ee ee ee ee 2e2F | v v \\ Testi W es ee es ee ee Siemens Aktiengesellschaft 95 wo
34 FIFO and Transfer Registers
HDLC Receive FIFO (HRFIFO) Address: 00 - OF Read Value after Reset: FFH 7 0 MSB T uss | HAFIFO i Ll Ll 1 | Any address combination between 00x and OFH will read the next byte from the HDLC receive FIFO. USART Receive FIFO (URFIFO) Address: 10 - 1FH Read Value after Reset: FFH 7 0 [ use T rs rs re | 8] Le a Any address combination between 10H and 1FH will read the next byte from the USART receive FIFO. HDLC Transmit FIFO (HXFIFO) Address: 00 - OFH Write Value after Reset: FFH 7 0 LS a Any address combination between 00H and OFH hex will write at the end of the HDLC transmit FIFO. USART Transmit FIFO (UXFIFO) Address: 10 - 1FH Write Value after Reset: FF 7 0 MSB v T qv T I LsB i 1 | Any address combination between 10H and 1FH will write at the end of the USART transmit FIFO. Siemens Aktiengesellschaft 96
Character Insert Register (INSC) Address: 70, 714 Read/Write Value after Reset: 00H 7 0 | MSB LsB Ses ee a eS Ss eo ee Eee The character written into the INSC register will be inserted in the data stream to- wards the DCE interface at the next opportunity. Received characters are not pertubed. The status of inserting the character is indicated by the STR:CIS status bit. MONITOR Data Receive Register (MOR) Address: 74, 751 Read Read Value after Reset: 00H 7 i) L \\ L Contains the last byte received from the MONITOR channel handler. MONITOR Data Transmit Register (MOX1) Address: 74, 751 Write Value after Reset: 00H 7 ° {mse v q Misa po The value written into the MOX1 register will be transmitted by the MONITOR channel handler if the MOCR:MXC bit is '1". Siemens Aktiengeselischaft 7
3.2 Status Registers
Status bits of the ITAC are not cleared after the corresponding register has been read. Status bits with the indication 'A’ have to be acknowledged. This means that a '1' has to be written into the register address to reset the status bit. The acknowledgement of a status bit has to occur before the status is evaluated and the pointed register is read. This proce- dure asures that no status change gets lost. Interrupt Status Register (IST) Address: 20, 214 Read Value after Reset: 00H 7 0 unc | toc | Roc | svc | ex | AF xF | sc a | oA A A LDC __Local DTE Status Change Indicates that at least one bit in the LDS register has changed since the last ac knowledgement. This status bit must be acknowledged. ELDC Extended Local DTE Status Change Indicates that at least one bit in the ELDS register has changed since the last ac- knowledgement. This status bit must be acknowledged. RDC Remote DTE Status Change Indicates that at least one bit in the RDS register has changed since the last ac- knowledgement. This status bit must be acknowledged. syc Synchronization Status Change Indicates that at least one bit in the SYS register has changed since the last ac- knowledgement. This status bit must be acknowledged. ext Extended Interrupt Indicates that at least one bit is set in the EXIR register. RF Receiver and RFIFO Status Indicates that at least one bit in the RFS register has changed since the read operation. Siemens Aktiengesellschaft 98
XF Transmitter and XFIFO Status Indicates that at least one bit in the XFS register has changed since the read operation. sc Special Condition Status Indicates that at least one bit in the SCS register has changed since the read operation. EXtended Interrupt Register (EXIR) Address: 22, 23: Read Value after Reset: 07H 7 ° [sxc | esc |. Mosc | strc | ctuR| 1 1 1 A A A SXC S-and X-Bit Status Change The SXC bit is set if a change has occured on the received S- or X-bits. This status bit must be acknowledged. ESC _E-Bit Status Change The ESC bit is set if a change has occured on the received E-bits. The status bit must be acknowledged. MOSC MONITOR Channel Status Change The MOSC bit is set if a change has occured in the MONITOR status register. The status bit is cleared after the changes in the MOSR register are acknowl- edged. STRC Status Register Change The STRC bit is set, if a change in the STR register has occured and the corre- sponding interrupt enable bit is set. This bit is cleared after the changes in the STR register are acknowledged. CTUR Counter Underrun The CTUR status bit is set with a delay of one clock cycle after the counter under- runs (00 — FF). When the counter underruns, it will automatically reload the value of the counter registers. The CTUR status bit must be acknowledged. Siemens Aktiengesellschaft 99
Local DTE Status Register (LDS) Address: 30, 31H Read Value after Reset: --H Non-X.21 (GCR:V24 = 1) 7 ° DTR | RTS pm pM | Mis 1 1 1 DTR Data Terminal Ready interchange circuit state. 1: DTR = 'OFF' (1) 0: DTR = 'ON' (0) RTS Request To Send interchange circuit state 1: RTS = ‘OFF (1) 0: RTS = 'ON' (0) MI1-3 Multifunctional Input circuit states 4: Mix =‘OFF" (1) 0: Mix = ‘ON’ (0) X.21 (GCR:V24 = 0) 7 ) LONo torus To | o | 4 1 1 LONO Local (0, ON) state LOFO1 Local (0101..., OFF) state LL3 Local Loop 3, Local (00001111..., OFF) state Extended Local DTE Status (ELDS) Address: 32, 334 Read Value after Reset: 03H 7 ° LoNnx | LOFX | LONI | tor: | toro | 2 1 1 “significant only in X.21 mode (GCR:V24 = 0) LONX Local (X,ON) state LOFX Local (X,OFF) state LON1 Local (1,ON) state LOF1 Local (1,0FF) state LOFO Local (0,OFF) state LL2 Local Loop 2, Local (0011...,OFF) state Siemens Aktiengesellschaft 100
Remote DTE Status (RDS) Address: 34, 351 Read Value after Reset: 03H 7 0 [om ROFX | RON1 | ROF1 | ROFO | AL2 | 1 1 RONX Remote (X,ON) state ROFX Remote (X,OFF) state RON1 = Remote (1,ON) state ROF1 Remote (1,OFF) state ROFO Remote (0,OFF) state RL2 Remote Loop2, Remote (0011...,OFF) state Synchronization Status (SYS) Address: 36, 371 Read Value after Reset: 8DH 7 0 Fst | Asi | RSS 0 1 vn2 | VN1 | VNO FSL Frame Sync Loss The intermediate rate receiver has detected at least one or three consecutive frames with erroneous frame synchronization pattern. After frame sync loss was detected, the value programmed in NRF frames is counted down, before a RS! status is generated. RSI ReSynchronization Impossible The intermediate rate converter has not achieved synchronization within the number of frames which has been programmed in the NRF register. The IRC re- ceiver continuous to search for the frame synchronization pattern. RSS ReSynchronization Successful The intermediate rate receiver has achieved synchronization after a FSL or RSI status. Siemens Aktiengesellschaft 101
VN2 VN1 VNO_ Version 1 1 914 At 1 1 0 BI 1 0 1 V2.2 S- and X-Bit Status (SXS) Address: 38, 391 Read Value after Reset:1FH . 7 ° RS/RSA Received S- or SA-Bit If (GCR:V110 = 0):S If (GCR:V110 = 1): SA 1: received S/SA-bit was 1 0: received S/SA-bit was 0 RSB Received SB-Bit “significant only if GCR:V110 =1 1: received SB-bit was 1 0: received SB-bit was 0 RX Received X-Bit 1: received X-bit was 1 0: received X-bit was 0 Siemens Aktiengesellschaft 102
a E-bit Status (ES) Address: 3A, 3BH Read Value after Reset: 01H 7 0 REI rez | RES [™ Res | Ree | RE7 " RE1-7 Received E-Bits RE7 is always 1 for NR = 600 bit/s Receiver and RFIFO Status (RFS) Address: 3C, 3DH Read/Write Value after Reset: 00H 7 0 { HRD | URD | HRFF | URFF | RMER | AME | FER | PER — [LA lA Aj A HRD HDLC Receive Data available The HRFIFO contains at least one byte. URD —_USART Receive Data available The URFIFO contains at least one character/byte. HRFF HDLC Receive FIFO Full All 9 bytes of the HRFIFO are occupied. At least one byte must be read before the next one is completed in the shift register. Otherwise a SCS:HAFO status is generated. URFF USART Receive FIFO Full All 9 bytes of the URFIFO are occupied. At least one byte must be read before the next one is completed in the shift register. Otherwise a SCS:URFO status bit is generated. RMER Receive Message End Reception This bit is set after the receiver status byte was written into the HRFIFO. It indi- cates that the end of a frame is stored in the HRFIFO. This status bit must be ac- knowledged. Siemens Aktiengesellschaft 103 ,
Register Description . RME Receive Message End This bit indicates, that the byte previously read from the HRFIFO was the last byte of a frame. This status bit must be acknowledged. FER Framing Error “active only if UMR:ASYC = 1 and HMR:HRLC = 0. The USART receiver detected a framing error (missing stop bit) on the byte pre- viously read from the URFIFO. This status bit must be acknowledged. PER Parity Error “active only if UMR:PTY = 1 while receiving the character. The USART receiver detected a parity error on the byte previously read from the URFIFO. This status bit must be acknowledged. Transmitter and XFIFO Status (XFS) Address: 3E, 3FH Read/Write Value after Reset: 07H 7 0 Hxw | uxw | HxFE | uxre | HxDU [os | 1 1 | A HXW HDLC Transmit FIFO Write enable At least one more byte can be written into the HXFIFO. UXW —_-USART Transmit FIFO Write enable At least one more character can be written into the UXFIFO. HXFE HDLC Transmit FIFO empty The HXFIFO is empty. Up to nine bytes can be written into the HXFIFO. UXFE —USART Transmit FIFO empty The UXFIFO is empty. Up to nine bytes can be written into the UXFIFO. | Siemens Aktiengesellschaft 104
a HXDU HDLC Transmit Data Underrun Non-DMA: All data from the HXFIFO was transmitted and no HCC:XME (transmit message end) command was issued. The frame will be closed with an abort sequence. The HXDU status bit is set during the transmission of the last bit from the last byte. DMA: The HXDU bit indicates that the RME bit has been generated internally and the frame will be closed by the CRC field and the closing flag. A new frame may be started by writing the HDMS command after the HXDU bit has been acknowl- edged. This status bit must be acknowledged. UXSE USART Transmit Shifter Empty The USXE bit indicates that the USART shifter is empty. If asynchronous operation of the USART is selected (UMR:ASY = 1 and UMR:BTM = 0), the USXE bit will be set to '1' after the last stop bit has been trans- mitted and no further data is available in the UXFIFO. If asynchronous bit transparent mode is selected (UMR:ASYC = 1, UMR:BTM = 1), the UXSE bit will be set after the last data bit has been transmitted and no fur- ther data is available in the UXFIFO. If synchronous operation is selected (UMR:ASYC = 0), the USXE bit will set after the last bit of the last byte has been transmitted. During idle-state it will stay ‘1’ al- though the last byte will be transmitted continuously. The USXE bit will be cleared after a new data byte has been transfered from the UXFIFO to the shift register. The UXSE bit is active both in DMA and in non- DMA operation. The UXSE bit is not acknowledgeable. It will generate an inter- rupt, if XFSE:EXSE = 1 and ISEN:XF = 1. Siemens Aktiengesellschaft 105
Special Condition Status (SCS) Address: 40, 414 Read/Write Value after Reset: 00H 7 ° HRFO | URFO| BRB | BRE | Lc1 | Lc2 | RCI | RC2 A | ALA A | A A A A HRFO HDLC Receive FIFO Overflow The start of a frame could not be stored in the HRFIFO due to a filled HRFIFO. Thus at least one entire frame was lost. This status bit must be acknowledged. URFO USART Receive FIFO Overflow A character which was completed in the receiver shift register could not be stored in the URFIFO due to a filled URFIFO. This status bit must be acknowl- edged. BRB Break Signal Begin This bit is set if the USART receiver has detected 2M-2 bits of start polarity if it is connected to the network side (IRC receiver) or M bits of start polarity if it is con- nected to the DCE interface. This status bit must be acknowledged. BRE Break Signal End This bit is set when the first stop bit is received by the USART receiver after a BRB status indication. This status bit must be acknowledged. Lei Local Character 1 recognized The character programmed in the LCAR1 register has been recognized from the local DTE. This status bit must be acknowledged. Lc2 Local Character 2 recognized The character programmed in the LCAR2 register has been recognized from the local DTE. This status bit must be acknowledged. RC1 Remote Character 1 recognized The character programmed in the RCAR1 register has been recognized from the received D-bits. This status bit must be acknowledged. Siemens Aktiengesellschaft 106
RC2 Remote Character 2 recognized The character programmed in the RCAR2 register has been recognized from the received D-bits. This status bit must be acknowledged. MONITOR Channel Status Register (MOSR) Address: 42, 431 Read/Write Value after Reset: 00H 7 ° 1 1 1 1 mor | MER | MDA | MAB MDR = MONITOR Channel Data Received A new data byte is available in the MORI register. This status bit must be ac- knowledged. MER MONITOR Channel End of Reception The end of reception condition has been recognized by the MONITOR channel handler. This status bit must be acknowledged. MDA = MONITOR Channel Data acknowledge The opposite side has acknowledged the transmitted data byte written into MOX1. This status bit must be acknowledged. MAB MONITOR Channel Data abort The opposite side has aborted the transmitted data written into MOX1. This status bit must be acknowledged. Siemens Aktiengesellschaft 107
Status Register (STR) Address: 44, 45H Read/Write Value after Reset: -H 7 ° cac | cis | ALA | IDLE | RCHR| RDB | xDB | OVS [va A | A A CAC Command Accepted The bit must be polled before a HRR, HXR, HDMS, URR, UDMS, SBK, HNT and TRA command is issued. After a command was accepted, this bit is set. Writing any of the previous commands will set the CAC bit to ‘0’ until the command is ac- cepted. During this period no further command may be written into the HCC or UCC register. cis Character insertion Successful 1: The character written to INSC has been inserted in the received character stream (to the DCE interface). Another character may be inserted using INSC. 0: The character written into INSC has not been inserted yet. A write operation to INSC may overwrite the insertion character. RLA Receive Line active 1: HDLC flags or messages are being received by the HDLC receiver. 0: Neither flags nor messages are being received. IDLE Idle State on the HDLC received data 1: At least 12 consecutive '1' have been detected by the HDLC receiver. 0: No idle state. RCHR Receive Character detected 1: At least on start bit was detected from the DCE interface since the last acknowledgement. 0: Only stop bits have been received from the DCE interface since the last acknowledgement. This status bit must be acknowledged. Siemens Aktiengeselischaft 108
RDB Receive Data Byte (from SNI) This bit is set after every eighth bit in the received X.30/V.110 frame (P8, Q8, R8 or D8, D16, D24 ...) when SYS:RSS = 1. This status bit must be acknowledged. XDB Transmit Data Byte (to the SNI) This bit is set after every eighth bit in the transmitted X.30,V.110 frame (P8, Q8, R8 or D8, D16, D24 ...) when ENFR = 1. This status bit must be acknowledged. Ovs Overspeed This bit is set if the ASC receives a data stream where the data rate exceeds the selected tolerance range. At least one bit in the output data stream has been lost. This status bit must be acknowledged. Receive HDLC Frame Status Byte (RSTA) Address: --H Value after Reset: --H 7 0 RDo | cRC | RAB ° 0 ve2 | vei | veo The Receive HDLC Frame Status Byte is not accessable via a register address. It's value is added to the data of the received frame as the last byte. RDO Receive Data Overflow 1: At least one byte of the message could not be stored due to an occupied HRFIFO. CRC CRC Check correct 1: No CRC error has been detected in this frame. RAB Receive Abort 1: An abort sequence was received. Siemens Aktiengeselischaft 109
VB2-0 shows the valid bit count of the last received byte. VB 210 0 00=1Bit 001=2Bit 0 10=3Bit 011=4Bit 100=5Bit 101=6Bit 110=7Bit 111=8Bit
3.3 Interrupt Enable Registers
Interrupt Status Enable Register (ISEN) Address: 48, 49+: Read/Write Value after Reset: 00H 7 0 Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable Loc | Etoc | rpc | syc | ex RF XxF sc A'1' in a bit of the ISEN enables the interrupt from the corresponding bit position of the IST register. If an interrupt is disabled, the bit in IST will still indicate the status and thus disabled interrupts may be polled. Receiver and RFIFO Interrupt Enable Register (RFIE) Address: 4A, 4BH Read/Write Value after Reset: 00H 7 0 Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable HRD | URD | HRFF | URFF | AMER | RME | FER | PER A‘1' in a bit of the RFIE enables the status in IST (IST:RF) being activated by the corresponding bit in the RFS. If an interrupt is disabled, the bit in RFS will still in- dicate the status and thus disabled interrupts may be polled. Siemens Aktiengeselischaft 110
Transmitter and XFIFO Interrupt Enable (XFIE) Address: 4C, 4DH Read/Write Value after Reset: 00H 7 0 — —_ Enable | Enable | Enable | Enable | Enable | Enable Hxw | UXW | HXFE | UXFE | HXDU | UXSE At’ in a bit of the XFSE enables the status in IST (IST:XF) being activated by the corresponding bit in the XFS. If an interrupt is disabled, the bit in XFS will still indicate the status and thus disabled interrupts may be polled. Special Condition Interrupt Enable Register (SCIE) Address: 4E, 4F1 Read/Write Value after Reset: 00H 7 i) Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable HRFO | URFO| BRB | BRE | LC1 | Lc2 | ACt | RC2 A'1' in a bit of the SCIE enables the status in IST (IST:SC) being activated by the corresponding bit in the SCS. If an interrupt is disabled, the bit in SCS will still in- dicate the status and thus disabled interrupts may be polled. Status Register Interrupt Enable (STIE) Address: 46, 47 Read/Write Value after Reset: 00H 7 0 Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | cac | cis | ALA | IDLE | RCHR| RDB | XDB | OVS ‘At’ in a bit of the STIE enables the status in EXIR (EXIR:STRC) being activated by the corresponding bit in the STR. If an interrupt is disabled, the bit in STR will still indicate the status and thus disabled interrupts may be polled. Siemens Aktiengeselischaft 411
3.4 Configuration Register
General Configuration Register (GCR) Address: 50, 51H Read/Write Value after Reset: 00H 7 0 a a a a la PU Power-Up 1: ITAC is in power-up state. 0: ITAC is in power-down mode. DOE DCE Interface Output Enable 0: all output pins of the DCE interface are tri-state. 1: all output pins are operating. v24 V.24 or X.21 Control lines Selects the meaning of the DCE interface control lines and the meaning of the LDS status register. 0: X.21 interchange circuits 1: V.24 interchange circuits V110 Mapping of S bits 0: S bits are mapped according to X.30. 1: S bits are mapped according to V.110 ASY Selects asynchronous or synchronous DCE interface operation 0: Synchronous DCE interface. The data transfer over the DCE interface is synchronized by the clock signal ‘supplied by the S clock output. The ASC is inactive. 1: Asynchronous DCE Interface The ASC is active and no clock signal is output on S. The synchronization is performed on each received start bit. Siemens Aktiengeselischaft 112
ENFR Enable frame output to the Synchronous Network Interface 0: No frames are transmitted to the SNI. The receiver is inactive. The status dit in the SYS-register are set to FSL = 1 and RSI = 0. 1: Frames are generated and output to the SNI. The receiver searches for the frame pattern. ENFR = 1 will become active after the next FSC signal. ENFR = 0 will tri-state the SNl-interface regardless of the current position in the frame. Caution: ENFR = 1 should be programmed after the DPLL is locked and the network rate, the frame format and the active time slot has been programmed. Changes of the network rate, frame format or active time slot needs the ENFR bit to be cleared for ‘one clack cycle of the previous intermediate rate. DMA __ Controls the DMA block 0: DMA interface is inactive. The DMA request outputs are tri-state. 1: DMA interface is active as selected by the DMA bit. The DMA request outputs are push-pull outputs. DMH Selects DMA mode for USART or HDLC controller 0: DMA interface is connected to the USART. 1: DMA interface is connected to the HDLC controller. Siemens Aktiengeselischaft 113
Special Configuration Register (SCR) Address: 52, 531 Read/Write Value after Reset: 00H 7 0 TSS Time-Slot Select MSB TSS holds the value of the most significant bit of the time-slot register. 0: The value of TSR accesses time-siots 0 - 31. 1: The value of TSR accesses time-slots 32 - 63. DLL Selects Double Last Lock for S-bit mapping. *RSC must be '1" 0: Receive status bit changes are mapped to the DCE interface directly. 1: Receive status bit changes are mapped to the DCE interface after two identi- cal values (double last lock). The contents of the SXS register is changed im mediately. LCS Selects Local Character Stop 0: The characters programmed in the LCAR1 and LCAR2 registers are not removed from the data stream. 1: The characters programmed in the LCAR1 and LCAR2 registers are deleted. ‘Stop bits are transmitted instead of the character bits. RCS Selects Remote Character Stop 0: The characters programmed in the RCAR1 and RCAR2 registers are not removed from the data stream. 1: The characters programmed in the RCAR1 and RCAR2 registers are deleted. Stop bits are transmitted instead of the character bits. F56 Selects the frame format for a user rate of 56 kbit/s (according to V.110). 0: Bit 8 of the 64 kbit/s channel is filled with ‘1’. 1: Bit 8 of the 64 kbit/s channel is filled with the pattern ‘0 X SASB 1111". Siemens Aktiengeselischaft 114
ed DCL bit selects the type of clock signal used on the serial network interface 0: CLK is a single bit clock signal (one clock period per data bit). 1: CLK is a double bit clock signal (two clock periods per data bit). This will switch to 1OM-2 timing. oD Open Drain Output The OD bit specifies the operation of the SDX/DU output. 0: The SDX/DU driver is push-pull during the selected time-slot bits. 4: The SDX/DU driver is open-drain during the selected time-siot bits. An exter- nal pull-up resistor is required. The SDX/DU output is always tri-state during the inactive time-slot bits. SFS Single Frame Sync loss 0: The Frame Sync Loss (FSL) status is set after three incorrect frame sync pat- terns have been detected. 14: The Frame Sync Loss (FSL) status is set after one incorrect frame sync pattern has been detected. Siemens Aktiengeselischatt 115
Async Interface Configuration Register (AICR) Address: 54, 55H Read/Write Value after Reset: 00H 7 tL) CHL cHio | ste ™ | UROF | — T | I CHL1-0 Character Length CHL1 CHLO Character Length 0 0 eight bits 0 1 seven bits 1 0 six bits 1 1 five bits The character length does not include a possible parity bit. STP Stop Bits. 0: One stop bit per character. 1: Two stop bits per character. This selection affects only the transmit direction. in receive direction only the first ‘stop bit is checked. TR Tolerance Range of the ASC 0: Normal tolerance range (12,5 %). Every 8th stop bit may be removed from the data stream. In transmit direction the length of the stop bit is reduced. 1: Extended tolerance range (25 %). Every 4th stop bit may be removed from the data stream. In transmit direction the length of the stop bit is reduced. URDF URFIFO Data Format 0: The received parity bit is stored in the URFIFO. 1: The received parity bit is not stored in the URFIFO. Siemens Aktiengeselischaft 116
Data Path Configuration Register (DPCR) Address: 56, 57H Read/Write Value after Reset: 00H 7 0 [ Roct | poco 7001 | x00 asc | xsc | T2 | 713 Any change in the DPCR is active after the data bits D8, D16, D24, D32, D40, 48 in transmit direction when ENFR = 1, in receive direction when RSS = 1. If ENFR = 0 the change is active after the next intermediate rate period. RDCO-1 Receive Data Connect Selects the path for the RxD output pin of the DCE interface. RDC1 RDCO 0 i) RxD is connected to the register bit RD 0 1 RxD is connected to the Serial Communication Logic 1 ) RxD is connected to the D-bits 1 1 reserved XDCO-1 Transmit Data Connect Selects the path for the input of the IRC transmitter. xDC1 XDCO 0 0 D-bits are equal to the register bit XD 0 1 D-bits originate from the Serial Communications Logic
1 VY) D-bits originate from TxD
0: Received S/SA, SB bits (from the SNI) are written to the register. 1: Received S/SA, SB bits (from the SNI) are additionally mapped onto the DCE interface interchange circuits. xsc Transmit S-Bit Connect 0: Transmitted S/SA,SB bits (to the SN) originate from the ROR register. 1: Transmitted S/SA,SB bits (to the SNI) are mapped from the DCE interchange circuits. Siemens Aktiengesellschaft 17
TL2 Test Loop 2 activation 0: Normal operation 1: Test loop 2 is active. The received data from the network interface is looped back at the output of the IRC (sync DCE-Interface) or ASC (async DCE-Inter- face). TL3 Test Loop 3 activation 0: normal operation 7 1: Test loop 3 active. The loop indside the BRC is closed. The output of the BRC is looped back. HDLC Mode Register (HMR) Address: 58, 591 Read/Write Value after Reset: 00H 7 ° HRLC HDLC Receiver to Local DCE Connection 0: The USART receiver is connected to the DCE interface. The HDLC receiver is connected to the IRC. 4: The USART receiver is connected to the IRC. The HDLC receiver is con- nected to the DCE interface. HXLC HDLC Transmitter to Local DCE Connection 0: The USART transmitter is connected to the DCE interface. The HDLC transmit- ter is connected to the IRC. 1: The USART transmitter is connected to the IRC. The HDLC transmitter is con- nected to the DCE interface. HREN HDLC Receiver Enable 0: The HDLC receiver is inactive. 1: The HDLC receiver is active. Siemens Aktiengeselischaft 118
HXEN HDLC Transmitter Enable 0: The HDLC transmitter is inactive. 1: The HDLC transmitter is active. Any data entered into the HXFIFO will be transmitted. HINV HDLC Inverted 0: The data stream of the HDLC transmitter and receiver is not inverted. 4:The data stream of the HDLC transmitter and receiver is inverted. ITF Interframe Time Fill 0: Continuous ones are transmitted as interframe time fill. 4: Non-shared flags are transmitted as interframe time fill. USART Mode Register (UMR) Address: 5A, 5BH Read/Write Value after Reset: 00H 7 ° [as pry | UREN | UxeN| scm | PY1 | Pyo | BT™ | ASYC Asynchronous mode 0: The USART operates in synchronous mode. 1: The USART operates in asynchronous mode. PTY Parity 0: parity check / generation disabled. 1: parity check / generation enabled. The parity type is specified by bits PYO-1. UREN USART Receiver Enable 0: The USART receiver is disabled. 1: The USART receiver is enabled. Siemens Aktiengesellschaft 119
UXEN USART Transmitter Enable 0: The USART transmitter is disabled. 1: The USART transmitter is enabled. SCM = Synchronous Communication Mode “significant only in synchronous operation (ASYC = 0) 0: Bisyne operation of the USART receiver. 1: Monosyne operation of the USART receiver. PYO-1 Parity Type *PTY has to be set '1' to enable parity check / generation PY1 PYO Parity type 0 0 0 0 1 odd 1 te) even 1 1 1 BIM Bit Transparent Mode *ASYC must be set to '1' 0: Normal operation of the USART. 1: Bit transparent mode of the USART. Siemens Aktiengeselischaft 120
a MONITOR Channel Configuration Register (MOCR) Address: 5C, 5DH Read/Write Value after Reset: 00H 7 0 tome | cIx6 cixs | saw | MRE wrc | mic | Mxc 1O0M2 1OM2 Mode Selection 0: MONITOR channel handler is disabled, CIX5, CIX6 and SAW have no affect. Time-slot 7 and 8 are not influenced. 14: MONITOR channel handler is enabled. CIX5, CIX6 and SAW are active. CIX6 = Commandi/indicate Transmit Bit 6 “significant only if IOM2 = 1 0: C/I 6 of IOM channel 1 is set to '1'. 1: C/I 6 of IOM channel 1 is set to ‘0’. CIX5 — Command/indicate Transmit Bit 5 “significant only if IOM2 = 1 0: C/I 5 of IOM channel 1 is set to '1’. 1:C/15 of IOM channel 1 is set to '0'. SAW Software Awake *significant only if IOM2 = 1 0: Normal operation of the SDX/DU output. 1: Software awake function of the IOM-2 interface. The SDX/DU output will be forced to low while the following condition is true: FSC"IOM2*SAW = 1. MRE MONITOR Channel Receiver Enable *significant only if IOM2 = 1 0: The MDR interrupt is masked. 1: The MDR interrupt is enabled. The MCR bit controls the generation of the MOR interrupt. | Siemens Aktiengesellschaft 421
MRC = MONITOR Channel Receiver Control *significant only if IOM2 = 1 0: The transmitted MR-bit is always ‘1’. The MDR interrupt is generated only for the first byte of a message. 1: The MR-bit is controlled by the MONITOR channel! handler. The MDR interrupt is generated when a new MONITOR data byte has been received. The MR-bit performs the acknowledgement after the MOR1 register has been read. MIE MONITOR Channel Interrupt Enable *significant only if OM2 = 1 0: The interrupts of the status bits MER, MDA and MAB are masked. 1: The interrupts of the status bits MER, MDA and MAB are enabled. MXC —- MONITOR Channel Transmitter Control “significant only if (OM2 = 1 0: The MX-bit is always ‘1’. The MONITOR channel transmitter is inactive. 1: The MX-bit is controlled by the MONITOR channel handler. The transmitter outputs the MONITOR channel data byte from the MOXt register and performs the proper handshake. The MER, MDA and MBA status bits report status changes. Siemens Aktiengeselischaft 122
Bit Rate Select (BRS) Address: 5E, 5FH Read/Write Value after Reset: 00H 7 —_ _ — urs | UR2 [* uro | NR3 | NR2 wer] NRO URO-3 User Rate Specifies the user rate. UR3 UR2 UR1 URO User rate ASYNC DCE-IF = SYNC DCE-IF 0 0 0 0 300bit/s x = o 0 0 1 600bil/s x x 0 0 1 0 1200bit/s x x 0 0 1 1 2400bit/s x x 0 1 0 0 4800bit/s x x i} 1 0 1 9600bit/s x x oO 1 1 0 19200bit/s x x i) 1 1 1 38400bit/s x x 1 0 oO 0 48000bit/s - x 1 0 0 1 56000bit/s - x 1 0 1 0 64000bit/s - x
1 O 1 1 reserved
: Siemens Aktiengeselischaft 123
Specifies the network rate. A change of these bits becomes active after the ENFR bit has been cleared for one clock cycle of the previous intermediate rate. NR3 NR2 NR1 NRO Network rate Intermediate rate ) 0 0 ° - - () 0 0 1 600bit/s 8000 bits 0 i 1 0 1200bit/s 8000 bits 0 0 1 1 2400bit/s 8000 bit/s 0 1 0 O 4800bit/s 8000 bit/s 0 1 0 1 9600bit/s 16000 bit/s 0 1 1 0 19200bit/s 32000 bit/s 0 1 1 1: 38400bit/s 64000 bit/s 1 0 O te) 48000bit/s 64000 bit/s 1 0 0 1 56000bit/s 64000 or 56000 bit/s 1 0 1 oO 64000bit/s 64000 bit/s 1 i} 1 1 reserved - 1 1 x x reserved - ‘Siemens Aktiengeselischaft 124
Time-Slot Register (TSR) Address: 60, 61H Read/Write Value after Reset: 00H 7 0 | ts3 | ts2 | Ts1 | Tso | Ics2 | Icst | Icso | TSO-4 Time-slot Select Selects the active time-slot on the SNI. If TS5 is ‘0’, TSO-4 specifies a time-slot between time-slot 0 to 31. If TS5 is '1', TSO-4 specifies a time-slot between time slot 32 to 63. ICSO-2 Intermediate Rate Channel Select Selects the position of the first bit used by bearer rate converter within the speci- fied time-siot. Number of Retry Frames (NRF) Address: 62, 631 Read/Write Value after Reset: 00H 7 0 N7 NG NS Na no | N2 Nt NO Specifies the number of frames between a FSL status change and the generation of the RSI status. Siemens Aktiengesellschaft 125
3.5 Control Registers
Local DCE Control Register (LDR) Address: 64, 65H Read/Write Value after Reset: 00H 7 i) Goal DSR os | #0 | wor | woe DCD/ State of the DCD/I (109) interchange circuit *significant only if DPCR:RSC = 0 0: DCD/ is ‘ON’ (0). 1: DCD/lis ‘OFF’ (1). DSR State of the DSR (107) interchange circuit “significant only if DPCR:RSC = 0 0: DSR is ‘ON' (0). 1: DSR is ‘OFF’ (1). cis State of CTS (106) interchange circuit 0: CTS is ‘ON’ (0). 14: CTS is OFF’ (1). RD State of the RxD (104) data circuit 0: RxD is ‘0’. 1: RxD is 1". MO1-2 State of the multifunctional outputs MO1, MO2 0: MOx is ‘ON’ (0). 1: MOx is ‘OFF’ (1). Siemens Aktiengesellschaft 126
Remote DCE Control Register (RDR) Address: 66, 67H Read/Write Value after Reset: 00H 7 0 XSKSA| XSB | XX XD XS/XSA Value of the transmitted S/SA bit *significant only if DPCR:XCS = 0. 0: Transmitted S/SA-bit is ‘ON’ (0). 1: Transmitted S/SA-bit is ‘OFF (1). XSB Value of the transmitted SB bit *significant only if DPCR:XSC = 0. 0: Transmitted SA-bit is ‘ON’ (0). 1: Transmitted SA-bit is ‘OFF’ (1). XX Value of transmitted X bit 0: Transmitted X-bit is 'ON' (0). 1: Transmitted X-bit is ‘OFF’ (1). xD Value of the transmitted D bits *significant only if DPCR:XDC1-0 = 00. 0: Transmitted D-bits is '0'. 1: Transmitted D-bits is '1". Transmitted E-Bit Register (NER) Address: 68, 69+ Read/Write Value after Reset OOH 7 i) xer | xe2 xes | xE4 | xes | xE6 | XE7 LL a ee es en on eo Value of the transmitted E bits in the intermediate rate frame. The value of XE7 has no meaning if the network rate is set to 600 bit/s. In this case E7 is controlled by the ITAC internally. Siemens Aktiengesellschaft 127
3.6 Command Registers
The synchronization status of both the HCC and UCC commands are reported by the STR:CAC status bit. It must be polled before a new value is written into the HCC or UCC register. HDLC Controller Command Register (HCC) Address: 6C, 6DH Write Value after Reset: 00H 7 0 HRR | HXR | XME HOMS HRR ~~ HDLC Receiver Reset The HDLC receiver is reseted. The HRFIFO is cleared and the DMOR-line becomes inactive if the DMA controller is connected to the HDLC controller and DMA is enabled. HXR —_-HDLC Transmitter Reset The HDLC transmitter is reseted. The HXFIFO is cleared and the DMIR-ihe becomes inactive if the DMA controller is connected to the HDLC controller and DMA is enabled. XME Transmit Message End XME acts as a frame delimiter. XME marks the last byte in the HXFIFO as the last byte of a HDLC frame. After the HDLC controller has transmitted this byte, it will add the CRC field and the closing flag. HDMS DMA start for the HDLC transmitter “significant only if GCR:HMH = 1 and GCR:DMA = 1. HDMS will start the generation of DMIR requests. After entering the first byte in the HXFIFO, the HDLC transmitter will start to transmit a frame. The HDLC frame will be closed by the CRC field and the closing flag if the HDLC transmitter becomes empty. Siemens Aktiengesellschaft 128
USART Controller Command Register (UCC) Address: 6E, 6FH Write Value after Reset: 00H 7 0 uRR | UXR o | upms | sex | HNT } TRA — i —_ URR USART Receiver Reset The USART receiver is reseted. The UXFIFO is cleared and the DMOR-line becomes inactive if the DMA controller is connected to the HDLC controller and DMA is enabled. UXR USART Transmitter Reset The USART transmitter is reseted. The UXFIFO is cleared and the DMIR-line becomes inactive if the DMA controller is connected to the HDLC controller and DMA is enabled. UDMS DMA start for the USART transmitter “significant only if GCR:HMH = 0 and GCR:DMA = 1. UDMS will start the generation of DMIR requests. SBK Send Break *significant only if ASYC = 1. If the send break command (SBK — UCC) is issued, the output of the USART transmitter is set to ‘0' regardless of any character currently transmitted. The out- put will stay ‘0’ until a new command is entered with the SBK bit set to ‘0’. HNT Set Hunt Mode *significant only it ASYC = 0. Forces the USART to search for sync character(s) before starting to store data re- gardless of any data being received at this time. The hunt mode is default after reset or UCC:URR = 1. TRA Set Transparent Mode “significant only if ASYC = 0. Enables the USART to store received data without searching for character syn- chronization. Siemens Aktiengesellschaft 129
Counter Value 0 (CTV0) Address: 30, 31H Write Value after Reset: 00H 7 0 | cr cTé | crs, crs | cT3 [or [on | cTo Counter Value 1 (CTV1) Address: 32, 33H Write Value after Reset: 00H 7 0 fers | cra | cra ore | ore ctto | ct9 | cre Counter Value 2 (CTV2) Address: 34, 354 Write Value after Reset: 00H 7 0 | ; fo] cont | cT19 | ctis | cm17 | ome CTO-19 Counter Value 0-19 Specify the number of bits which are counted down before the CTUR status bit is set. CTRN Counter Run 0: Counter is stopped. 1: Counter is active. CONT Continuous Operation 0: The counter is reloaded with every start bit. 1: The counter counts down regardless of the received data bits. Siemens Aktiengesellschaft 130
3.7 Constants and Special Character Registers
Synchronization Character Register (SYN) Address: 76, 774 Read/Write Value after Reset: 00H 7 0 jw T ~T TT TT TT T ise pt L \\ *significant only if UMR:ASYC = 0 In the hunt phase of the USART receiver it searches for one or two characters of the value stored in the SYN register before it stores characters in the URFIFO. Local Character 1 (LCAR1) Address: 78, 791 Read/Write Value after Reset: 00H 7 0 pe TT L \\ L L 1 Local Character 2 (LCAR2) Address 7A, 7BH Read/Write Value after Reset: 00H 7 0 a 3B | vse rT iss | ee es a ee Characters received by the DCE interface are compared with the programmed value of the LCAR1 and LCAR2 register. Upon a match, the SCS:LC1 or SCS:LC2 status bit is set. If SCR:LCS is set to '1', the character bits are replaced by stop bits. In case of a character length less than eight bits, the unused bits of the LCAR1 and LCAR2 register must be set to ‘1’. Siemens Aktiengesellschaft 131
Remote Character 1 (RCAR1) Address: 7C, 7D Read/Write Value after Reset: 00H 7 0 MsB i y I "iss Remote Character 2 (RCAR2) Address: 7E, 7F Read/Write Value after Reset: 00H 7 oO MSB ' I "sp L ! \\ 1 Characters received by from the IRC receiver are compared with the pro- grammed value of the RCAR1 and the RCAR2 register. Upon a match, the SCS:RC1 or SCS:RC2 status bit is set. If SCR:RCS is set to '1', the character bits are replaced by stop bits. In case of an character length less than eight bits, the unused bits of the RCAR1 and RCAR2 register must be set to '1'. Siemens Aktiengeselischaft 132
a
38 Other Registers
Test Register 1 (TEST1) Address: 2E, 2FH Write Value after Reset: 004 7 0 [ a | I L This register is reserved for factory testing. Bit 0 controls a test loop located between the IRC and the BRC. It loops the out- put of the IRC to its input and the output of the BRC to its input. Note that there is no octet alignment provided by the BRC loop. Thus it is unlikely that the data received by the IRC will be transmitted with the same alignment on the B-channel. It is recommended to use a serial bit-oriented protocol like HDLC for testing the BRC loop. Test Register 2 (TEST2) Address: 2C, 2DH Write Value after Reset: 00H 7 0 ee ee ae This register is reserved for factory testing. The user should not write to this regis- ter. Siemens Aktiengeselischaft 133
Electrical Characteristics
4 Electrical Characteristics
Absolute Maximum Ratings . Parameter Symbol Limit Values Unit [min (rma Voltage on any pin with respect to | V. -04 Voo +0.4 v ground DC Characteristics Ta=0to 70°C; Voo=5V45%,Vss=0V Parameter Symbol [ Limit Vaiues | Unit | Test [max. | Condition Linputvoltage | Vu fos | Vv — Allpins H-input voltage vw Voo Vv +0.4 L-output voltage Vo 0.45 Vv To=2mA All pins ex- cept DU/SDX H-output voltage Vou Voo Vv Tou =— 100 pA | -0.5 Power | power- Toc 07 |mA |Voo=5V;in- | Voo supply | down puts at 0 V or voltage V0; No output loads; CLK = 0 MHz operational mA |Voo=5 V; in- puts at 0 V or | Voo; no output | loads; | CLK = 4 MHz Output leakage lo 10 pA OV<Vm<Voo current Siemens Aktiengellschaft 134
Ta=25 °C; Voo=5 V+ 5 %, Vss = 0 V; fo = 1 MHz, unmeasured pins grounded a Parameter Symbol | Limit Values | Unit Input capacitance cw 7 pF All pins except XTAL1, 2 W/O capacitance Cw 7 pF Load capacitance cu 50 pF XTAL1,2 Recommended Oscillator Circuits Figure 48 Oscillator Circuits “ External ll XTALL Oscillator — ->— TALI d 10.752 MHz =a l | | «| xrave Ne. xTal ia Crystal Oscillator Mode Driving from External Source vrso7968 Crystal Specification _ __ __ Parameter ‘Tsymbol | Limit Values unit Frequency f 10.752 MHz Frequency calibration tolerance |_| max. 100 ppm Oscillator mode fundamental Note: The load capacitance C. depends on the recommandation of the crystal specifica- tion. Typical values for Cx are 18 .. 22 pF. Siemens Aktiengelischaft 135
Ta=0t0 70°C; Voo=5V+5% Inputs are driven to 3.0 V for a logical '1' and to 0.4 V for a logical '0'. Timing measure- ments are made at 2.0 V for a logical '1' and at 0.8 V for a logical ‘0’. The AC testing input/output waveforms are shown below. Figure 49 Input/Output Waveform for AC Tests 2 20 Device Test Points Under 08 08 Test 4 if C tyo¢= 150 pF sasass Siemens Aktiengelischaft 136
« ty hee | wo0-7 AX Figure 53 DMA Write Cycle DMIR fe oo TXT
Microprocessor Interface Timing Parameter Symbol] _LimitValues [Unit ‘nin mae. ‘Address setup time to ALE fn | 2a | | ns ‘Address hold time from ALE ta jo | ns ‘Address hold time toread lta 0 ns Address holdtimetowrte iiiw | 0 | {ns Data output delay from RD [two | 100 ms RD ule wih Ca 1 RDcontrolinteval stm | 85 ns WRopulsewidth Eww 1000 rs Data setup time to WR x CS tow 300 ss Data hold time from WRxCS [two | 10 ns WR control interval lw | 88 | ns DMA request to acknowledge [tom | 0 | ns DMA request inactive delay ee ee ns DMA request hold delay tom [35 [ns DACKholdafterwrte itm |B ns Interrupt acknowledge to tri-state [fur | ~~ |r00 [ns Siemens Aktiengellschaft 139
Synchronous Network Interface Figure 55 PCM Interface Timing ——* oe a —<— yy cuk/oet | \\ les 35 =], ~ ineicaie nical | FSC r \\ f AQ or Open-Drain ery so SOs Te ro02s36 Parameter pre | Limit Values | Unit GILKIBGL period [i= [aes [rm [re H-CLK period ts 100 ns L-CLK period - 7 tw 100 nm Frame sync setup trss 40 ns Output data from high impedance to active [too | ————«([t00__—i[ns Output data delay from CLK [too | sf tC ns Output data from active to high impedance tooz 80 ns Input data setup ___| ties 20 - ns Input data hold ton a) ns Note: fm = Intermediate Rate Period Siemens Aktiengellschaft 140
1om®-2 Interface Timing De] CLK/DCL i fess. fisw. fess fisu rc NN | te fos || how foo ae Ys 03/0 TM wo02657 Parameter =~ ~~: | Symbol Limit Values | Unit ___[rrin. max. _ CLK/DCL period te 244 tinl4 ns Output data from high impedance to active | tow __ 100 ns Output data delay from CLK tooo —_fr00 [ns Output data from active to high impedance _| fooz 80 ns Input data setup [tos | ns Input data hold [ton | 40 | ns Note: fin = Intermediate Rate Period Siemens Aktiengelischaft 141
‘Synchronous DCE Interface Timing s el ty | RxD —™) fas hy «002638 Parameter Symbol Limit Values |Unit | Test Condition T x D setup time tr User rate <> 56 kbit/s T x D setup time tis 7000 User rate = 56 kbit/s Siemens Aktiengelischaft 142
5 Application Note Summary
The following paragraphs describe application information for the ITAC. They cover the topics ® connecting the ITAC to the ISAC-S via SSI © support of the V.110 by the ITAC. @ autobauding @ alternative solution for autobauding © octet aligned data transfer at 64 kbit/s
51 Connecting the ITAC® (PSB 2110) to the ISAC®-S (PEB 2085) via SSI
The SSI Interface of the ISAC®-S The SSI interface serves as a full duplex connection to B-channel sources/destinations in terminal equipment at a data rate of 128 kbit/s. It consists of one data line for each direction (transmit and receive), a 8-kHz frame syn- chronization signal and a 128-kHz clock signal. The default polarity of the frame syn- chronization signal is such that it is high during the transmission of channel B2 and low during the transmission of channel B1. Figure 60 Signals of the SS! Interface SDAX a TO ST SDAR SS TT seyeso TTT FSC1/FSC2 __I LJ \\roozse1 Siemens Aktiengeselischaft 144
The Serial Network Interface of the ITAC® The serial network interface of the ITAC also consists of four lines. One data line in each direction (transmit and receive), a frame start signal and a data clock signal. The network interface is defined as a time-siot oriented interface. Each time-slot has the fixed width of eight bits. Six bits, five in the TSR and one in the SCR register, specify the time-slot which is used for transmission and receiption. The number of used bits within the time-slot is determined by the programmed network rate (BRS:NRO-NR9). If the network rate is less or equal to 4800 bit/s, the bearer rate converter uses one bit of the time-slot. If the network rate is 9600 bit/s, the bearer rate converter uses two bits of the time-slot. If the network rate is 49200 bit/s, the bearer rate converter uses four bits of the time-slot. If the network rate is greater or equal to 38400 bit/s, the bearer rate converter uses all eight bits of the time-slot. The start position within the time-slot is programmed by bits ICSO - ICS2 in the TSR register. Ics2.ICS1_ICSO___ Start position 0 oO i} bit O i 0 1 bit 1 0 1 O bit 2 O 1 1 bit 3 1 0 0 bit 4 1 0 1 bit 5 1 1 0 bit 6 1 1 1 bit7 Siemens Aktiengesellschaft 145
Assignment between SSI and SNI SNI eS ssi eS 7 sca ck fl FSC1/2, FSC _ _I woo26es Programming the ISAC®-S In the ISAC-S, the ADFR register is programmed to default polarity of the FCS signal. This is done by setting bit 1 to ’0' if FSC1 is used or setting bit 2 to '0' if FSC2 is used. ADFR=x x xxxx0x for FSC1 ADFR=x xx xx 0x x for FSC2 The SPCR register must be set to connect the used B channel to the SSI interface. This is done with the B1C1, B1CO bits for channel B1 and with the B2C1, B2CO bits for channel B2. SPCR=x x x x10x x for B1 to SSI SPCR=x xx xx x10 for B2 to SS! Siemens Aktiengesellschaft 147
Programming the ITAC® In the ITAC, the TSR, the SCR, the BRS and the GCR register must be programmed. The TSR register specifies the used B-channel and the start position of the used bits within the time-slot. TSR=00001 ICS2 ICS1 ICSO for B1 TSR =00000 ICS2 ICS1 ICSO for B2 The TSS bit in the SCR register must be set to zero. SCR=0 x x x x 00x The network rate is selected by the NRO - NR bits in the BRS register. BRS =x x x x NR3 NR2 NR1 NRO The number of used bits depends on the selected network rate as described before. The ENFR bit in the GCR register controls the output of the network interface. If ENFR = '0', the SDX output is tri-state for all positions in the selected time-slot. The re- ceiver is inactive. it ENFR = '1', the SDX output sends data at the programmed bit Positions within the se- lected time-slot. The receiver receives data at the programmed bit positions within the se- lected time-slot. Important Note The ITAC needs a maximum time of 84 ms to synchronize the internal clock to the FSC sig- nal after the ITAC is powered up by the PU bit in the GCR register or after the position of the frame start signal has changed. Therefore it is recommended to select B1 or B2 in the ITAC by changing the TSR register and not by changing the FSC polarity in the ISAC-S. Siemens Aktiengesellschaft 148
5.2 ‘Support of V.110 by the ITAC® This chapter describes the register settings for the ITAC to implement chapter four of the V.110 recommendation (blue book version). The chapter numbers are according to the ones used in the recommendation. 4 Operation sequence. 44 TA-A duplex operation. 4.1.1 Idle state. 4.1.1.4. During the idle (or ready) state the TA (DCE) will be receiving the following from the DTE: . Circuit 103 (TxD) = ‘1" Circuit 105 (RTS) = ON Circuit 108/1 = OFF; Circuit 108/2 (OTR) = ON This is inputed to the ITAC DCE interface and may be checked using the LDS register.
4.1.1.2 During the idle state the TA will transmit continuous binary 1s into the B- and D-
channels. Therefore, the output of the SNI must be disabled. This is done by setting GCR:ENFR = 0
4.1.1.3 During the idle state the TA (DCE) will transmit the following toward the OTE:
) Circuit 104. (RxD) = ‘1 Circuit 107 (DSR) = OFF Circuit 106 (CTS) = OFF Circuit 109 (DCD) = OFF This is done by setting LDR == _‘1111xx00' b,'FO' hex DPCR = '00xx0x00'b,'00' hex ) Siemens Aktiengeselischaft 149
Setting all bits to zero in the DPCR registers means to connect the control and data output lines of the DCE interface to the register bits of the LDR register. Since they are set to one, the output at the DCE pins is also high and thus these lines are 'OFF'. Note: The LDR register must be programmed before the GCR:DOE (DCE Output Enable) bit is set to one. If the DOE bit is set to one before the LDR register is programmed, the output pins will go low for a short moment which will be interpreted as a start bit. Thus an unknown character may be received by the terminal. 4.1.2 Connect TA to line state.
4.1.2.1 Switching to the data mode causes the TA to transmit the following toward the
ISDN: a) Frame synchronization pattern, as follows: - octet 0 = all binary 0 ~ bit number one of octets 1-9 = binary 1 b) Data bits = binary 1 c) Status bits S = OFF and X = OFF This is done by setting: BRS:NR3-NRO0 to the corresponding network rate RDR_ = ='11110000' b,'FO" hex DPCR = 'xx00x000' b,'00' hex GCR:ENFR = 1 The DPCR register is set so that the value of the transmitted D-, S- and X-bits originate from the bits of the RDR register. The value is independent of the status ‘on the DCE interface.
4.1.2.2 The receiver will start to search for the frame synchronization pattern in the re-
ceived bit stream. At the same time, a timer T1 shall be started with a time out value of at least 10 seconds. Aiter setting GCR:ENFR to ‘1’ , the receiver will automatically search for the sync pattern. The FSL (frame sync loss) bit in the SYS register will be set to '1' and the programmed value of the NRF register (number of retry frames) will be counted down. If the counter reaches zero, a RSI = 1 status (resynchronization im- possible) is generated. Siemens Aktiengesellschaft 150
If at any time, the receiver recognizes the frame pattern, it will set FSL to ‘0° and generate the SYC status change in the IST register. This can generate an inter- rupt if enabled in the ISEN register. The timer can be realized in two ways. In the first case it is realized with the microprocessor. The software must check the FSL bit, to see if it becomes 0 within the timer period. In the second case, the NRF register is programmed and the RSI status is used to reload the NRF register and to increment the software retry counter. The value for the NRF register and the value for the software counter is determined by the intermediate rate. If the intermediate rate is equal to 8 KHz, a total of 1000 frames (4000 * 80 bits) must be searched before the 10 s time out occurs. To count 1000 frames, the NRF register may be programmed to 250 dec. = 'FA' hex and the soft- ware counter must count four RSI status changes. If the intermediate rate is equal to 16 kbit/s a total of 2000 frames must be searched. Therefore, the NRF register is programmed with 250 dec and the software counter must count eight RSI status changes. For an intermediate rate of 32 kbit/s, the software counter must count sixteen RSI status changes.
4.1.2.3 When the receiver recognizes the frame synchronization pattern, it causes the S-
and X-bits in the transmitted frames to be turned ON. Therefore, the S- and X-bits are set to '0' in the RDR register. RDR ='00010000' b, '10' hex
4.1.2.4 When the receiver recognizes that the status bits S and X are in the ON condi-
tion it will perform the following functions: a) Turn ON circuit 107 (DSR) toward the DTE and stop timer T1 LDR = '1011xx00' b, ‘BO’ hex b) Then, circuit 103 (TxD) may be connected to the data bits in the frame; how- ever the DTE must maintain a binary 1 condition until circuit 106 is turned ON in the next portion of the sequence. DPCR = '00100000' b, '20' hex The transmitted D-bits originate from the DCE interface. Siemens Aktiengesellschaft 151
c) Turn ON circuit 109 (DCD) and connect the data bits to circuit 104 (RxD). LDR = ='0011xx00' b, '30' hex DPCR ='10100000' b, 'AO' hex d) After a N (N = 24) bit interval it will turn ON circuit 106 (CTS). Wait for three status changes of bit STR:RDB (3*8 = 24 = N) and set: LDR = '0001xx00', '10' hex DPCR = '10101100'b, ‘AC’ hex (connect S- and X-bit to DTE) 4.1.3 Data transfer state. DPCR = '10101100' b,'AC’ hex S- and X-bits are connected to DTE. 4.1.4 Disconnect mode.
4.1.4.1 At the completion of the data transfer phase, the local DTE will indicate a discon-
nect request by turning OFF circuit 108 (DTR). This will cause the following to occur: a) The status bit S in the frame toward the ISDN will turn OFF, status bits X are kept ON; RDR_ = '110x0000' b, 'CO' hex DPCR = "10101000" b, 'A8' hex Set the S-bits in the RDR register to one and connect the transmitted S-bits to the register bits. b) Circuit 106 will be turned OFF. LDR = = '0011xx00' b, ‘30’ hex DPCR ='10101000' b, ‘A8' hex Siemens Aktiengeselischaft 152
a c) The data bits in the frame will be set to binary 0. RDR == '11000000' b, 'CO'hex DPCR ='10001000' b, '80' hex Set XD to zero and cannect the transmitted D-bits to the register bit.
4.1.4.2 If circuit 108 (OTR) is still ON at the remote TA, this TA will recognize the transi-
tion of the status bits from ON to OFF and the data bits from data to binary 0 as a disconnected signal and it will turn OFF circuits 107 (DSR) and 109 (DCD). A change in the received S-bits is indicated by the SXC bit in the EXIR register. An interrupt is generated, if the ‘ENABLE EXI' bit is set in the ISEN register. The received D-bits can be monitored by the USART receiver. Therefore the USART receiver is connected to the received D-bits. HMR = '1xxxxxxx' b, '80" hex The USART is set to synchronous operation. UMR_ = '00000000' b, ‘00° hex Look for a change in the received S-bits (IST:EXI!, EXIR:SC). If both SXS:RSA and SXS:RSB are ‘0’, turn on the USART (UMR:UREN = 1), start reception (UCC:TRA = 1) and read the next characters. If they are ‘00' disconnect RxD, set S-bits to OFF and/or disable frame. Wait for IST:EXI Check for EXIR:SC_ If SXS:RSA = 1 and SXS:RSB = 1: HMR = 10000000" b, '80" hex connect USART receiver to frame UMR == '00100000' b, '20' hex USAR sync, ON UCC — ='00000010' b, '02' hex TRA=1 Wait for RFS:URD Read URFIFO If data = '00' then LDR = ='1111xx00" b, "FO" hex set all DCE outputs to OFF DPCR_ ='00000000' b, '00' hex connect DCE interface to register bits GCR:ENFR =0 disable V.110 frame Return to disconnect mode | Siemens Aktiengeselischaft 153
4.1.4.3 The TA at the station that originated the disconnect request will recognize receip-
tion of S = OFF or the joss of framing signals as disconnect acknowledgement and turn OFF circuits 107 (OSR) and 109 (DCD) and transfer to disconnect mode. Wait for IST:EXI, EXIR:SC or IST:SYC If SXS:RSA = 1 and SXS:RSB = 1 then return to disconnect mode if SYS:RSL then return to disconnect mode 415 Loss of frame synchronization.
4.1.5.1 In the event of loss of frame synchronization, the TA should attempt to resyn-
chronize as follows: a) Place circuit 104 (RxD) in binary 1 condition (passes from the data mode). LDR = 'xxx1xx00' b, '10" hex DPCR ='00101100' b, '2C' hex b) Turn OFF status bit X in the transmitted frame ROR = = 'xx1x0000' b, '20 hex c) The remote TA upon recognition of status bit X OFF will turn OFF circuit 106 (CTS) which will cause the remote DTE to place circuit 103 in a binary 1 condi- tion. LDR = 'xx1xxx00' b, '20° hex d) The local TA should attempt to resynchronize on the incomming signal. e) If after an interval of three seconds the local TA cannot attain synchronization, it should send a disconnect request by turning OFF all of the status bits for sev- eral (at least three) frames with data bits set to binary 0 and then disconnect by turning OFF circuit 107 (DSR) and transferring to the disconnect mode. The timer of three seconds can be realized in two ways like timer T1 during ‘switching to data mode (4.1.2.2). A microprocessor timer can be used and the SYS:RSS bit is polled or register NRF is programmed. Siemens Aktiengesellschaft 154
f) If resynchronization is achieved, the TA should turn ON status bit X toward the distant station. RDR = = 'xx0x0000' b, '00' hex g) If resynchronization is achieved, the TA (which has turned OFF circuit 106) should, after a N bit interval, turn ON circuit 106. This will cause circuit 103 to change from binary 1 to the data mode. LDR = ='xx0xxx00' b, '00" hex Siemens Aktiengesellschaft 155
5.3 Autobauding
One of the major areas of application of the ISDN Terminal Adapter Circuit (ITAC PSB 2110) is the connection of terminals and PC's supporting RS232C/V.24 to the Integrated Services Digital Network. This is implemented according to the V.110 specification. If one thinks in terms of today's technologies the ITAC could be compared, in this application, to a highly sophisticated modem since it interfaces a terminal/PC to the telephone network. Of course there is no modulation/demodulation going on and the additional features of- fered by the ITAC constitute a major advance on current equipment. Whereas most mod- ern modem's work at dedicated rates with limited configuration possibilities the ITAC can be programmed to any combination of the following: bit rate 38400 bit/s 19200 bit/s 9600 bit/s 4800 bit/s 2400 bit/s 1200 bit/s 600 bit/s 300 bits parity None, Odd, Even, Space, Mark character bit 8, 7, 6, 5 bits stop bit 1, 2 stop bits What is in itself very flexible is not without some programming overhead under certain cir- cumstances. Consider the case where the ITAC is at the front end of a 'ISDN Modem’ sit- ting in some office somewhere. Now in this office there are several V.24 terminals of various calibres all wanting access to the ISDN on an occasional basis. What may seem like a minor configuration headache can be eased considerably if we consider the possi- bility of Autobauding. By this procedure the "ISDN Modem’ would be able to recognize automatically the configuration settings of the terminal that's plugged into it. Hence any of the terminals lying around the office can be connected into the ISDN with the minimum of fuss. This is just one fanciful example where autobauding may prove indispensable. This chap- ter will propose a possible implementation. The example discussed will limit itself to char- acter lengths of 7 and 8, speeds up to and including 19200 bit/s and all parity types ex- cept Mark. The characters sent will be in ASCII format. This does cover most of the normal applications encountered in the real world. In most cases these limits are self-inflicted and the principles explained below can equally be extended to accommodate a wider range of configurations. Siemens Aktiengesellschatt 156
The Hardware etc. Before considering any code it is appropriate to mention the hardware on which this algo- rithm was realized. Those familiar with the Siemens ISDN PC User Board (SIPB) will know that it is based around an 80188 microprocessor. An ITAC add-on module was plugged into the mainboard. The algorithm was built into the mainboard firmware. It can be initiated by sending a command to the firmware via a command/response mailbox which lies at the core of the software architecture of the system. The code was written in ‘C' and compiled with Microsoft C Compiler version 5.1. The PC was used as a V.24 terminal and con- nected to a V.24 driver which in turn was connected to the ITAC. The Procedure In order for the ISDN Modem’ to automatically recognize the set-up characteristics of the terminal that has been plugged into it, some input from that terminal is required. In other words the terminal has to tell the ‘ISDN Modem’ a little bit about itself! In keeping with the syntax of the ubiquitous Hayes Smartmodem the string; AT is used for this purpose. Also in keeping with Hayes the string at is also supported. Entering either of these character sequences at the terminal is sufficient for the ISDN Modem’ to calculate its characteristics. All the information required is there; it ‘only remains for the code to extract it. First let us see how these characters would look on the TxD line from the terminal. The corresponding character strings are shown below; A (41Hex) s 1000001(8 P)S T (64Hex) s 0010101(8 P)S a (61Hex) s 1000011(8P)S t (74Hex) s 0010111(8 P)S where s - start bit 8 - possible eight character bit P - possible parity bit S - stop bit The first thing to note is that the spaces in the character strings are only there to make it more legible. The leftmost bits are only the first transmitted by the terminal and the first re- ceived by the ITAC. In the middle of the string is the ASCII code of the character. Note that the LSB of the character is transmitted first. The character string begins with a bit of start polarity (0) and ends one of stop polarity (1). An eight character bit (in these cases 0) and a parity bit (could be 0 or 1) may also be present. Siemens Aktiengesellschaft 157
The problem devides naturally in two. Firstly the code has ascertain the terminal's speed. The first two bits of the string are used for this purpose. Having performed this the ITAC is programmed accordingly and as much of the remainder of the string as possible is stored in the USART which ist switched to eavesdrop on the V.24 TxD line. This residual string in the FIFO is used to figure out parity and character bit length settings. The problem is complicated somewhat by asynchronous nature of the system. Any num- ber of stop bits can be sent between characters. These superfluous stop bits can effect what gets stored in the FIFO. In some cases the presence of a third character directly after the v/T can also have some effect. The algorithm attempts to take all these factors into ac- count and to recognize the terminal characteristics despite their confusing effects. Problem 1: Recognizing the Speed This is by far the more demanding of the two problems because it is time critical. In effect we time the length of the start bit. Considering the character strings shown above it should be noted that the first two bits in the aVAT sequence are always 0 followed by 1. This is in- dependent of the number of character bits or the parity settings. It is important to realize that the line contains all stop bits (i.e. ones) when no character is sent. Hence we have a situation as depicted in figure 64. We have a isolated 0 character in the line which we know is only one bit long. If we can measure the length of this bit we can work out the speed at which the character is being sent. In fact we don't even have to be very accur- ate in our measurement since the possible speeds increase in multiples of two. For exampie if a bit at a given speed is x long we know that it would be 2x long for the next lower speed and x/2 for the next higher. Figure 64 ‘Speed Measurement Start Bit First Character Bit New Start Bit RHCR = 1 RHCR = 0 Speed Programmed Start Timer Stop Timer USART Reset Software Timer Runs In the ITAC if the status/interrupt bit RCHR (receive character detected) is set in means that at least one start bit has been detected on the DCE/DTE interface since the last ac- knowledgement of RCHR. In fact it is set as soon as a start polarity is detected on the TxD line and not after the complete start bit has been detected. Hence it can be used to detect the beginning of the start bit and to start a software timer. Furthermore by repeatedly ac- knowledging the bit and testing it again, the continuing presence of the start polarity can be ascertained. As soon as the RCHR ceases to be set we know that the stop polarity is present on the {ine. In this way the end of the start bit can be determined and the timer stopped. Siemens Aktiengesellschaft 158
a This is the relevant section of the code; Start_count = 0; /* wait for character to arrive*/ while (!(*it->pt_r_str & STR_RCHR)) do Start_count++; /* Increment */ *it->pt_r_stra |= STR_RCHR; /* Acknowledge*/ } /* Test RCHR*/ while (*it->pt_r_str & STR_RCHR); ‘As soon as the first 1 is received the do loop is exited. In order to store as much of the re- mainder of the string as possible we must program the ITAC for the detected speed and clear the USART before the current bit (1) is finished (see figure 64). Because we have the shortest time for the fastest bit rate the 19200 bit/s case is tested first. This accounts for the rather cumbersome testing of the value of Start_count. To save time the USART is al- ready connected to the TxD line. It had been programmed to a speed of 38400 bit/s. It only requires that it be reprogrammed and reset. Siemens Aktiengesellschaft 159
If (Start_count < 4) /*19200 */ else if (Start_count < 7) /*9600 */ else if (Start_count < 15) /*4800 */ else if (Start_count < 30) /*2400 */ else if (Start_count < 60) 7*1200 */ else if (Start_count < 120) /*600 */ else /*300 */ /* Reset Rx USART but don’t bother /* waiting for command — ac- cepted +/ The boundaries for Start_count were determined empirically. These will vary for different microprocessors, C compilers etc. The progression of values reflect the fact that lengths increase as a factor of two as speeds decrease. Once the reset has been given the time critical stage is passed. It only remains to ac- knowledge any break signal which may be recognized. Because the original speed had been set to 38400 bit/s it is possible that the start bit was longer than the break signal for this high speed. Siemens Aktiengesellschaft 160
— In the above case the beginning of the start bit is detected in a while loop. Bearing in mind that the ISDN Modem’ to terminal connection is useless before the speed of the terminal has been recognized, it is not so important that the firmware is in a blocked state while waiting for the start bit. Although RCHR is an interrupt it was found that on our system the use of an interrupt service routine took too much time. In the worst cases the start bit was already over by the time the routine was entered. — The software timer is not very accurate. However, as was said above, the length of the start bit for different speeds increases/decreases by a factor of two. The timer doesn't need to be more accurate. Because of these failings the timing method described here is admittedly neither very ele- gant nor very portable. However considering the small amount of time available to the pro- gram it does the job efficiently. It has the advantages that it can be written completely in ‘C’ and requires no special hardware modifications. A more elegant method is outlined in figure 65. In this case the TxD line is input directly into the timer unit of the microprocessor. The timer is set-up and enabled to begin counting clock pulses on the falling edge of the first start bit. The rising edge will inhibit the clocking and signal a timer interrupt. The timer count is an indication of the data speed which is used to program the ITAC during the interrupt service routine. This method is more accur- ate and more efficient and such a method is to recommended when hardware is to be spe- cially developed for an autobauding application. Figure 65 Start Bit Timing in wP SAB 80C188 —[p rue 4 1 —— | o Tac ® T0265 Siemens Aktiengeselischaft 161
Problem 2: Recognizing Bit Length and Parity The Basic Procedure Having recognized the speed, by whatever method, it is now possible to store the remain- ing bits in the character string A/a and all the bits of the T/t character string in the FIFO. From the stored values we can figure out the set-up characteristics of the terminal. The first 3 bits received in all cases are 010. The first zero is the start bit which is used to measure the bit length. The time during the receiption of the first one is used to program the ITAC and reset the USART. If the USART reset is completed before the end of the receip- tion of the 1 then the second zero will be interpreted as a new start bit and the subsequent characters will be stored in the USART. To store the remaining bits of the A character string the USART is set to 7 bits wide, no parity and one stop bit. So, for example, for A with 8 character bits and a parity bit the following would occur; As 1000001 8PS s_ is used to measure the bit length. 1 is lost because the programming of the ITAC takes place at this time. 0. is interpreted as the new start bit. 000018P is stored in the USART. S The ITAC expects that the character stored has no parity bit and so the bit immediately following the character should be of Stop bit polarity. Note: The blank spaces are meant to aid legibility. Look at the value stored in the USART. It includes the parity bit and the eight character bit. In principle, the information we're looking for is in the FIFO. The presence of fhe Stop bit is also important. As will be seen there will cases where a zero will be in the position where a stop polarity is expected. It is important to understand how this is interpreted by the ITAC in order to understand the algorithm itself. Take the example where there are seven bits, no parity, one stop bit and the subsequent T follows the A immediately. Siemens Aktiengeselischaft 162
a s 1000001 $s0010101S SSSSSS s_ is used to measure the bit length 1 is lost because the programming of the ITAC takes place at this time. 0. is interpreted as the new start bit. 00001Ss_is stored in the USART. 0 In this case the expected stop bit is a zero. The ITAC now releases a framing error (FER) interrupt and interprets this 0 as a new start bit. 010101S is stored in the USART FIFO as the second character. S Finally a Stop bit is present at the end of the character as expected. The Framing Error will be used extensively in the algorithm. Its main purpose is to over- come the difficulties caused by the fact that in an asynchronous system it is not known in advance how many stop bits will separate the two characters input. Having dealt with the general principles we move on to the specific. Figure 66 lists the possible sequences which can be received when using the sequence AT as input. In the algorithm used the usual sequence is to use a 7 bit wide USART to store the remaining bits of the A character string and an 8 bit wide USART to store the T character string. The stored character is available in the FIFO. Siemens Aktiengesellschaft 163
First we'll look at the simple case where there are plenty of stop bits between the charac- ters of the character string. Consider the first example in figure 66 illustrating what is re- ceived when AT is input from a terminal configured for 7 character bits, no parity, one stop bit (7,N,1). In this case two extra stop bits were sent between the characters. The signific- ance of this will become apparent later. The first character read out of the FIFO is 70 and no framing error is reported since the bit immediately following is 1. Once again the LSB is received first (leftmost bit) and hence the value stored appears to be the reverse of the value in the bit sequence. The USART is then set to be 8 bits wide, again without parity, and the USART is reset. The next value read is D4. Because it is not know if a subsequent character is going be received immediately after, there could be a framing error reported. In this case however this is unimportant. We have stored all the remaining bits of the char- acter string using this 7 bits wide USART/8 bits wide USART technique and all other infor- mation is superfluous. Note that the 7,N,1 setting can produce a number of special cases which will be dealt with in section The Decision. For the present these special cases will be ignored. Now consider one of the cases marked with a * (e.g. 8,E,1). A framing error occurs at the end of the T character. In this case this information is not unimportant as this point coin- cides with the arrival of the parity bit of the T character. The same situation arises for all cases marked with a *. In these cases this information is vital to decide what type of parity is being used. Therefore the occurrence of the framing error at the end of the T character is always checked. If it occurs it is recorded for further evaluation. It is indicated by the presence of a” character in the tables. So to recap the usual procedure would be; a. determine the speed b. use a 7 bit wide USART to store the remains of the A/a character c. use an 8 bit wide USART to store the /T character d. use the framing error at the end of the second stored character to capture infor- mation which could not be squeezed into the FIFO. There is one case, however, when this algorithm is inadequate. This occurs when a fram- ing error occurs at the end of the first character (a/A). When this happens a slightly differ- ent approach must be used (described in the next section). Unfortunately the liberal wide- spread use of the framing error may prove a little confusing. If so the flow charts in Appen- dix A should help differentiate the different cases. Siemens Aktiengeselischaft 164
The AT Sequence Possibilities Character Strings FIFO Contents s ASCIl 8 P S(S)s_ ASCIL 8 PS 7.N1 0 1000001 11110 0010101 1X 70 D4(~) 7,N,1 0 1000001 11110 = 0010101 1x 70 D4(~) 7.E1 0 1000001 0 11110 0010101 1 1X 50 D4 7,0,1 0 1000001 4111110 0010101 0 1X 70 54 7.M,1 0 1000001 111110 0010101, 1 1X 70 D4 7SA 0 1000001 011110 0010101 0 1X 50 54 8,N,1 0 10000010 411110 00101010 1x 50 54 8.E,1* 0 10000010 0 11110 00101010 1 1X 10 54 8,0,1* 0 10000010 1 11110 00101010 0 1X 50 547 8,M,1* 0 10000010 1 11110 00101010 1 1X 50 54 8,S,1* 0 10000010 0 11110 00101010 0 1X 10 547 without sufficient stop bits s ASCI 8 P S(S)s ASC 8 PS ! > 54 -> D4 7,N,1 0 1000001 1.410 0010101 1X 707 54 ->D4 7E1 0 1000001 o4 0 0010101 1 1X 507 54 ->D4 7,01 0 1000001 14 QO 0010101 O 1X 707 547 -> 54 7.M,1 0 1000001 11 QO 0010101 1 1X 707 54 ->D4 781 0 1000001 O14 0010101 0 1X 507 547 -> 54 8.N,1 © 10000010 1 00101010 1X 507 547 ->54 where 0/1 bits stored in the FIFO. ! framing error in first character. “framing error detected in second character. (S) denotes superfluous stop bits which may or may not be present. : Siemens Aktiengeselischaft 165
Parity 7 Bits 8 Bits ; E 5 2) 1 5 ee sis [sft is Framing Errors after a/A and How to Deal With Them A framing error can occur for certain character settings when there aren't sufficient stop bits between the characters. The procedure outlined above must be slightly modified when this occurs. Consider the case 7,E,1 when there are no superfluous stop bits be- tween the characters of the sequence (figure 66; without sufficient stop bits section). A framing error is generated since a 0 follows the value stored in the FIFO and the ITAC was expecting a 1 in this position. Furthermore the FIFO will interpret this zero as a start bit and begin storing what comes afterwards as the second charater. This presents us with a prob- lem. If, after storing the first 7 bit wide character in the FIFO, we proceed to change the FIFO width to 8 we will loose this character. The FIFO will discard the start bit already rec- ognized and go looking for the next falling edge. This would mess up the second value stored in the FIFO. So in this case the FIFO is not switched to 8 bits wide but left at 7 bits wide. But as we have already seen we need to store 8 bits in the second character. When we look at what's stored in the FIFO in the 7,E,1 case we find 54. More importantly we see that the parity bit isn’t stored in the FIFO . So we appear to have lost an important bit of in- formation. In order to retrieve it we use the framing error again. If this bit is zero a framing error occurs and we can put a zero in the MSB position of the value read from the FIFO. Otherwise we put a 1 in this position. In this way we have patched together the value which would have been stored had we been able to use an eight bit wide USART in the first place. This correction is indicated in figure 66 by the '-" transitions. So in this case the framing error is used to identify the problem (when it occurs after a/A) and to correct for the shortfall in the FIFO data contents. In section Basic Procedure we saw the framing error being used for different settings and to a different end. Therefore there is no conflict in the use of this status bit. It is important to realize that although in both cases the parity bit is recognized using the framing error the subsequent procedures are completely different. In this case the framing error is used to recognize bits which would, under normal circumstances, be stored in the FIFO. In section Basic Procedure the fram- ing error records the polarity of bits which would never under any circumstances be stored in the FIFO. Siemens Aktiengesellschaft 166
a Note also that the case 7,N,1 with no extra stop bits between the characters is a special case which be handled in a special way. No doubt the above appears quite complicated. Studying figure 66 in detail is highly rec- ommended to understand the cases and the flow chart diagrams to understand how to deal with them. Evaluating What We Get Once we have stored two characters in the FIFO we are in a position to figure out the ter- minal characteristics. It is important to note that the lower byte is the same in all cases (either 0 or 4 in the AT case). These bits are only used to double check that the expected characters were typed at the terminal. This prevents the algorithm from jumping to the false conclusions if 'Wq' were to be typed at the terminal. The information pertaining to the parity and character length is in the upper byte. Table 49 shows how these are evaluated. For example if the upper byte of the first FIFO character is 7 and of the second is D then the terminal must be set at 7 bits, no parity. With one ex- ception each of the characteristic combinations produce a unique combination making it easy to identify the characteristics. The exception is not such a great problem. In table 49 we see that the cases 8,N,1 and 7,S,1 are indistinguishable. Compare the character A using these settings; 8,N,1 s 1000001 8S 7,81 ss 1000001 PS The character strings are exactly identical excepting the bits 8 and P. But, because of Space Parity, bit P is always zero. Furthermore for the seven bit character set bit 8 is al- ways zero. The 7,S,1 case is really a subset of the 8,N,1 case. Hence the case 7,S,1 can be programmed as 8,N,1 without causing any errors. In one case however the procedure fails to identify the settings. The mark parity bit looks the same as a superfluous stop bit. Both arrive after the ASCII character and both are 1. Since this is an asynchronous system any number of stop bits are allowed between char- acters. Hence it is impossible to tell the mark parity bit from the stop bits using this method. Similarly stop bits can be sent as part of the character string or as inter-character time fills. It is therefore also impossible to identify the number of stop bits which are programmed at the terminal. To overcome this limitation it would be necessary to ensure that the AT/at se- quence is sent without any superfluous stop bits in between. This makes life more difficult at the terminal. Besides these settings do not occur ail that frequently. Therefore this program ignores this difficulty and interprets all these cases as No parity, One stop bit. This doesn’t cause problems with the receiption of the characters. it simply looks as though there are always plenty of stop bits between characters. If a V.110 link is made no problems will be encountered as the link will be transparent and the extra ‘stop bits’ will be forwarded on to the remote. What will be problematical, however, will be those cases when the local FIFO is used to write to the local DTE. In this case the FIFO oper- Siemens Aktiengeselischaft 167
ation will not append the required number of ones at the end of the character in the FIFO. The terminal will see errors in the data stream. For example if it is expecting two stop bits per character it may only receive one. How it reacts to these errors is terminal dependant. The AT String and What to do with it The final case to be considered is the string at. Figure 67 and table 50 detail this case. The principles are the same. The ASCII character itself is different since it has a extra 1" bit in the lower case characters (see section above). This bit is referred to as the lower case bit. This bit effects the contents of the FIFO not only by simply being there but also because the even and odd parity values are affected. Table 50 details the results re- ceived for the at case. Siemens Aktiengeselischaft 168
a Figure 67 The AT Sequence Possibilities Character Strings FIFO Contents s ASCIL 8 P S(S)s | ASC 8 PS 7,.N,1 0 1000011 11110 = 0010111 1x 78 Fa(7) 7,N1 0 1000011 411110 = 00101114 1x 78 F4a(~) 7,E,1 * 0 1000011 111110 0010111 O 1X 78 74 7,0,1* 0 1000011 O 11110 0010111 1 1X 58 Fa 7.M1* 0 1000011 1 11110 0010111 1 «+1X 78 F4 7,8,1* 0 1000011 0 11110 0010111 QO 1X 58 74 8.N.1* 0 10000110 11110 = 00101110 1x 58 74 8,E,1* 0 10000110 1 11110 00101110 0 1X 58 74a 8,0,1* 0 10000110 0 11110 00101110 1 1X 18 74 8.M1" 0 10000110 1 11110 00101110 1 1X 58 74 8S,1* 0 10000110 0 11110 00101110 0 1X 18 14 without sufficient stop bits s ASCII 8 P S(S)s ASCII 8PS 7,N,1* © 1000011 1 0 0010111 1x 3a" 7A(~) ! >74 > F4 7,N,1 * 0 1000011 140 0010111 1X 7s 74 > F4 7,6,1* © 1000011 1.1170 0010111 0 1X 78 14 ->74 7,01* 0 1000011 O41. 0 0010111 1 1X 58” 74 ->F4 7,.M.1* 0 1000011 1.41. 0 0010111 1 1X 78 74 ->F4 7,S,1* 0 1000011 o4 00101114 0 1X 58" 74 ->74 . 8,N,1* © 10000110 1 00101110 1X 50" 54 +> 54 where 0/1 bits stored in the FIFO. | ! framing error in first character. ) “framing error detected in second character. | (S) denotes superfluous stop bits which may or may not be present. Siemens Aktiengeselischaft 169
The AT Decode Table _ Parity 7 Bits 8 Bits Nz dec) fs? e 7 7s ea s|s [7 |e i The Decision We now have all the information we can possibly get and its about time that we make a de- cision. However the information is bit scattered. We have two tables for each of the two character strings and we also have some additional information which is not contained in the upper bytes we have extracted from the FIFO characters. First of all the lower case bit of the A/a character appears in the lower byte of the first FIFO word. Secondly there is still some framing error information in the tables (described using the symbol (~) which isn't included in the decision word. We want to incorporate this information into the decision word to simplify the decision making process (simple switch’ case decision). Now if we consider the words at present in tables below we find the following bits are al- ways constant. 7 t) 0 1 | 1 1 | used two of these erstwhile un-used bits to store the ‘missing’ information. The MSB was used the store the lower case bit of the A/a character. The LSB was reset when a framing error occurs (e.g the value 57 becomes 56). The two tables were combined into one and the corresponding modifications have been made. The result is the decision table in table 51. ‘Siemens Aktiengeselischaft 170
E 5 D 1 {5 E F 7 D 6 fe} 7 5 4 O° D F 7 Ss 5 1 4 Ss 7 9 6 The Special Cases of 7,N,1 Finally there are special cases which can occur for the 7,N,1 setting. These have been ignored up to now to avoid unnecessary complication, although they were detailed in figures 66 and 67. Table 51 states that upper bit combinations which can be obtained with 7,N,1 are 7D and FF. However we saw in figures 66 and 67 that a framing error can ‘occur randomly at the end of the second FIFO character depending on whether another character follows the avVAT sequence or not. Because of the way the algorithm treats a framing error the cases 7C and FE are also valid when the setting is 7,N,1. Another special case occurs when there are no superfluous stop bits between the charac- ters. Here are the relevant lines from figures 66 and 67. s ASCE 8 P S(S)s ASCIl 8 PS 7,N,1 0 1000001 1 O 0010101 1X 30" 6A(~) ! > 54 -> D4 7,.NA 0 1000011 4 001011 IX 7A(~) 1 >74 > F4 Siemens Aktiengeselischatt 171
To simplify matters a bit in the second byte is changed into 54 or 74 (the equivalent /T character) in the code; if (icht == Ox6A) ichr = 0x54; if (ichr == 0x7A) ichr = 0x74; This allows us to continue dealing with this case without having to change any of the procedures used for the non-special cases. It is now only a question of working out all the possible result combinations which could occur. Once again a framing error can occur randomly since the bit following what is stored in the FIFO is unknown (X). In this case, however, this causes the MSB of the upper byte to be set or reset randomly (see section Framing Errors). Hence the cases which can occur are; 35, B7, 3D, BF; When dealing with these special cases | have simply let them filter through the algorithm, making as little modifications as possible to the FIFO data and simply reacting to every Possible result combination which could occur. Although this is a bit complicated to fol- low, it generated as little extra code as possible. The switch case statement ended up with a few extra cases, but the basic handling of the received characters remained the same. A easier to follow (but less economical) way of dealing with these special cases would be to treat them separately. For example as soon 30/38 is read from the FIFO the program would jump to a separate part of the code which waited for 6A/7A. If some other value was found we would simply start again normally, looking for A/a. Framing errors etc. would be ignored. This is easier to visualise but more difficult to realize. Siemens Aktiengesellschaft 172
Appendix A contains a flow chart description of the procedure described above. Appendix B contains the corresponding code. For the most part the code should be self- explanatory. However a little overview wouldn't go amiss. The structure table register ITACTAB “it = itac; contains all the pointer to the registers of ITAC. For example to reset the USART the code lines reads; *it->pt_r_uce points to the ucc register of the ITAC UCC_URR refers to the URR bit of the UCC register Other important definitions include; BRS_U_9K6 The byte necessary to program the brs register to yield a User rate of 9600 bit/s BRS_N_600 The byte necessary to program the brs register to yield a User rate of 600 bit/s UMR_P_ODD The byte necessary to program odd parity Armed with this knowledge the code itself should be easy to follow. For the sake of clarity the program is implemented in a continuous routine. In a many apli- cations it will prove more sensible to use interrupt routines to detect the presence of the characters in the FIFO rather than waiting for URD in a while routine as is the case in the code presented here. ‘Siemens Aktiengeselischaft 173
Speed Recognition Flow Diagram ——< from other Flow Diagrams SS Ves YNo Reset USART 002646 Siemens Aktiengesellschaft 174
Reception of Remaining Bits of A/a (C1) Vyes Ke YNo USART -> 8,N1 I INITIALIZATION Fig.68 Yes Shift Lower Case Bit to MSB of Ct rane? Siemens Aktiengeselischaft 175
Reception of Character of T/t (C2) > . Yes No No Yes + > Bit of C2 <maee> No, INITIALIZATION Fig.68 Yes Set Pority and Bit Length wooze4s Siemens Aktiengesellschaft 176
a Appendix B C Code SESE GSE E SSIES OSIEUG EI EESON SSSI ISIG I ISIG AISI IT * Function: Auto_speed_ITAC () * * Parms: * * purpose: * LEHI IESE SSUES ISIS II IOSSOSSHOS GEST I EGO IOC IIR / EXPORT int Auto_speed ITAC () unsigned int Start_count, T_length, i; unsigned char ichr, Test_Byte; register ITACTAB *it = itac; /* USART connected to the TxD line = */ /* of the V.24 */ /* USART is set to async and enabled */ *it->pt_r_umr = UMR_ASYC | UMR_UXEN | UMR_UREN; 7* Don’t want anything interrupting */ /* our time-critical routines */ *it->pt_r_mask = MASK ALL; TEST: /* Program USART to be 7,N,1 at */ /* 38400 bps */ it->pt_r_aicr = AICR_B7 | AICR_SP_1l; /* Reset USART */ 7* acknowledge everything used to */ /* prevent residual effects */ A_found = 0x00; T_found = 0x00; Start_count = 0; /* wait for character to arrive */ while (!(*it->pt_r_str & STR_RCHR)) do Start_count++; . | Siemens Aktiengesellschatt 177
while (*it->pt_r_str & STR_RCHR); /* Work out the speed and program */ /* BRS accordingly */ /* NOTE the boundaries have been */ i chosen from empirical */ i measurements */ /* NOTE the most time critical */ /* speeds must be programmed */ /* first */ if (Start_count < 4)/* 19200 */ else if (Start_count < 7)/* 9600 */ else if (Start_count < 15)/* 4800 / else if (Start_count < 30)/* 2400 */ *it->pt_r brs = BRS_U_2K4 | BRS _N 2K4; else if (Start_count < 60)/* 1200 / else if (Start_count < 120)/* 600 ” else /* 300 */ /* Reset Rx USART but dont bother */ /* waiting for command accepted */ 7* Clear any erroneous break */ /* detection ”/ if (*it->pt_r_scs & (SCS_BRB | SCS_BRE)) *it->pt_r_scsa = SCS_BRB | SCS_BRE; Start_count = 0; /* wait till all a/A character is */ /* there */ /* NOTE; the timeout prevents the */ /* program hanging because of */ /* incorrect speed conclusions due */ /* to erroneous characters being */ i= 0; /* input from the terminal ” if (it+ > 2000) goto TEST; /* Read in the byte from FIFO */ Siemens Aktiengeselischaft 178
a ichr = *it->pt_r_ufifo; if (1(*it->pt_r_rfs & RFS_FER)) { 7* Reset width of FIFO only if no */ /* other byte is in FIFO */ *it->pt_r_aicr = AICR_B8; wit->pt_r_uce = UCC_URR; /* Yo differentiate FIFO length “/ T_length = 8; else Tlength = 75 /* if the character is wrong start = */ /* autobauding speed process again */ if ((ichr & 0x17) != 0x10). goto TEST; A found = (ichr & 0x70); /* small letters being used */ if (ichr & 0x08) A_found |= 0x80; /* wait for next character 't/T’ */ /* read in the byte from FIFO */ ichr = *it->pt_r_ufifo; /* if the FIFO was not changed */ /* to eight bits wide this section */ /* manipulates the T_found */ /* character to be the same as it */ /* would have been had the FIFO */ /* been set to 8 bits wide */ if (T_length == 7) /* treat special rare cases */ if (ichr == 0x6A) ichr = 0x54; if. (ichr == 0x7A) ichr = 0x74; T_found = ichr; 7* put one in upper bit «f/f Siemens Aktiengesellschaft 179
T_found |= 0x80; else /* acknowledge it */ t else T_found = ichr; . { /* reset bit in value to indicate */ /* FER has occurred */ T_found s=~0x10; /* Note that the FER interrupt has */ /* a different meaning for the */ 7* T length = 8 case */ if ((T_found & 0x4F) != 0x44) /* if the character is wrong start a/ /* autobauding process again */ goto TEST; /* prepare registers for changes */ *it->pt_r_umr &= ~(UMR PTY | UMR_P EVEN); /* Strip off the all- importanttart */ /* upper bytes */ TEST_Byte = (A found | (T_found >> 4)); switch (Test_Byte) /* DECISION TABLE */ { /* 7 bits Even Parity One stop bit */ case 0xSD: case OxF7: break; case 0x75: /* 7 bits Odd Parity */ case OxDF: break; /* 7 bits No Parity One stop bit */ case 0x7D: case OxFF: case Ox7C: case OxFE: case 0x35: /* These cases arises rarely; */ case 0xB7: /* if 't! follows 'a' directly; “/ case 0x3D: /* without sufficient stop bits */ case OxBF: Siemens Aktiengesellschaft 180
a break; /* 8 bits No Parity One stop bit a/ case 0x55: case OxD7: break; /* 8 bits Even Parity One stop bit = */ case 0x15: case OxD6: break; /* 8 bits Odd Parity One stop bit */ case 0x54: case 0x97: +it->pt_r umr |= (UMR_PTY | UMR_P_ODD); break; /* 8 bits Set Parity One stop bit */ case 0x14: case 0x96: break; /* get any other possibilities: */ /* start again “/ default: goto TEST; break; return (ACK_DONE) ; Siemens Aktiengesellschaft 181
5.4 Alternative Solution for Autobauding
Autobauding is used in terminal adapters to detect the data rate at which the terminal transfers its data. Two characters at the begin. of each command string are evaluated and indicate the data rate and the character format. Problems with the Current Implementation of an Autobauding Procedure A solution for implementing autobauding with the ITAC has been issued in several im- plementations from various customers showed two weaknesses. First it is not possible to detect a character format of 8 bit plus parity bit in the case where the 'A' and 'T character follow with only one stop bit. Second, the period to reset the USART receiver after repro- gramming its character format is less than half a bit period. For high data rates, the inter- tupt handling takes longer and thus the character immediately following the ‘T' got lost. These problems can be solved in two ways. One way is to specify a minimum number of two stop bits between the ‘A’, the 'T' and the next character. The second way is by using an alternative autobauding solution which is limitied to data formats of 7 bit plus parity or 8 bit without parity. Alternative Solution to Detect the Character Format In most cases, the terminal adapter needs to detect only five character formats. These are 7 data bit plus one parity bit or 8 bit without parity bit. They have in common a total charac- ter length of 8 bit plus start bit and stop bit. In the chapter 5.3 it is described that the USART has to be reset if the character format changes. This is only true if the total number of bits change, e.g. from 7 bit no parity to 8 bit with parity. If the overall character length is kept the same, the character format need to be changed before the parity bit is received. This gives at least 7 bit periods time to repro- gram the USART. In contrary to the chapter 5.3, the character format of the USART is now set to 8 bit no parity (8N1) before the speed is detected. Once the speed is detected, the USART re- ceiver is enabled and receives both characters. The software will evaluate the pattern of the ‘A’ and the 'T’ character. The first byte from the USART represents the ‘A’ character and it is compared against the following pattern: MSB LSB x1ix1xoa00 Siemens Aktiengesellschaft 182
A framing error on the first character indicates that the 'T- character follows immediately ‘or with one stop bit. The MSB of the first character is tested to distinguish between two cases of handling the second character. If the MSB is zero than the second USART-FIFO character is compared against: MSB LSB 1x1x1010 A framing error on the second character indicates again that another character is follow- ing immediately. The software has to reprogram the USART format within the next 7 charac- ter bits. The character following the 'T' will be received correctly. If no framing error is indicated or the MSB of the first character is one, the gap between the first and the second character is at least one additional stop bit. In this case, the second USART-FIFO byte is compared against: MSB LSB x1x10100 The software has more than 7 character bits time to reprogram the USART character format. Siemens Aktiengeselischaft 183
Evaluation of the Character Format The character format is determined by testing three bits from both FIFO-values. The signifi- cant bits of the first FIFO character are bit 3 to 5. Bit 5 to 7 from the second FIFO character are the significant bits if no framing error has been detected. If a framing error has been de- tected, the significant bits are bit 4 to 6. The bit values and the corresponding character format are shown in the following table. Table 52 First Char Second Char Char Format 543 765 if no framing error on first char. 543 654 if framing error on first char. 010 010 8N1 or 701 on 011 8N1 or 701 110 010 701 on 110 701 010 110 7E1 Wt 011 7E1 110 110 711 14 qt 711 8N1 8 bit, no parity, 1 stop bit AICR=00H, UMR=B0H 7 701 7 bit. 0 parity, 1 stop bit AICR=40H, UMR=FOH 701 7 bit, odd parity, 1 stop bit AICR=40uH, UMR=F2H 7E1 7 bit, even parity, 1 stop bit = AICR=40H, UMR=F4H 711 7 bit, 1 parity, 1 stop bit AICR=40H, UMR=F6H Figure 71 shows the timing diagram for receiving the AT-characters with a different num- ber of stop bits. Figure 72 shows the flow diagram for the character evaluation. Siemens Aktiengeselischaft 184
ee 1. chor "A or ‘ot —efe— 2 Chor Tor th —efe— 5. Char (CR) ed Tot _ oo eo No Adsiione! D1 OOO OHIM1FOO1O1Hi10101 01100 00/11 Stop Bit s PSs PSs Ps a = URsIFO or FO al yy oo H wo vio we SR ACR ice [== 1. Chor 'A or ta! ef f= 2. Chor ‘Tt or tH ef = 3. Char (CR) —e} Toto One Additonal D1OOOOHI/I1 10001 O1/i1Hit TOTO V1 O00%U1N1 Stop Bit s PSSs PSSs pss HR tH vriro ra vnifo it vo ' vo uo eM nice nce Fee 1. char “A or tote] R= 2. Chor Tor th ef 3. Chor (CR) ey Foo or re 01000 001111110001 01/10/11 110101100 00/111 Rathore : PSSSs PSSss pss Spun Pe oH UFO j ‘iro j Umno ) uo UMR uk cee Nc Nice Siemens Aktiengesellschatt 185
ne <> Yes Read 1.Char No Yes; 1.Char & 80 —t =00? No No | Yes Yes Read 2.Cnar " <> ExIT.error Yes} No Yes No No Lyes Yes fick FER 2 ExiTerror Use 1.Char + 2.Char to Use 1.Chor + 2.Char to tenn vmat reprogram USART format ‘program USART formal vroozes9 EXIT.ok EXIT,ok Siemens Aktiengesellschaft 186
5.5 Octet Alignment for Data Transfer at 64 kbit/s by the ITAC®
In many applications which transfer data at 64 kbit/s the octet alignment provided by the B- channel is used for synchronization. Examples for these applications are in-band Par- ameter Exchange (IPE), voice processing or handling of proprietary protocols. One may have assumed that aligned octet data transfer would occur by programming the ITAC into a data rate of 64 kbit/s and the USART to transparent mode. However the USART does not just transfer the data with the octet alignment provided by the time-slot. How the SNI and USART Operate In the receive direction, the synchronous network interface receives the time-slot informa- tion and forwards it to the USART as a continuous data stream at 64 kbit/s. The USART will start to receive octets after the TRA command has been entered or the USART receiver has been enabled. The relation between the time-slot information and the USART FIFO data depends on the timing when the command is executed. In the transmit direction, the USART sends a continuous data stream at 64 kbits/s to the SNI. The SNI cuts the continuous data stream into octets and transmits them in the se- lected time-slot. The relation between the USART FIFO data and the data on the time-slot depends on when the USART transmitter is enabled. How to Achieve the Octet Alignment With the following procedure it is possible to transfer data octets aligned to the time-slot. The procedure is time critical and therefore it is recommended to turn off all interrupts. The synchronization procedure roughly needs 500 microseconds. The IRC transmitter generates an XDB interrupt after eight data bits have been sent. Since the network rate is set to 64 kbit/s, the XDB interrupt is generated at the end of a time-slot. For the transmitter the alignment is achieved by enabling it after a delay of between 83 and 97 microseconds from the XDB interrupt. In the receive direction the principle is for the receiver to synchronize on a known charac- ter being sent from the transmitter and looped round to the receiver by ‘test loop 3'. There- fore a known character is written into the UXFIFO and into the SYNC register. Since the transmitter continues to repeat the last character entered in the UXFIFO, only one value must be entered. The receiver is set to mono-sync which will generate an URD interrupt after two know characters have been received. Once the correct value is received, ‘FF’ is written to the UXFIFO to transmit idle bits and the test loop 3 is deactivated. The USART transfers now all data aligned to the time-slot. IT SHOULD BE NOTED THAT A USART TRANSMITTER OR RECEIVER RESET COM- MAND WILL DESTROY THE ALIGNMENT. Also note that there will be another one or two synchronization characters sent over the SNI before the ‘FF’ value is sent. If this causes problems in the application, the deactiva- tion of test loop 3 may be delayed until the 'FF' character is read from the URFIFO. Siemens Aktiengesellschaft 187
This listing shows the necessary register setting of the ITAC. It has been tested on a sys- tem using a 80C31 CPU, an ITAC and a HSCX to varify the alignment. write to TAC_GCR reg COH ; this powers up the chip, enables DCE as sync DCE wait 100ms ; waiting to ensure that the DPLL is locked before the ; IRC is enabled write to ITAC_BRS reg AAH pur =nr = 64000 write to ITAC_DPCR reg 51H ; connect SCL to D bits, activate test loop 3 write to ITAC_GCR reg C4H ; Enable IRC by setting ENFR = 1 write to ITAC_IST reg FFH ; acknowledge all interrupts outstanding write to ITAC_HMR reg COH ; connect usart to IRC write to ITAC_UMR reg 00H ; disable usart write to ITAC_UCC reg COH ; reset usart transmitter and receiver write to ITAC_ISEN reg 00H ; disable all interrupts disable all system interrupts write to ITAC_SYN reg 41H ; prepare sync. character write to ITAC_UFIFO reg 41H } prepare usart fifo with character write to ITAC_STR reg 024 ; acknowledge XBD wait till ITAC_STR bit XDB = 1 wait 83 microseconds ; Delay of 83 to 97 us before enable TX write to ITAC_UMR reg 38H ; enable TX. and RX. TX is now octet aligned. RX is ;mono-sync wait till ITAC_RFS bit URD =1 i the receiver is than sync read ITAC_UFIFO ; should be 41H (syne character) write to ITAC_UFIFO reg FFH 3 Set USART to idle (transmit '1') write to ITAC_DPTR reg 50H ; turn off test loop as we are now synchronized activate all system interrupts Siemens Aktiengesellschaft 188
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6 Package Outlines
Plastic Dual-in-Line Package, P-DIP-40 Fe i [2 15.2440.2 ) tL } | wet | 3 ales" 2.54 1.5mox 0.45*o m3 4) thos 15.24412 40 21 rT +| ‘GPD05055 | { 1 20 Piastic-Leaded Chip Carrier, P-LCC-44 (SMD) 17.7 -03— I 16.7 -02—-} Index wag 14s dq ° B a4 Be du eq b> 2S q f S SSF Fat03 artosio2 ‘SMD = Surface Mounted Device Siemens Aktiengeselischaft 189