PS51259-A MITSUBISHI | Alldatasheet

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MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS51259-A TRANSFER-MOLD TYPE INSULATED TYPE Mar. 2003 PS51259-A INTEGRATED POWER FUNCTIONS

  • Single phase AC input, DC output IGBT/FWD con- verter bridge
  • 600V, 20Arms (Input current) APPLICATION AC100~200V Active-Converter for PFC (Power Factor Correction), of Air-conditioner and so on. Fig. 1 PACKAGE OUTLINES MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS51259-A TRANSFER-MOLD TYPE INSULATED TYPE INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
  • IGBTS driver circuit
  • Control supply under-voltage (UV) protection
  • Input interface : 5~15V line CMOS/TTL compatible, Schmitt Trigger receiver circuit (Active high) Dimensions in mm Detail A Detail B Type name , Lot No. A B

21 TERMINAL

  1. 10. 11 TERMINAL 2-φ4.5 ±0.2 Heat sink (71) 16±1 8±0.5 31±0.5 28±0.5 0.8 0.6 1.8 1.4 13.4±0.5 21.4±0.5 11.5±0.5 79±0.5 27×2.8(=75.6) 2.8±0.3 67±0.3 12 34 56 78 9 1 0 1 1 1 2 1 3 14 15 16 17 18 19 20 21 22 23 24 25 26 1N 2 2N 2 3N C 4N C 5N C 6N C 7N C 8N C 9N C 10 NC 11 NC 12 NC 13 NC

14 GND

D

16 V IN

17 GND

MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS51259-A TRANSFER-MOLD TYPE INSULATED TYPE Mar. 2003 –20~+100 –40~+125 1500 (Note 2) 60Hz, Sinusoidal, AC 1 minute, connection pins to heat-sink plate TC Tstg Viso V V 0~VD +0.5 Applied between : VD -GND Applied between : VIN-GND Control supply voltage Control input voltage VD VIN ConditionSymbol Parameter Ratings Unit CONTROL (PROTECTION) PART Symbol Ratings Unit Module case operation temperature Storage temperature Isolation voltage Vrms TOTAL SYSTEM Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-PFC is 150°C (@ TC ≤ 100°C) however, to en- sure safe operation of the DIP-PFC, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ TC ≤ 100°C). Parameter Condition Note 2 : TC MEASUREMENT POINT Vi Vi(surge) VO VO(surge) VCES VRRM Ii Ii(125%) I2t Tj MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted) MAIN CIRCUIT PART Vrms V V V V V Arms Arms A2s 264 500 450 500 600 600 120 –20~+125 Applied between : S-R Applied between : S-R, Surge value, Non-operating Applied between : P-N Applied between : P-N, Surge value, Non-operating T C ≤ +90°C, Vi = 200V, VO = 300V, fPWM = 20kHz TC ≤ +90°C, Vi = 200V, VO = 300V, fPWM = 20kHz, 1 min Non-repetitive Value for 1msec of Surge Current (Note 1) Supply Voltage Supply Voltage (surge) Output Voltage Output Voltage (surge) Collector-Emitter Voltage Repetitive Peak Reverse Voltage Input Current (100% Load) Input Current (125% Load) I 2t for Fu sing Junction Temperature ConditionsSymbol Parameter Ratings Unit Control Terminals Power Terminals Tc Heat sink boundary Heat sink Tc

MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS51259-A TRANSFER-MOLD TYPE INSULATED TYPE Mar. 2003 2.4 2.6 1.55 1.90 0.067 mA mA A V T j = 25°C Tj = 125°C VCE(sat) VF ton trr tc(on) toff tc(off) ICES IR ConditionSymbol Parameter Limits Inverter IGBT part Inverter FWDi part Case to fin, (per 1 module) thermal grease applied R th(j-c)Q R th(j-c)F R th(c-f) Min. °C/W THERMAL RESISTANCE Typ. Max. Unit IF = 50A ConditionSymbol Parameter Limits Min. Typ. Max. Unit ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted) INVERTER PART Collector-emitter saturation voltage Forward voltage Junction to case thermal resistance Contact thermal resistance VD = 15V, VIN = 5V, IC = 50A Switching times VCC = 300V, VD = 15V IC = 30A, Tj = 125°C, VIN = 5V ↔ 0V Inductive load Collector-emitter cut-off current Reverse current FWDi reverse recovery current VCE = 600V 1.8 2.1 0.29 0.13 0.15 0.46 0.17 V µs µs µs µs µs °C/W °C/W Control input current ON threshold voltage OFF threshold voltage 16.5 3.0 3.0 0.45 3.7 12.5 13.0 15.0 0.8 0.7 0.3 3.0 2.0 Trip level Reset level V D IIN Vth(on) Vth(off) UV Dt UV Dr V mA V V V V Limits CONTROL (PROTECTION) PART 13.5 1.3 10.3 10.8 V D = 15V, VIN = 5V VD = 15V, VIN = 0V Applied between : VD -GNDControl supply voltage ConditionSymbol Parameter Min. Typ. Max. Unit Applied between : VD -GNDCircuit currentID Supply circuit under-voltage protection Tj ≤ 125°C Applied between : VIN-GND mA VR = 600V Tj = 25°C Tj = 125°C VD = 15V, VIN = 5V Irr VCC = 300V, VD = 15V, IC = 30A, Tj = 25°C

MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS51259-A TRANSFER-MOLD TYPE INSULATED TYPE Mar. 2003 Vrms V V/µs kHz V V Supply voltage Control supply voltage Control supply variation PWM input frequency Input ON threshold voltage Input OFF threshold voltage Applied between : S-R Applied between : V D -GND TC ≤ 100°C, Tj ≤ 125°C Applied between : VIN-GND 264 16.5 Vi VD ∆VD fPWM VIN(on) VIN(off) ConditionSymbol Parameter Limits Min. Typ. Max. 13.5 Unit RECOMMENDED OPERATION CONDITIONS 15.0 4.0~VD 0~1.0 Note 3: Measurement point of heat-sink flatness Mounting screw : M4 (Note 3) ConditionParameter Limits Mounting torque Weight Heat-sink flatness Min. MECHANICAL CHARACTERISTICS AND RATINGS Typ. Max. 0.98 –50 Unit 1.18 1.47 100 N ·m g µm Symbol Measurement point Heat sink Place to contact a heat sinkHeat sink 3mm

MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS51259-A TRANSFER-MOLD TYPE INSULATED TYPE Mar. 2003 Fig. 2 THE DIP-PFC INTERNAL CIRCUIT DIP-PFC VD VIN GND R OUT SOUT VNO VCC LVIC P R S N VIN GND

MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS51259-A TRANSFER-MOLD TYPE INSULATED TYPE Mar. 2003 DIP-PFC Wiring Guidelines Because DIP-PFC switches large current at a very high speed, considerable large surge voltage is generated easily between P and N termi- nals. Please pay attention to the following items:

  • The area of P-Co-N shown in Fig. 3 should be as small as possible because the rectangle shaped switching current flows on this route. In addition, please add a bypass condenser Co’ with good frequency response such as a polypropylene film condenser closely to the P and N terminals.
  • The two IGBT emitters are connected to the VNO terminal of LVIC inside the DIP-PFC. If the internal wiring inductance shown as L1 and L2 in Fig. 4 is too large, large surge voltage will be generated by di/dt. Especially, the lower the temperature, the faster the switching speed, therefore the larger the di/dt. This surge voltage applies to the VNO and N terminals, which is possible to destruct LVIC.
  • In order to suppress the surge voltage, the external wiring method shown in Fig. 4 is recommended. To reduce the parasitic wiring induc- tance, the wiring of the external terminals of N(N-1) and N(N-2) should be made as short as possible.
  • Please mount a fast clamp diode (EG01Y@Sanken) between N and control GND terminals to prevent control GND potential variation from the minus voltage of N terminal. R N / F LVIC VNO P DIP • PFC S VIN N (N-1, N-2) Control ICMCU VD GND Co' Co P R N-1 GND VD Control input GND VD VIN N-2 Insert a diode here To restrain the IPM surge voltage, mount the condenser closely to the terminals To reduce the parasitic inductance, this wire should close to N terminal Fig. 3 DIP-PFC INTERFACE Fig. 4 RECOMMENDED WIRING METHOD