M74LS76AP MITSUBISHI | Alldatasheet
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DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET DESCRIPTION ; ; PIN CONFIGURATION (TOP VIEW) The M74LS76AP is a semiconductor integrated | circuit containing 2 J-K negative edge-triggered flip-flop circuits with discrete terminals for clock input T, inputs J and K and direct set and reset inputs Sp and Rp. Clock inpuT IT + [7] 1K INPUT DIRECT SET ye _, ik Fo o| +19} FEATURES wneut | dy he = pours ‘ owmect peser was. rT) gab Ab + 10 © Negative edge-triggering INPUT So @ Each fli-flop can be used independently wpuT 1s + [a] GND © Direct set and reset inputs Vee 2k input © Qand @ outputs 7 | © Wide operating temperature range (T, = -20~+75°C) Clock INPUT 2T —» [6] ip Sos] 7] — 20 jours DIRECT SET 28> —» CHUNK wy of 0) ~+ 20 APPLICATION inecr Reset om, + fat} Yay = 2) inpur General purpose, for use in industrial and consumer INPUT equipment, FUNCTIONAL DESCRIPTION Outline 16P4 While T is high, signals J and K are put in the read-in state, FUNCTION TABLE tote 1) - and when T changes from high to low, the J and K signals [ty7T=]sfl[.s.frijpesfl.] immmediately before the change emerge in outputs Q and Px [ec | H x [ox Taw fe | © in accordance with the function table. By using Sp and bet eet SH Pu | # | Rp this IC can be made into a direct R-S flip-flop. When Pox [oe foe x eae ae] both Sp and Rp are low, @ = @ = high. However, when ee both of them change to high at the same time, the status of puj se Pate Ta | Puy # | Q and © cannot be anticipated. For use as a J-K flip-flop, ee 8p and Fp must be kept in high, a Also available is M74LS112AP with the same functions [4 ~[ nw ] w [ x 1x Je? [| and, electrical characteristics. This offers easy mounting jow1 |: yamnorvonm ih 0 owlevel (opative aye wing) with Voc positioned at pin 16 and GND at pin 8. X 5 Irrelevant 4 = G= high when Sp ~ Fig = low and so when both 55 and RG are set high, the satus of © and @ cannot be anticipated eve of O before the indicated steady state input conditions wee extablshed GP: love of B before the inczated steady-state input conditions were established Toggle : Complemant of previous state with 4 ansiion of outputs BLOCK DIAGRAM (EACH FLIP-FLOP) oumur To J at Dip 09 ounur = + RET Feo a oe O% in Neu —— input Peo INeur KO m— UG O4 insur T clock INPUT OOOO % MITSUBISHI : 2-80 FiccTer.
DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET ABSOLUTE MAXIMUM RATINGS (12 = ~20~ +750, unissotnewise noted) Poraneter Conditions Une Tos Sopp votoge os. -7 v [vif orci os. +5 v Operating fee o7enblon emperaure onge 2-475 | Storage terperaure rage I --507 te RECOMMENDED OPERATING CONDITIONS (to~—20~ +15, soles otheoise sot) 5 | 525) v [ton | Honeetonpurewen [vowze.ry [a | = 400 | uA [aso fe pm | ELECTRICAL CHARACTERISTICS (Ta=—20~ +75, unies otrenvse not) Symba Paranete Test cndivons uni Lew! pol oe] vy Input ela voltage Voo=4.75V. lig = — 18mA ee ee TVeo=4.75V.-0.8V u High tee utout vloge | >| a4 al 3 “ | W=2V. low=—400W8 2 8 Vow | Habe inputeucrent | Yoo=4.75v Joy =a oe v snpu veosv.ys2v [loc =8ma os | 0s] Vv Veo=5.95V 20 yon —_ " tie | towel np curent r | ~ : 1 a re [orf ad Neon os; ma c ; ss) T o4 Me owrtevel ovtous volaa ‘Sp. Ao. T W=0.4V (Note 2) =0.8 | mA [es | Sarcraronpremen need | Meo 5.28V. Wo=OV = =100 | mA SO es) na
7 All ypicalvalus are ot Voo SV, Ta=25'¢
Note 2: 5p and Rip should not both be set to 0.4V simultaneously. Note 4: Supply current measurements should be done with Q and @ set alternately high and T should be set low during actual measurement. SWITCHING CHARACTERISTICS (voo=$V. Ta=25'C, vats otherwise nous) Tm Symtet Poramate - a Cowsorhighieve, high-to-lowsevel output propagation a Lowi, iho torteel vip Brabant 7 | 2) ns [tor | tine, rom 55, Ap 10.7 7 [20 as MITSUBISHI . ate MirsuBis 2-81
. MITSUBISHI LSTTLs DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET TIMING REQUIREMENTS (voo~ 5. To=25%, unies otherwise noted) ce Clock input F igh pul width _ [20 | 2 [ys Two oy | Direct st, rer pul wath _ a] | ns | tr Gockisetine 0 | 100 | te] eioc ta tine 300 | 100_| Setup time high J, K 10 [20 [ie [ns Setup time ow 3, K 10 [ao [oe | ns [tno | Hold ime nah J, Kio [oe [=o [Ts | Hold time low J.K 10 a Note5: Messurement circuit INPUT Voc OUTPUT (11 Tha pulse generator (PG) has the following characteris [> ] bur PRR INE, = Er, = Bt = 500s, | Vp = 3vpe, 29 = 508 sap: rt (2) Cites robe and jp capacitors, TIMING DIAGRAM (Reference level = 1.3V) tsu(L) thi) suc) thw) two) \\ Bo ) aK j 5 wih)
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werw) | Q @ leva} oH —| te Ht, ° it Q Frau Leng ced Note: The shaded seas indicate when the input i permitted o change for predict abe output performance 9. MITSUBISHI 2-82 ELECTRIC
; . MITSUBISHI LSTTLs _.. PACKAGE OUTLINES . MITSUBISHI {DGTL LOGIC} O7E D J veusae7 00135b1 3 I : T-10-20 : TYPE 14P4 14-PIN MOLDED PLASTIC DIL . Dimension inmm : 1903 . i oo oa aa on . . cae . | Wooo oe em (EER | O.5MIN|3MIN | 07 2:88 | . 15284 TYPE 16P4 16-PIN MOLDED PLASTIC DIL ~ : ==. Dimension in mm i 9733 : so, ee | poo eo : b olf a : aa . MOA a ae aman | 2.540.258 0.52011 1.6~10 | 1233 eh . TYPE 20P4 20-PIN MOLDED PLASTIC DIL Dimension in mm 26403 . : bt i : ° 7.62£0.3 TOOUDDOOOo oe flo . . . 0.5MiN | aMiN | ozrto-ar Hl aseroos| |S*% rs 28-3 1283 16-10 .