PS12033

PS12033 MITSUBISHI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 5

Technical content

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12033 FLAT-BASE TYPE INSULATED TYPE Mar. 2002 PS12033 INTEGRATED FUNCTIONS AND FEATURES

• Converter bridge for 3 phase AC-to-DC power conversion.
• 3 phase IGBT inverter bridge configured by the latest 3rd. generation IGBT and diode technology.
• Inverter output current capability IO (Note 1): APPLICATION Acoustic noise-less 0.4kW/400V AC Class 3 phase inverters, motor control applications, and motors with built-in small size inverter package PACKAGE OUTLINES Type Name PS12033 IO (100%) 1.8Arms IO (150%; 60sec) 2.7Arms Motor Rating 0.4 kW/400V AC (Note 1) : The inverter output current is assumed to be sinu- soidal and the peak current value of each of the above loading cases is defined as : IOP = IO × √2, TC < 100°C (Fig. 1) MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12033 FLAT-BASE TYPE INSULATED TYPE Terminals Assignment : 1. P2 2. P1 3. R 4. S 5. T 6. N1 7. N2 8. U 9. V 10. W 11. F O 12. Vamp 13. GND 14. WN 15. VN 16. UN 17. WP 18. VP 19. UP 20. TH 21. VD 22. NC 23. CBW– 24. CBW+ 25. CBV– 26. CBV+ 27. CBU– 28. CBU+ 1.4 12.5 20.4 12.5 12.5 11.5 4-φ4 30.48 22.8612 33.5 2 6 3.5 7.62 7.62 9.5 15 24 6.5 463 3 792.5 2.5 2 8.5 39±0.2 95±0.2 –0.4 0103 –0.4 073 0.5 0.5 (13.04)9 (8) (9) (10) (11)(22)(23) (25)(28) 7.62 4-R2 8-R1 4-R4 INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• P-Side IGBTs : Drive circuit, high-level-shift circuit, Bootstrap circuit supply scheme for single control-power-source drive, and Under voltage (UV) protection,
• N-Side IGBTs : Drive circuit, DC-Link current sense and amplifier circuits for over-current protection, Control-supply under-voltage (UV) protection, and fault output (FO ) signaling circuit.
• Fault Output : N-side IGBT short circuit (SC), over-current (OC), and control supply under-voltage (UV).
• Inverter Analog Current Sense : N-Side IGBT DC-Link Current Sense.
• Input Interface : 5V CMOS/TTL compatible, Schmitt Trigger input, and Arm-Shoot-Through interlock protective function.

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12033 FLAT-BASE TYPE INSULATED TYPE Mar. 2002 W V T S R U VD UP VP WP UN VN WN FO V(amp) GND TH Input signal conditioning (Interlock circuit) Level shifter Drive circuit Drive circuit UV Protection UV Protection Fo Circuit OC/SC Protection INTERNAL FUNCTIONS BLOCK DIAGRAM MAXIMUM RATINGS (Tj = 25°C) INVERTER PART CONVERTER PART CONTROL PART (Fig. 2) ConditionSymbol Item Ratings Unit Applied between P2-N2 Applied between P2-N2, Surge-value Applied between P2-U.V.W, U.V.W-N2 Applied between P2-U.V.W, U.V.W-N2 (Pulse) T C = 25°C, “( )” means IC peak value VCC VCC(surge) VP or VN VP(S) or VN(S) ±Ic(±Icp) Supply voltage Supply voltage (surge) Each IGBT collector-emitter static voltage Each IGBT collector-emitter switching voltage Each IGBT collector current 900 1000 1200 1200 ±5 (±10) V V V V A ConditionSymbol Item Ratings Unit 3φ rectifying circuit 1 cycle at 60Hz, peak value non-repetitive Value for one cycle of surge current V RRM Ea IO IFSM I2t Repetitive peak reverse voltage Recommended AC input voltage DC output current Surge (non-repetitive) forward current I 2t for fusing 1600 440 120 V Vrms A A A Symbol Item Ratings Unit VD , VDB VCIN VFO IFO Iamp Supply voltage Input signal voltage Fault output supply voltage Fault output current DC-Link IGBT current signal Amp output current –0.5 ~ 20 –0.5 ~ +7.5 –0.5 ~ +7.5 V V V mA mA

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12033 FLAT-BASE TYPE INSULATED TYPE Mar. 2002 TOTAL SYSTEM (Note 2) : The indicated values are specified considering the safe operation of all the parts within the ASIPM. The max. ratings for the ASIPM power chips (IGBT & FWDi) is Tj < 150. THERMAL RESISTANCE ELECTRICAL CHARACTERISTICS (Tj = 25°C, VD = 15V, VDB = 15V unless otherwise noted) ConditionSymbol Item Ratings Unit (Note 2) (Fig. 3)

60 Hz sinusoidal AC applied between all terminals and

the base plate for 1 minute. Mounting screw: M3.5 Tj Tstg TC VISO Junction temperature Storage temperature Module case operating temperature Isolation voltage Mounting torque –20 ~ +125 –40 ~ +125 –20 ~ +100 2500 0.78 ~ 1.27 Vrms N ·m ConditionSymbol Item Ratings Inverter IGBT (1/6) Inverter FWDi (1/6) Converter Di (1/6) Case to fin, thermal grease applied (1 Module) Rth(jc) Q Rth(jc)F Rth(jc)FR Rth(cf) Junction to case Thermal Resistance Contact Thermal Resistance Min. °C/W °C/W °C/W °C/W Typ. Max. 2.5 4.5 2.5 0.05 Unit Short circuit endurance (Output, Arm, and Load, Short Circuit Modes) Switching SOA Tj = 25°C, Input = ON, Ic = 5A, VD = VDB = 15V (Shunt voltage drop not included) Tj = 25°C, –IC = 5A Tj = 25°C, IFR = 5A VR = VRRM , Tj = 125°C 1/2 Bridge inductive, Input = 5V ↔ 0V VCC = 600V, IC = 5A, Tj = 125°C VD = 15V, VDB = 15V Note: ton, toff include delay time of the internal control circuit. ConditionSymbol Item Ratings Min. V V V mA µs µs µs µs µs Typ. Max. 0.3 1.2 0.5 2.2 0.9 0.2 3.6 3.5 1.5 2.0 1.4 4.0 1.6

• No destruction
• FO output by protection operation
• No destruction
• No protecting operation
• No FO output Collector-emitter saturation voltage FWDi forward voltage Converter diode voltage Converter diode reverse current Switching times FWDi reverse recovery time VCE(sat) VEC VFR IRRM ton tc(on) toff tc(off) trr CC ≤ 800V, Input = 5V → 0V (One-Shot) –20˚C ≤ Tj(start) ≤ 125°C, 13.5V ≤ VD = VDB ≤ 16.5V @V CC ≤ 800V, Input = 5V ↔ 0V, Tj ≤ 150°C IC < OC trip level, 13.5V ≤ VD = VDB ≤ 16.5V Unit (Fig. 3) CASE TEMPERATURE MEASUREMENT POINT TC LABEL

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12033 FLAT-BASE TYPE INSULATED TYPE Mar. 2002 ELECTRICAL CHARACTERISTICS (Tj = 25°C, VD = 15V, VDB = 15V unless otherwise noted) (Note 3) : The dead-time has to be set externally by the CPU; it is not part of the ASIPM internal functions. (Note 4) : Fault output signaling is given only when the internal OC, SC, & UV protection circuits are activated. The OC, SC and UV protection (and fault output) operate for the lower arms only. The OC and SC protection Fault output is given in a pulse format while that of UV protection is maintained throughout the duration of the under-voltage condition. Tj = 25°C, VD = 15V, Vin = 5V Tj = 25°C, VD = VDB = 15V, Vin = 5V Applied between input terminal-Inside power supply TC ≤ 100°C, Tj ≤ 125°C Relates to corresponding inputs T C = –20°C ~ +100°C (Note 3) Relates to corresponding input (Fig. 6) IC = IOP(100%) VD = 15V IC = IOP(200%) Tj = 25°C (Fig. 4) IC = IOP(250%) VD = 15V IC = 0A (Fig. 4) Tj = 25°C (Fig. 5) Tj = 25°C (Fig. 5) Tj = 25°C (Fig. 5) Tj = 25°C (Fig. 5) –20°C ~ 100°C TC = Tj = 25°C Tj = 25°C (Note 4) Open drain output (Note 4) Tc = 25°C Resistance at 25°C, 50°C Circuit current Circuit current Input on threshold voltage Input off threshold voltage Input pull-up resistor PWM input frequency Input interlock sensing Inverter DC-Link IGBT current sense voltage output signal Inverter DC-Link IGBT current sense voltage output limit Over current trip level Over current delay time Short circuit trip level Short circuit delay time V D UV trip level VD UV reset level VDB UV trip level VDB UV reset level UV delay time Fault output pulse width Fault output current Thermistor Resistance Thermistor B constant ConditionSymbol Item Ratings ID IDB Vth(on) Vth(off) R i fPWM tdead tint Vamp(100%) Vamp(200%) Vamp(250%) Vamp(0) OC t OC SC tSC UV D UV Dr UV DB UV DBr tdV tFO IFo(H) IFo(L) R TH B Min. mA mA V V kΩ kHz µs ns V V V mV A µs A µs V V V V µs ms µA mA kΩ K Typ. Max. 0.8 2.5 4.0 1.5 3.0 5.0 7.6 11.0 11.5 10.1 10.6 1.0 9.5 1.4 3.0 100 2.0 4.0 9.1 13.7 12.0 12.5 10.8 11.3 1.8 3450 2.0 4.0 2.5 5.0 100 12.75 13.25 11.6 12.1 10.5 Unit Supply circuit under voltage protection RECOMMENDED OPERATING CONDITIONS V V V V/µs V V µs kHz µs 800 16.5 16.5 0.8 5.0 100 13.5 13.5 4.0 4.0 Applied across P2-N2 terminals Applied between V D -GND Applied between CBU+ & CBU–, CBV+ & CBV–, CBW+ & CBW – Applied between UP • VP • WP • UN • VN • WN and GND Relates to corresponding inputs TC ≤ 100°C, Tj ≤ 125°C ConditionSymbol Item Ratings VCC VD VDB ∆VD , VDB VCIN(ON) VCIN(OFF) tdead TC fPWM tXX Supply voltage Supply voltage Supply voltage Supply voltage ripple Input on voltage Input off voltage Arm shoot-through blocking time Module case operating temperature PWM Input frequency Allowable input on-pulse width Min. Typ. Max. 600 15.0 15.0 Unit 200 3001000

0 Vamp (V)

Vamp (200%) Vamp (100%) VD = 15V Tj = 25°C Vamp DC-LINK IGBT Current (%), (IC = IO ✕ 2) (Fig. 4) INVERTER DC-LINK IGBT CURRENT ANALOGUE SIGNALING OUTPUT (TYPICAL) Arm shoot-through blacking time

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12033 FLAT-BASE TYPE INSULATED TYPE Mar. 2002 SC Ic(A) OC tw (µs) Over current trip level Collector current Short circuit trip level 102 CURRENT ABNORMALITY PROTECTIVE FUNCTIONS ARM-SHOOT-THROUGH INTER-LOCK PROTECTIVE FUNCTION Protection is achieved by monitoring and filtering the N-side DC-Bus current. When a current trip-level is exceeded all the N-side IGBTs are intercepted (turned OFF) and a fault-signal is output. After the fault-sig- nal output duration (1.8m sec (typ.)@25°C), the interception is Reset at the following OFF input signal level (more than 4.0V). (Fig. 5) P-Side Input Signal : VCIN(p) N-Side Input Signal : VCIN(n) ON ON P-Side IGBT Gate : VGE(p) N-Side IGBT Gate : VGE(n) a1 b4 b1a4 (Fig. 6) Description: (1) During the ON-State of either of the upper-arm or the lower-arm IGBT, the inter-lock protection circuit blocks any erroneous ON pulses (re- sulting from input noise) from triggering the other arm IGBT and thus it prevents the arm-shoot-through situation. (2) When two ON-signals are received for both the upper and the lower arms, the signal received first will be passed to the IGBT and the sec- ond signal will be blocked. The second signal will be passed to its corresponding IGBT immediately after the first signal is OFF. Note: This protective function provides no fault signaling output. The Dead-Time has to be set using the micro-controller (CPU). b1. N-side normal ON-signal ⇒ N-side IGBT gate turns ON. b2. Simultaneous ON-signals ⇒ P-side IGBT gate remains OFF. b3. N-side receives OFF-signal ⇒ N-side IGBT gate turns OFF. b4. Immediately after (b3) ⇒ P-side IGBT gate turns ON. Operation: a1. P-side normal ON-signal ⇒ P-side IGBT gate turns ON. a2. N-side erroneous ON-signal ⇒ N-side IGBT gate remains OFF. a3. While P-side ON-signal remains ⇒ P-side IGBT gate remains ON. a4. N-side normal ON-signal ⇒ N-side IGBT gate turns ON. RECOMMENDED I/O INTERFACE CIRCUIT (Fig. 7) FO Vamp GND ASIPM5V VD(15V) CPU 5.1kΩ 10kΩ 0.1nF Up, Vp, Wp, Un, Vn, Wn