PS11037

PS11037 MITSUBISHI | Alldatasheet

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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11037 FLA T-BASE TYPE INSULATED TYPE Jan. 2000 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. PS11037 INTEGRATED FUNCTIONS AND FEATURES

• 3 phase IGBT inverter bridge configured by the latest 3rd. generation IGBT and diode technology.
• Inverter output current capability IO (Note 1): APPLICATION Acoustic noise-less 3.7kW/200V AC Class 3 phase inverters, motor control applications, and motors with built-in small size inverter package PACKAGE OUTLINES MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11037 FLAT-BASE TYPE INSULATED TYPE INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• P-Side IGBTs : Drive circuit, high-level-shift circuit, bootstrap circuit supply scheme for Single Control-Power-Source drive, and un- der voltage (UV) protection.
• N-Side IGBTs :Drive circuit, DC-Link current sense and amplifier circuits for overcurrent protection, control-supply under-voltage protection (UV), and fault output (FO ) signaling circuit.
• Fault Output : N-side IGBT short circuit (SC), over-current (OC), and control supply under-voltage (UV).
• Inverter Analog Current Sense : N-Side IGBT DC-Link Current Sense.
• Input Interface : 5V CMOS/TTL compatible, Schmitt T rigger input, and Arm-Shoot-Through interlock protective function. (Fig. 1) 95 – 1 85 – 0.3 20.4 – 1 Terminals Assignment 17 – 0.8 3 – 0.5 30.7 – 0.5 8 – 0.5 62.35 – 0.8 74 – 1 0.5 4 23.523.5 (31.65) 50.8 – 0.8 12.7 – 0.3 59 – 0.3 3.5 9 24.5 (4-f5) 4-f4.6 (MOUNTING HOLE) 2.5 71 (82.1) (35) 21 22 23 24 25 34 7 1656 61 8 0.5 42 (18.5)

1 CBU+

2 CBU–

3 CBV+

4 CBV–

5 CBW+

6 CBW–

15 Vamp

16 GND

Lot.No (Note 1) : The inverter output current is assumed to be sinu- soidal and the peak current value of each of the above loading cases is defined as : IOP = IO × √2, TC < 100°C PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Type Name PS11037 IO (100%) 17.0Arms IO (150%; 60sec) 25.5Arms Motor Rating 3.7 kW/200V AC

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11037 FLA T-BASE TYPE INSULATED TYPE Jan. 2000 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. W V N P U VD UP VP WP UN VN WN FO V(amp) GND UV Protection Fo Circuit Level shifter Drive circuitDrive circuit UV Protection OC/SC Protection Input signal conditioning (Interlock circuit) INTERNAL FUNCTIONS BLOCK DIAGRAM ConditionSymbol Item Ratings Unit Applied between P-N Applied between P-N, Surge-value Applied between P-U.V .W, U.V.W-N Applied between P-U.V .W, U.V.W-N (Pulse) TC = 25°C, “( )” means IC peak value VCC VCC(surge) VP or VN VP(S) or VN(S) ±Ic(±Icp) Supply voltage Supply voltage (surge) Each IGBT collector-emitter static voltage Each IGBT collector-emitter switching voltage Each IGBT collector current 450 500 600 600 ±50 (±100) V V V V A MAXIMUM RATINGS (Tj = 25°C) INVERTER P ART Symbol Item Ratings Unit VD , VDB VCIN VFO IFO Iamp Supply voltage Input signal voltage Fault output supply voltage Fault output current DC-Link IGBT current signal Amp output current –0.5 ~ 20 –0.5 ~ +7.5 –0.5 ~ +7.5 V V V mA mA CONTROL PART (Fig. 2)

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11037 FLA T-BASE TYPE INSULATED TYPE Jan. 2000 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. VCE(sat) VEC ton tc(on) toff tc(off) trr ConditionSymbol Item Ratings Unit (Note 2) (Fig. 3)

60 Hz sinusoidal AC applied between all terminals and

the base plate for 1 minute. Mounting screw: M4 Tj Tstg TC VISO Junction temperature Storage temperature Module case operating temperature Isolation voltage Mounting torque –20 ~ +125 –40 ~ +125 –20 ~ +100 2500 0.98 ~ 1.47 Vrms N·m TOTAL SYSTEM (Note 2) : The indicated values are specified considering the safe operation of all the parts within the ASIPM. The max. ratings for the ASIPM power chips (IGBT & FWDi) is Tj < 150. ConditionSymbol Item Ratings Inverter IGBT (1/6) Inverter FWDi (1/6) Case to fin thermal, grease applied (1 Module) Rth(jc)Q Rth(jc)F Rth(cf) Junction to case Thermal Resistance Contact Thermal Resistance Min. °C/W °C/W °C/W THERMAL RESISTANCE Typ. Max. 1.75 2.4 0.031 Unit Short circuit endurance (Output, Arm, and Load, Short Circuit Modes) Switching SOA Tj = 25°C, Input = ON, Ic = 50A, VD = VDB = 15V (Shunt voltage drop not included) Tj = 25°C, –IC = 50A 1/2 Bridge inductive, Input = 5V ↔ 0V VCC = 300V, IC = 50A, Tj = 125°C VD = 15V, VDB = 15V Note:ton, toff include delay time of the internal control circuit. ConditionSymbol Item Ratings Min. V V µs µs µs µs µs Typ. Max. 0.3 0.6 0.5 1.6 0.5 0.12 2.9 2.9 1.5 1.0 2.5 1.2 Unit @V CC ≤ 400V, Input = 5V → 0V (One-Shot) –20°C ≤ Tj (start) ≤ 125°C, 13.5V ≤ VD = VDB ≤ 16.5V @V CC ≤ 400V, Input = 5V ↔ 0V , Tj ≤ 125°C IC < OC trip level, 13.5V ≤ VD = VDB ≤ 16.5V

• No destruction
• FO output by protection operation
• No destruction
• No protecting operation
• No F O output ELECTRICAL CHARACTERISTICS (Tj = 25°C, VD = 15V, VDB = 15V unless otherwise noted) Collector-emitter saturation voltage FWDi forward voltage Switching times FWDi reverse recovery time CASE TEMPERATURE MEASUREMENT POINT Tc LABEL (Fig. 3)

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11037 FLA T-BASE TYPE INSULATED TYPE Jan. 2000 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Applied across P-N terminals Applied between VD -GND Applied between CBU+ & CBU–, CBV+ & CBV–, CBW+ & CBW– Applied between UP • VP • WP • UN • VN • WN and GND Relates to corresponding inputs TC ≤ 100°C, Tj ≤ 125°C Tj = 25°C, VD = 15V, Vin = 5V Tj = 25°C, VD = VDB = 15V, Vin = 5V Applied between input terminal-inside power supply TC ≤ 100°C, Tj ≤ 125°C Relates to corresponding inputs T C = –20°C ~ +100°C (Note 3) Relates to corresponding input (Fig. 6) IC = IOP(100%) VD = 15V IC = IOP(200%) Tj = 25°C (Fig. 4) IC = IOP(250%) VD = 15V IC = 0A (Fig. 4) Tj = 25°C (Fig. 5) Tj = 25°C (Fig. 5) Tj = 25°C (Fig. 5) Tj = 25°C (Fig. 5) –20°C~100°C T C = Tj = 25°C Tj = 25°C (Note 4) Open collector output (Note 4) Circuit current (Average) Circuit current (Average) Input on threshold voltage Input off threshold voltage Input pull-up resistor PWM input frequency Arm shoot-through blocking time Input interlock sensing Inverter DC-Link IGBT current sense voltage output signal Inverter DC-Link IGBT current sense voltage output limit Over current trip level Over current delay time Short circuit trip level Short circuit delay time T rip level Reset level T rip level Reset level Delay time Fault output pulse width Fault output current Condition Symbol Item Ratings ID IDB Vth(on) Vth(off) R i fPWM tdead tint Vamp(100%) Vamp(200%) Vamp(250%) Vamp(0) OC tOC SC tSC UV D UV Dr UV DB UV DBr tdV t FO IFo(H) IFo(L) Min. mA mA V V kΩ kHz µs ns V V V mV A µs A µs V V V V µs ms µA mA Typ. Max. 0.8 2.5 2.2 1.5 3.0 5.0 86.7 11.0 11.5 10.1 10.6 1.0 1.4 3.0 100 2.0 4.0 102 181 12.0 12.5 10.8 11.3 1.8 2.0 4.0 2.5 5.0 100 117 12.75 13.25 11.6 12.1 Unit ELECTRICAL CHARACTERISTICS (Tj = 25°C, VD = 15V, VDB = 15V unless otherwise noted) ConditionSymbol Item Ratings VCC VD VDB ΔVD , VDB VCIN(ON) VCIN(OFF) tdead TC fPWM tXX Supply voltage Supply voltage Supply voltage Supply voltage ripple Input on voltage Input off voltage Arm shoot-through blocking time Module case operating temperature PWM Input frequency Allowabel input on-pulse width Min. V V V V/µs V V µs kHz µs RECOMMENDED OPERATING CONDITIONS Typ. Max. 13.5 13.5 4.0 2.2 300 15.0 15.0 400 16.5 16.5 0.8 5.0 100 Unit INVERTER DC-LINK IGBT CURRENT ANALOGUE SIGNALING OUTPUT (TYPICAL) Supply circuit under voltage protection 200 3001000

0 Vamp (V)

Vamp (200%) Vamp (100%) VD = 15V Tj = 25°C Vamp DC-LINK IGBT Current (%), (IC = IO 5 2) (Fig. 4) (Note 3) : The dead-time has to be set externally by the CPU; it is not part of the ASIPM internal functions. (Note 4) : Fault output signaling is given only when the internal OC, SC, & UV protection circuits are activated. The OC, SC and UV protection (and fault output) operate for the lower arms only . The OC and SC protection Fault output is given in a pulse format while that of UV protection is maintained throughout the duration of the under-voltage condition.

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11037 FLA T-BASE TYPE INSULATED TYPE Jan. 2000 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. SC Ic(A) OC tw (ms) Over current trip level Collector current Short circuit trip level 102 CURRENT ABNORMALITY PROTECTIVE FUNCTIONS ARM-SHOOT -THROUGH INTER-LOCK PROTECTIVE FUNCTION (Fig. 7) Protection is achieved by monitoring and filtering the N-side DC-Bus current. When a current trip-level is exceeded, all the N- side IGBTs are intercepted (turned OFF) and a fault-signal is out- put. After the fault-signal output duration (1.8msec (typ.)@ 25°C), the interception is Reset at the following OFF input signal level (more than 4.0V). (Fig. 5) P-Side Input Signal : VCIN(p) N-Side Input Signal : VCIN(n) ON ON P-Side IGBT Gate : VGE(p) N-Side IGBT Gate : VGE(n) a1 b4 b1a4 (Fig. 6) RECOMMENDED I/O INTERFACE CIRCUIT U P,VP,WP,UN ,VN ,WN Fo V(amp) GND(Logic) ASIPM5V VD (15V) CPU R R 5.1kW 10kW 0.1nF0.1nF Note : The parts shown dotted are to be used if noise filtering is required. Description: (1) During the ON-State of either of the upper-arm or the lower-arm IGBT, the inter-lock protection circuit blocks any erroneous ON pulses (re- sulting from input noise) from triggering the other arm IGBT and thus it prevents the arm-shoot-through situation. (2) When two ON-signals are received for both the upper and the lower arms, the signal received first will be passed to the IGBT and the sec- ond signal will be blocked. The second signal will be passed to its corresponding IGBT immediately after the first signal is OFF. Note: This protective function provides no fault signaling output. b1. N-side normal ON-signal ⇒ N-side IGBT gate turns ON. b2. Simultaneous ON-signals ⇒ P-side IGBT gate remains OFF. b3. N-side receives OFF-signal ⇒ N-side IGBT gate turns OFF . b4. Immediately after (b3) ⇒ P-side IGBT gate turns ON. Operation: a1. P-side normal ON-signal ⇒ P-side IGBT gate turns ON. a2. N-side erroneous ON-signal ⇒ N-side IGBT gate remains OFF . a3. While P-side ON-signal remains ⇒ P-side IGBT gate remains ON. a4. N-side normal ON-signal ⇒ N-side IGBT gate turns ON.