Power Management

PRM48AF480M400A00

Vicor Corporation

PRM??Regulator

Manufacturer: Vicor Corporation

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1 - PRM48A x 480 y 400A00 Rev. 1.0 PRM™ Regulator

FEATURES

 48V input (36V to 75V), non‐isolated ZVS buck‐boost regulator  20V to 55V adjustable output range  400W output power in 1.1in2 footprint  97.5% typical efficiency, at full load  1355 W/in3 (83 W/cm3) Power Density  4.01 MHrs MTBF (MIL‐HDBK‐217Plus Parts Count)  Pin selectable operating mode  Adaptive Loop  Remote Sense / Slave  Full VIChip Package  32.5mm x 22.0mm x 6.73mm TYPICAL APPLICATIONS  High Density Power Supply DC-DC rail outputs  High Density ATE system DC-DC power  Telecom NPU and ASIC core power  Communications Systems  Non-isolated and isolated power converters

DESCRIPTION

The VIChip™ PRM™ Regulator is a high efficiency converter, operating from a 36 to 75 Vdc input to generate a regulated 20 to 55 Vdc output. The ZVS buck – boost topology enables high switching frequency (~1.03 MHz) operation with high conversion efficiency. High switching frequency reduces the size of reactive components enabling power density up to 1355 W/in3. The Full VIChip package is compatible with standard pick-and -place and surface mount assembly processes with a planar thermal interface area and superior thermal conductivity. In a Factorized Power Architecture™ system, the PRM and down stream VTM™ current multiplier minimize distribution and conversion losses in a high power solution, providing an isolated, regulated output voltage. The PRM48A[x]480[y]400A00 has two selectable modes of regulation depending on the application requirements. In Adaptive Loop operation, the PRM48A[x ]480[y]400A00 utilizes a unique feed-for ward scheme that enables precise regulation of an isolated POL voltage without the need for remote sensing and voltage feedback. In Remote Sense operation, the internal regulation circuitry is disabled, and an external control loop and current sensor maintain regulation. This affords flexibility in the design of both voltage and current com pensation loops to optimize performance in the end application. PRODUCT RATINGS VIN = 36V to 75V P OUT = 400W VOUT= 48V (20V to 55V Trim) IOUT = 8.33A

2 - PRM48A x 480 y 400A00 Rev. 1.0 TYPICAL APPLICATIONS Typical Application: PRM48A[x]480[y]400A00 + VTM Adaptive Loop Configuration Typical Application: PRM48A[x]480[y]400A00 + VTM non-Isolated Remote Sense Configuration {1} Non-Isolated Configuration: –Out connected to -IN VT M Startup Pulse Adaptive Loop Temperature Feedback 36V to 75V VF: 20V to 55V LF RALRTRIM CF COUT CIN SGND SGND GND ON/OFF CONTROL VIN VOUT SEC_GND TRIM AL +IN -IN +OUT -OUT VC IFB VT REF/ REF_EN VAUX SHARE/ CONTROL NODE ENABLE SGND PRM SGND +IN -IN +OUT -OUT VC PC PRIMARY SECONDARY ISOLATION BOUNDRY TM VTM CFCIN 36V to 75V COUT LF VOLTAGE REFERENCE WITH SOFT START VOUT +IN -IN VOLTAGE SENSE AND ERROR AMPLIFIER Voltage Sense (SINGLE ENDED) External C urrent Sense and Feedback IN OUT GND SGND ON/OFF CONTROL VIN SGND SGND SGND SGND GND GND VOUT VTM Startup Pulse VREF TRIM AL +IN -IN +OUT -OUT VC IFB VT REF/ REF_EN VAUX SHARE/ CONTROL NODE ENABLE SGND PRM SGND +IN -IN +OUT -OUT VC PC PRIMARY SECONDARY ISOLATION BOUNDRY TM VTM {1} {1}

3 - PRM48A x 480 y 400A00 Rev. 1.0 PIN CONFIGURATION FULL VIC

4 - PRM48A x 480 y 400A00 Rev. 1.0 PIN DESCRIPTIONS Pin Signal Name Type Function Number A1, A2 SHARE (adaptive loop / slave operation) BIDIR Parallel sharing control bus for master-slave configuration. CONTROL NODE (remote sense operation) INPUT Modulator control node input. Driven by external error amplifier in remote sense operation. A3, A4 VT (adaptive loop operation) INPUT VTM TM input for temperature compensation. Leave disconnected for remote sense operation. B1, B2 ENABLE BIDIR Enables power supply when allowed to float high. 5.0V during normal operation. B3, B4 VAUX OUTPUT 9.0V auxiliary bias voltage. C1, C2 TRIM INPUT Selects operating mode. Adjusts output voltage in adaptive loop operation. C3, C4 IFB (Remote Sense operation) INPUT Current sense input for current limit and overcurrent protection in remote sense operation. Leave disconnected for adaptive loop operation. D1, D2 NC n/a Do not connect this pin. D3, D4 SGND INPUT Signal ground, reference for analog controls. Kelvin connected internally to –IN and -OUT. E1, E2 NC n/a Do not connect this pin. E3, E4 REF (adaptive loop operation) OUTPUT Reference voltage for internal error amplifier in adaptive loop operation. REF_EN (remote sense operation) OUTPUT Powers and enables external control circuit voltage reference in remote sense operation. F1, F2 AL (adaptive loop operation) INPUT Adaptive loop gain control. Sets the magnitude of the adaptive loop load line in adaptive loop operation. Leave disconnected for remote sense operation. F3, F4 VC OUTPUT Bias voltage to power VTM module during startup G1,G2 +IN INPUT POWER Positive input power terminal G3,G4 +OUT OUTPUT POWER Positive output power terminal H1,H2 -IN INPUT POWER RETURN Negative input power terminal. Connected internally to –OUT. H3,H4 -OUT OUTPUT POWER RETURN Negative output power terminal. Connected internally to -IN. PART ORDERING INFORMATION PART ORDERING INFORMATION Device Type Input Voltage Range Package Type Output Voltage x 10 Temperature Grade Output Power Revision Version PRM 48A F 480 T 400 A 00 PRM = PRM 48A = 36V – 75V F =Full VIC SMD T = Full VIC TH 480 = 48V T = -40 to 125 °C M = -55 to 125 °C 400 = 400W A 00 = AL / RS STANDARD MODELS PART NUMBER VIN PACKAGE TYPE VOUT TEMPERATURE POWER VERSION PRM48AF480T400A00 36V – 75V Full VIC SMD 48V (20V to 55V) -40 to 125 °C 400W AL / RS (Pin Selectable) PRM48AF480M400A00 -55 to 125 °C PRM48AT480T400A00 36V – 75V Full VIC TH 48V (20V to 55V) -40 to 125 °C 400W AL / RS (Pin Selectable) PRM48AT480M400A00 -55 to 125 °C

5 - PRM48A x 480 y 400A00 Rev. 1.0 ABSOLUTE MAXIMUM RATINGS The ABSOLUTE MAXIMUM ratings below are stress ratings only. Operation at or bey ond these maximum ratings can cause permanent damage to device. Electrical specifications do not apply when operating beyond rated operating conditions. Operating beyond rated operating conditions for extended period of time may affect device reliability. All voltages are specified relative to SGND unless otherwise noted. Positive pin current represents current flowing out of the pin. ABSOLUTE MAXIMUM RATINGS Parameter Comments Min Max Unit SHARE / -0.3 10.5 V +/- 10 mA -0.3 5.5 V +/- 10 mA +IN to –IN -0.5 10.5 V +/- 100 mA REF / REF_EN -0.5 18 V +/- 1.8 A Internal Operating Temperature Storage Temperature

6 - PRM48A x 480 y 400A00 Rev. 1.0 ELECTRICAL SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Specifications apply over all line and load conditions, and trim from 20 V to 55 V, unless otherwise noted; Boldface specifications apply over the temperature range of -40ºC < TINT < 125ºC; All Other specifications are at TINT = 25ºC unless otherwise noted. Attribute Symbol Conditions / Notes Min Typ Max Unit POWER INPUT SPECIFICATION Input Voltage Range V IN Continuous, operating 36 48 75 V VIN Slew Rate dV IN/dt 0 ≤ VIN ≤ 75V 0.001 1000 V/ms Initialization Voltage V INIT Internal micro controller initialization voltage 10 V Initialization Delay t INIT From V IN first crossing VINIT 5.0 7.0 9.0 ms No Load Power Dissipation P NL ENABLE HIGH, V IN = 48 V 2.4 3.5 W Input Quiescent Current I QC ENABLE LOW, V IN = 48V 14.5 20 mA Input Current I IN_DC I OUT = 8.33A, VIN =48 V, VOUT = 48 V 8.6 8.8 A Input Capacitance (Internal) C IN_INT Effective value, V IN = 48 V (see Fig. 13) 6 F Input Capacitance (Internal) ESR R CIN Effective value, V IN =48 V 1.5 mΩ POWER OUTPUT SPECIFICATION Output Current I OUT Standalone and Master operation, see Figure 1, SOA 8.33 A Output Power P OUT Standalone and Master operation, see Figure 1, SOA 400 W Switching Frequency F SW VIN = 48V VOUT = 48V, IOUT = 4.17A, TINT = 25°C 0.935 1.03 1.065 MHz Over line, load, trim and temperature, exclusive of burst mode 0.70 1.065 MHz Turn-ON Delay t ON From VIN first crossing VIN_UVLO+_SUPV to ENABLE high; tINIT expired µs From ENABLE released to ENABLE high, VIN applied, tOFF, and tiNIT expired Startup Sequence Timeout t STARTUP_SEQ From ENABLE high to startup sequence complete 17 ms Efficiency Ambient ηAMB VIN = 48V, VOUT = 48V, IOUT = 8.33A, TINT = 25°C 96.5 97.5 % VIN = 48V, VOUT = 48V, IOUT = 4.17A, TINT = 25°C 95.8 96.75 % VIN = 36V to 75V , VOUT = 48V, IOUT = 8.33A, TINT = 25°C 96.0 % VIN = 36V to 75V , IOUT = 8.33A, TINT = 25°C, over trim 92.0 % Efficiency Hot ηHOT VIN = 48V, VOUT = 48V, IOUT = 8.33A, TINT = 100°C 96.3 97.3 % VIN = 48V, VOUT = 48V, IOUT = 4.17A, TINT = 100°C 95.8 96.8 % VIN = 36V to 75V , VOUT = 48V, IOUT = 8.33A, TINT = 100°C 95.0 % VIN = 36V to 75V , IOUT = 8.33A, TINT = 100°C, over trim 91.0 % Efficiency Over Temperature η >50% load and VOUT =48 V; over temperature 95.0 % >50% load; over temperature and trim 90.0 % Output Discharge current I OD Average Value 0.5 mA Output Voltage Ripple V OUT_PP V IN =48 V, VOUT = 48 V, IOUT =8.33A, COUT_EXT = 0 F, 20 MHz BW 650 1000 mV Output Inductance (Parasitic) L OUT_PAR Frequency @ 1.00 MHz, Simulated J-Lead model 1.9 nH Output Capacitance (Internal) C OUT_INT Effective value, V OUT = 48 V (see Fig. 13) 6 F Output Capacitance (Internal) ESR R COUT Effective value, V OUT = 48 V 1.5 mΩ

7 - PRM48A x 480 y 400A00 Rev. 1.0

Specifications apply over all line and load conditions, and trim from 20 V to 55 V, unless otherwise noted; Boldface specifications apply over the temperature range of -40ºC < TINT < 125ºC; All Other specifications are at TINT = 25ºC unless otherwise noted. POWER OUTPUT SPECIFICATIONS: ADAPTIVE LOOP OPERATION Output Voltage Setpoint V OUT_SET No load, trim Inactive, Adaptive Loop load line inactive 47.04 48 48.96 V Output Voltage Trim Range V OUT 20 55 V Output Voltage Rise Time t RISE_VOUT From soft start initiated to output voltage settled 1.7 1.8 1.9 ms Output Voltage Load Regulation V OUT_REG_LOAD Adaptive Loop load line inactive 0.02 0.2 % Output Voltage Line Regulation V OUT_REG_LINE Adaptive Loop load line inactive 0.02 0.2 % Total Regulation Error V OUT_REG_TOTAL PRM Output Voltage, Adaptive Loop load line inactive 0.2 % Total AL Regulation Error V OUT_REG_AL VTM output voltage, total Adaptive Loop regulation, VOUT = 48 V, trim inactive 1 3 % VTM output voltage, total Adaptive Loop regulation, trim active, exclusive of external resistor tolerances 5 % Output Current Limit I LIMIT VIN = 48V, VOUT = 48V, TINT = 25°C, Constant current limit after supervisory limit detection time tLIM_SUPV 8.5 10.0 12.3 A Over line, load, trim and temperature 8.0 12.5 A Load Capacitance (Electrolytic) C LOAD_ALEL 0.1Ω ≤ ESR ≤1.0Ω, See Figure 31, total capacitance (CLOAD_ALEL + CLOAD_CER) ≤ 47uF 47 F Load Capacitance (Ceramic) C LOAD_CER 2mΩ ≤ ESR ≤ 200mΩ, See Figure 31 25 F Load Transient Voltage Deviation V TRANS 10% ↔ 100% load step, 10 A/µsec, 0 uF Cout, deviation from initial setpoint 4.8 V Load Transient Recovery Time t TRANS 10% to100% load step, 10 A/µsec, 0 uF Cout, Recovery to 90% of final value, Adaptive Loop load line inactive 100 s 10% to 100% load step, 10 A/µsec, 0 uF Cout, Recovery to 90% of final value, Adaptive Loop load line active, VAL=1.25V 500 s POWER OUTPUT SPECIFICATIONS: SLAVE OPERATION Rated Current Within an Array I OUT_ARRAY Slave operation within an array, up to 5°C case temperature differential, master-slave configuration 6.67 A Slave operation within an array, up to 30°C case temperature differential, master-slave configuration 5.83 A Rated Power Within an Array P OUT_ARRAY Slave operation within an array, up to 5°C case temperature differential, master-slave configuration 320 W Slave operation within an array, up to 30°C case temperature differential, master-slave configuration 280 W Current Sharing Difference (Master to Slave) IOUT_SHARE_MS Equal input, and output voltage at full load; VIN = 48 V, VOUT = 48 V 15 % Equal input and output voltage at full load; Over line and trim, with 25°C ≤ TC ≤ 100°C and ≤ 5°C part-part temp mismatch 15 % Equal input, and output voltage at full load; Over line and trim, with 25°C ≤ TC ≤ 100°C and ≤ 30°C part-part temp. mismatch 20 % Current Sharing Difference (Slave to Slave) IOUT_SHARE_SS Equal input, output, and SHARE voltage at full load; VIN = 48 V, VOUT = 48 V 5 % Equal input, output and SHARE voltage at full load; Over line and trim, with 25°C ≤ TC ≤ 100°C and ≤ 5°C part-part temp mismatch 10 % Equal input, output, and SHARE voltage at full load; Over line and trim, with 25°C ≤ TC ≤ 100°C and ≤ 30°C part-part temp. mismatch 15 % Maximum Array Size N PRMS_PARALLEL Maximum number of parallel devices, master-slave configuration 5 PRMs POWER OUTPUT SPECIFICATIONS: REMOTE SENSE OPERATION Output Voltage Range V OUT 20 55 V Rated Current Within an Array I OUT_ARRAY Remote Sense operation within an array, up to 5°C case temperature differential 7.5 A Remote Sense operation within an array, up to 30°C case temperature differential 5.8 A Rated Power Within an Array P OUT_ARRAY Remote Sense operation within an array, up to 5°C case temperature differential 360 W Remote Sense operation within an array, up to 30°C case temperature differential 280 W Current Sharing Difference I OUT_SHARE_RS Equal input, output, and CONTROL NODE voltage at full load; VIN = 48 V, VOUT = 48 V 5 % Equal input, output and CONTROL NODE voltage at full load; Over line and trim, with 25°C ≤ TC ≤ 100°C and ≤ 5°C part-part temp mismatch 10 % Equal input, output, and CONTROL NODE voltage at full load; Over line and trim, with 25°C ≤ TC ≤ 100°C and ≤ 30°C part-part temp. mismatch (worst case) 15 % Maximum Array Size N PRMS_PARALLEL Maximum number of parallel devices, Remote Sense configuration, CONTROL NODE externally driven 10 PRMs

8 - PRM48A x 480 y 400A00 Rev. 1.0

9 - PRM48A x 480 y 400A00 Rev. 1.0 SIGNAL SPECIFICATIONS Specifications apply over all line and load conditions, T INT = 25 ºC and output voltage from 20 V to 55V, unless otherwise noted. Boldface specifications apply over the temperature range of -40 ºC < TINT < 125 ºC (T-grade). ENABLE
The ENABLE pin enables and disables the PRM
In PRM array configurations, ENABLE pins should be connected in order to synchronize start up
ENABLE is 5.0V with 1.8mA source capability during normal operation Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit Analog Output Regular Operation ENABLE voltage V ENABLE 4.7 5.0 5.3 V ENABLE available current IENABLE_OP 1.8 mA Start up ENABLE source current I ENABLE_EN After t OFF 90 A Minimum time to start t OFF 13.5 15 16.5 ms Digital Input / Output Start up ENABLE enable threshold VENABLE_EN 2.5 3.2 V Standby ENABLE disable threshold VENABLE_DIS 0.97 2.4 V ENABLE resistance (external) RENABLE_EXT Resistance to SGND required to disable the PRM 235 Ω Digital Output Fault ENABLE sink current to SGND IENABLE_FAULT ENABLE voltage 1 V or above 4 mA VAUX: AUXILARY VOLTAGE SOURCE
Intended to power auxiliary circuits
9.0V during normal operation with 5mA source capability Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit Analog Output Regular Operation VAUX Voltage V VAUX 8.6 9.0 9.5 V VAUX Available Current I VAUX 5 mA VAUX Voltage Ripple V VAUX_PP Iout = 0A, CVAUX_EXT = 0. Maximum specification includes powertrain operation in burst mode. 100 400 mV Transition VAUX Capacitance (External) CVAUX_EXT 0.04 F VAUX Fault Response Time tFR_VAUX From fault recognition to VAUX = 1.5 V 30 s VC: VTM CONTROL
Pulsed voltage source used to power and synchronize downstream VTM during start up
14 V,10 ms typical voltage pulse Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit Analog Output Start up VC Voltage V VC_START Connected to VTM VC or equivalent, IVC = 115mA, CVC = 3.2uF 13 14 18 V VC Available Current I VC_START V C =14 V, VIN > 20 V 200 mA VC duration t VC 7 10 16 ms VC Slew Rate dVC/dt Connected to VTM or equivalent, I VC = 115mA, CVC = 3.2uF .02 .25 V/s ENABLE to VC delay t ENABLE_VC 20 s

10 - PRM48A x 480 y 400A00 Rev. 1.0 SGND: SIGNAL GROUND
All control signals must be referenced to this pin, with the exception of VC
SGND is internally connected to –IN and –OUT Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit Analog Input / Output Any Maximum Allowable Current ISGND -100 100 mA TRIM
TRIM is used to select operating mode and trim the output voltage in Adaptive Loop operation
Internal pullup to VCC_INT through10kΩ resistor
When pulled below 0.45V during power up, Remote Sense / Slave operation is selected
When allowed to pull up above 0.55 during power up, Adaptive Loop operation is selected
Operating mode is latched during power up and cannot be changed unless input power is cycled Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit Analog Input Normal Operation Internally generated VCC VCC_INT 3.20 3.28 3.36 V Internal Pullup Resistance to VCC_INT RTRIM_INT 0.5% tolerance resistor 9.83 10 10.18 kΩ Mode Detect Mode Detection Delay t MODE_DETECT From ENABLE high to mode detected, after VIN first applied 100 140 200 µs Remote Sense Enable Threshold VRS_MODE_EN Pull below this value during application of power to enable Remote Sense / Slave operation 0.45 V Remote Sense Disable Threshold V RS_MODE_DIS Pull above this value during application of power to enable Adaptive Loop operation 0.55 V TRIM (ADAPTIVE LOOP OPERATION ONLY)
Provides dynamic trim control over the PRM output voltage in Adaptive Loop operation
Sampled prior to every start up to detect if trim is active or inactive
Output voltage is equal to 20 times the voltage at the TRIM pin when applied TRIM voltage is within the active range
Trim state is latched during normal operation and cannot be changed until start up is initiated Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit Analog Input Start up Trim Enable Threshold V TRIM_EN Pull below this value during start up to enable trim control 3.10 V Trim Disable Threshold V TRIM_DIS Pull above this value during start up to disable trim control 3.20 V Minimum Trim Disable Resistance RTRIM_DIS_MIN Minimum TRIM resistance required to disable trim 10 MΩ Trim Capacitance (External) CTRIM_EXT 100 pF Trim Sample Delay t ENABLE_TRIM From ENABLE high to TRIM sampled 100 140 200 µs Normal Operation TRIM Pin Analog Range V TRIM_RANGE See Figure 26 1.00 2.75 TRIM Gain G TRIM V OUT / VTRIM, VTRIM applied within active range 20 V/V Trim Accuracy % ACC_TRIM Vout accuracy, exclusive of external resistor tolerance 0.5 2 % VOUT referred trim resolution VOUT_RES 200 mV Trim latency t TRIM_LAT 60 120 240 s Trim Bandwidth BW TRIM -3dB point 1.2 kHz

11 - PRM48A x 480 y 400A00 Rev. 1.0 AL: ADAPTIVE LOOP (ADAPTIVE LOOP OPERATION ONLY)
Provides Adaptive Loop load line programming in Adaptive Loop operation
Internal pullup to VCC_INT through10kΩ resistor
Sampled prior to every start up to detect if Adaptive Loop load line is active or inactive
Leave open to disable Adaptive Loop load line
Not used in Remote Sense operation Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit Analog Input Start up AL Enable Threshold V AL_EN Pull below this value during start up to enable AL load line 3.10 V AL Disable Threshold V AL_DIS Pull above this value to disable AL load line 3.20 V Minimum AL Disable Resistance RAL_DIS_MIN Minimum AL resistance required to disable AL load line 10 MΩ AL Capacitance (External) CAL_EXT 100 pF AL Sample Delay t ENABLE_AL From ENABLE high to AL sampled 100 140 200 µs Normal Operation Internally generated VCC VCC_INT 3.20 3.28 3.36 V Internal Pullup Resistance to VCC_INT RAL_INT 0.5 % tolerance resistor 9.83 10 10.18 kΩ AL Pin Analog Range V AL_RANGE 0 3.10 V AL Gain GAL Positive correction slope, VT inactive 0.5 Ω/V AL Load Line Accuracy % ACC_LL_AL Full load slope accuracy exclusive of external resistor tolerance 0.5 2 % AL load line resolution LL AL_RES 3 mΩ Maximum output referred compensation VOUT_AL_MAX Maximum increase from no load setpoint, V OUT ≤ 55V 5 V AL Latency t AL_LAT 60 120 240 s AL Bandwidth BW AL -3dB point 1.2 kHz VT: VTM TEMPERATURE (ADAPTIVE LOOP OPERATION ONLY)
VTM temperature compensation for Adaptive Loop regulation
Adjusts the slope of the Adaptive Loop load line to account for changes in VTM output resistance over temperature
Connect to TM pin of compatible downstream VTM to enable temperature compensation
Leave disconnected to disable temperature compensation Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit Analog Input Normal Operation Internal Resistance to SGND RVT_INT 80 kΩ VT Enable Threshold V VT_EN 2.1 V VT Disable Threshold V VT_DIS Pull below this value to disable VT temperature compensation 1.9 V VT Disable Default Temperature T VT_DIS Default AL temperature setting when VT disabled 25 °C VT analog range V VT_OP 2.18 3.98 V VT Temperature Coefficient TCVT VT within active range, referenced to 2.98V 30 %/V TCVT VTM TM voltage applied, .01V/°K, referenced to 25C 0.3 %/C VT Resolution TC VT_RES VTM TM voltage applied, .01V/°K 0.4 °C VT Latency t VT_LAT 60 120 240 s Bandwidth BW VT -3dB point 1.5 kHz

12 - PRM48A x 480 y 400A00 Rev. 1.0 REF / REF_EN REF: REFERENCE (ADAPTIVE LOOP OPERATION ONLY)
Functions as REF pin in Adaptive Loop operation
REF represents the internal voltage reference for the voltage control circuit
V OUT approximately equal to 20 times REF voltage Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit Analog Output Regular Operation REF Voltage V REF V OUT = 48V, Trim inactive 2.4 V REF to VOUT Scale Factor GREF_VOUT V OUT / VREF 20 V/V REF Resistance (External) RREF_EXT 10 MΩ REF Capacitance (External) CREF_EXT 200 pF REF Voltage Ripple V REF_PP includes burst mode, 20MHz BW 100 mV Transition ENABLE to REF Delay t ENABLE_REF ENABLE low to REF low 120 s VAUX to REF Delay t VAUX_REF VAUX = 8.1 V to REF soft start ramp initiated 1 ms REF_EN: REFERENCE ENABLE (REMOTE SENSE AND SLAVE OPERATION ONLY)
Functions as REF_EN pin in Remote Sense and Slave operation
REF_EN signals successful start up and powertrain ready to operate
Intended to power and enable the external feedback circuit reference in Remote Sense operation
3.25V, 4mA regulated voltage source Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit Analog Output Regular Operation REF_EN Voltage V REF_EN REF_EN unloaded 2.72 3.25 3.37 V REF_EN Source Impedance ROUT_REF_EN 50 100 Ω REF_EN Available Current IREF_EN 4 mA REF_EN Capacitance (External) CREF_EN_EXT 0.1 F REF_EN Voltage Ripple V REF_EN_PP includes burst mode, 20MHz BW 25 mV Transition ENABLE to REF_EN Delay tENABLE_REF_EN ENABLE low to REF_EN low 1 ms VAUX to REF_EN Delay t VAUX_REF_EN VAUX = 8.1 V to REF_EN high 1 ms

13 - PRM48A x 480 y 400A00 Rev. 1.0 SHARE / CONTROL NODE SHARE (ADAPTIVE LOOP AND SLAVE OPERATION ONLY)
Functions as SHARE pin in master slave array configuration
Current share bus for array operation (master/slave scheme)
Sources current and provides SHARE signal in master operation
Sinks constant current when externally driven in active range (Slave operation) Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit Analog Output Standalone / Master Operation SHARE Voltage Active Range VSHARE 0.79 7.40 V SHARE Available Current ISHARE V SHARE > 0.79V 2.5 mA SHARE Resistance to SGND RSHARE 93.3 kΩ Analog Input Slave Operation SHARE Sink Current I SHARE_SINK V SHARE > 0.79V 0.25 0.50 0.75 mA CONTROL NODE (REMOTE SENSE OPERATION ONLY)
Functions as CONTROL NODE pin in Remote Sense operation
Modulator control node voltage sets power train timing
Driven by external error amplifier in Remote Sense operation
Sinks constant current when externally driven in active range
Sources current, and clamps voltage to 0.79V when pulled below active range Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit Analog Input Regular Operation CONTROL NODE Voltage Active Range VCN 0.79 7.40 V CONTROL NODE Source Current ICN_LOW V CN < 0.79V 2.5 mA CONTROL NODE Sink Current ICN_SINK V CN > 0.79V 0.25 0.50 0.75 mA CONTROL NODE Resistance to SGND RCN 93.3 kΩ IFB: CURRENT FEEDBACK (REMOTE SENSE OPERATION ONLY)
Functions as IFB pin in Remote Sense operation
A voltage proportional to the PRM output current must be supplied externally to the IFB pin in order for the device to properly protect overcurrent events and to enable output current limit (clamp)
Overcurrent protection trip will cause instantaneous powertrain shutdown, detected after tBLNK
Not used for Adaptive Loop operation Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit Analog Input Regular Operation Current Limit (clamp) Threshold VIFB_IL VIN = 48V V; VOUT = 48V TINT = 25 °C 1.90 2.00 2.10 V Over Line, Trim, and Temperature 1.85 2.15 V Overcurrent Protection Threshold VIFB_OC Not Production Tested; Guaranteed by Design; TINT = 25 °C 2.58 2.69 2.80 V Not Production Tested; Guaranteed by Design; Over Line, Trim, and Temperature 2.09 2.17 V IFB Input Impedance R IFB 2.09 2.13 2.17 kΩ Current Limit Bandwidth BW IL 2.0 kHz NC: NO CONNECT
Reserved for factory use only
No connections should be made to these pins

14 - PRM48A x 480 y 400A00 Rev. 1.0 FUNCTIONAL BLOCK DIAGRAM +OUT -OUT L Cout +IN -IN Cin SHARE/ CONTROL NODE 57.6k 35.7k 1000pF ENABLE Modulator Enable TRIM 3.3V 10k 1000pF 10k NC NC 10k 10k 0.01uF AL 20k 60.4k VT 2200pF VAUX 0.01uF 2.1k 30.1 IFB 0.01uF REF/ REF_EN k 6800 pF Control and Monitoring OTP Undervoltage Lockout Output Short Circuit Overvoltage Lockout Output Overvoltage Protection Current Limit Voltage Reference 0.5mA 2.5mA Min Adaptive Loop IN OUT PGND SGND 1.58k 30.1k 3.3V Linear Regulator VCC SGND Internal VCC Regulator VC Error Amplifer PGNDSGND

15 - PRM48A x 480 y 400A00 Rev. 1.0 HIGH LEVEL FUNCTIONAL STATE DIAGRAM Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles. STARTUP SEQUENCE tON expired ENABLE: 1.8mA to HIGH VC Pulse REF_EN active Adaptive loop and trim modes latched RS mode latched at first ENABLE after Vin applied only Powertrain Active STANDBY SEQUENCE ENABLE: 10uA to LOW tOFF expired ENABLE: 90uA to HIGH Powertrain Stopped Application of Vin ENABLE rising edge ENABLE falling edge, Output OVP or OTP detected FAULT SEQUENCE ENABLE pulsed: 25mA to LOW Powertrain Stopped VIN > UVLO+ ENABLE falling edge, Output OVP, or OTP detected tSTARTUP_SEQ expired SUSTAINED OPERATION ENABLE: 1.8mA to HIGH Powertrain Active Input OVLO or UVLO, Output UVP, or UTP detected Short Circuit detected Input OVLO or UVLO, Output UVP, or UTP detected Fault Auto- recovery

16 - PRM48A x 480 y 400A00 Rev. 1.0 TIMING DIAGRAMS (Adaptive Loop operation page 1) Module Inputs are shown in blue; Module Outputs are shown in brown. REF VOUT ENABLE SHARE +IN VC VAUX TRIM Iout VVC_START 3.3V 2.4V tVC tBLNK INPUT POWER ON AND UV TURN‐ON AL ACTIVE INPUT OV INPUT OV RECOVERY ENABLE DISABLE ENABLE RELEASE FULL LOAD APPLIED OUTPUT OV tOFF tON tONtBLNK tBLNK tAUX_REF tPROT tPROT BIDIR BIDIR BIDIR OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT AL VINIT tOFF 48V 55V 2.75V 1.0V 20V TRIM INACTIVE AL = 1V tENABLE_VC VIN_OVLO VIN_UVLO VSHARE_MAX VSHARE_MIN ILIMIT VENABLE VENABLE_EN VOUT_OVP+ VOUT_MAX VOUT_NOM VOUT_MIN VAUX tSTARTUP_SEQ AL = 1V INPUT VREF FirstEnb: TR not low = not RS mode TR high = trim inactive for this enabled period AL not high = AL active for this enabled period TR high = trim inactive for this enabled period AL not high = AL active for this enabled period TR high = trim inactive for this enabled period AL not high = AL active for this enabled period Soft Start TRIM Ignored Vout increases by VAL * GAL * IOUT TRIM and AL pins sampled Soft Start Micro‐controller initialized Current sense activated, and output increase due to AL after tSTARTUP_SEQ expires

17 - PRM48A x 480 y 400A00 Rev. 1.0 TIMING DIAGRAMS (Adaptive Loop operation page 2) REF VOUT ENABLE SHARE +IN VC VAUX TRIM Iout VIN_OVLO VENABLE_EN VENABLE VVC_START VAUX VSHARE_MIN ILIMIT VSHARE_MAX INPUT POWER ON AND UV TURN‐ON OUTPUT SHORT CIRCUIT OUTPUT POWER LIMIT PROTECTION CURRENT LIMIT EVENT INPUT POWER OFF AND UV TURN‐OFF tOFF tSC tBLNK 20V INPUT BIDIR BIDIR BIDIR OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT 2.75V AL VINIT 1 V 3.3V 55V 2.4V 48V 1 V 2.4V 2.75V 3.3V OT SHUTDOWN AND RECOVERY ENABLE TOGGLING AL INACTIVE AND TRIM ACTIVE VOUT_MAX VOUT_MIN VOUT_NOM VIN_UVLO tSTARTUP_SEQ FirstEnb: TR not low = not RS mode TR not high = trim active for this enabled period AL high = AL inactive for this enabled period TR not high = trim active for this enabled period AL high = AL inactive for this enabled period TR high = trim inactive for this enabled period AL not high = AL active for this enabled period TR high = trim inactive for this enabled period AL not high = AL active for this enabled period tLIM_SUPV tSCR+tOFF tBLNK AL pin Ignored VOUT = VTRIM * 20 VOUT clamped to 55V for VTRIM > 2.75V AL active Vout increase due to Iout and AL after tSTARTUP_SEQ expires Operating Mode Trim and AL state detected Micro‐controller initialized

18 - PRM48A x 480 y 400A00 Rev. 1.0 TIMING DIAGRAMS (Remote Sense operation page 1) REF_EN VOUT ENABLE CONTROL NODE +IN VC VAUX TRIM IFB VENABLE_EN VENABLE VVC_START VCN_MAX VAUX VREF_EN tVC VIFB_OC tBLNK INPUT POWER ON AND UV TURN‐ON t < tBLNK QUICK OC (t<tBLNK) INPUT OV VIFB_IL INPUT OV RECOVERY ENABLE DISABLE ENABLE RELEASE FULL LOAD APPLIED LOAD RELEASE AND OUTPUT OV (SLOW F/B) tOFF tON tONtBLNK tBLNK tENABLE_REF_ENtAUX_REF_EN tPROT tPROT tENABLE_REF_EN VCN_MIN VIN_OVLO VIN_UVLO VOUT_OVP+ VINIT tENABLE_REF_EN This blue shaded region is where trim voltage is a don’t care. RS operating mode is latched. TRIM is ignored until Vin is removed. First Enable: Trim Low = RS mode RS mode detected and latched TRIM ignored for all subsequent start up events until VIN is removed Micro‐controller initialized

19 - PRM48A x 480 y 400A00 Rev. 1.0 TIMING DIAGRAMS (Remote Sense operation page 2) REF_EN VOUT ENABLE CONTROL NODE +IN VC VAUX TRIM IFB START UP WITH MINIMUM < dVIN/dt < 1.2V/ms OUTPUT SHORT CIRCUIT OUTPUT POWER LIMIT PROTECTION CURRENT LIMIT EVENT INPUT UV tOFF tSC <tBLNK tBLNKVCN_MAX VCN_MIN VIFB_OC VIFB_IL VENABLE VENABLE_EN VVC_START VREF_EN VAUX VIN_OVLO VIN_UVLO VINIT VOUT_OVP+ This blue shaded region is where trim voltage is a don’t care. RS operating mode is latched. TRIM is ignored until Vin is removed. First Enable: Trim Low = RS mode RS mode detected and latched TRIM ignored for all subsequent start up events until VIN is removed tSCR+tOFF Micro‐controller initialized

24 - PRM48A x 480 y 400A00 Rev. 1.0 GENERAL CHARACTERISTICS Specifications apply over all line and load conditions, T INT = 25 ºC and output voltage from 20 V to 55V, unless otherwise noted. Boldface specifications apply over the temperature range of -40 ºC < TINT < 125 ºC (T-grade). Attribute Symbol Conditions / Notes Min Typ Max Unit MECHANICAL Length L 32.3 32.5 32.8 mm Width W 21.8 22.0 22.3 mm Height H 6.48 6.73 6.98 mm Volume Vol No heat sink 4.81 cm3 (0.3) in3 Weight W 15 g Lead Finish Nickel 0.51 2.03 mPalladium 0.02 0.15 Gold 0.003 0.050 THERMAL Operating Internal Temperature T INT T Grade -40 125 ºC M Grade -55 125 ºC Thermal Impedance θINT-CASE 1 ºC/W θINT-LEAD 3 ºC/W Thermal Capacity 10 Ws/ºC ASSEMBLY Peak Compressive Force Applied to Case (Z-axis) Supported by J-Lead only 6 lbs 5.41 lbs / in2 Storage Temperature T ST T Grade -40 125 ºC M Grade -65 125 ºC Moisture Sensitivity Level MSL MSL 6, 245C Reflow MSL5, 225C Reflow ESD Rating Human Body Model, "JEDEC JESD 22-A114C.01" 1000 V Charged Device Model, "JEDEC JESD 22-C101D" 400 SOLDERING Peak Temperature During Reflow Under MSL 6 conditions above 245 ºC Under MSL 5 conditions above 225 ºC Maximum Time Above 217 ºC 150 s Peak Heating Rate During Reflow 1.5 2 ºC / s Peak Cooling Rate Post Reflow 2.5 3 ºC / s RELIABILITY AND AGENCY APPROVALS MTBF Telcordia Issue 2 - Method I Case 1; Ground Benign, Controlled 5.28 MHrs MIL-HDBK-217Plus Parts Count - 25C Ground Benign, Stationary, Indoors / Computer Profile 4.01 MHrs Agency Approvals / Standards CTUVUS EN60950-1, UL/CSA 60950-1 CE Mark Low Voltage Directive (2006/95/EC) ROHS 6 of 6

25 - PRM48A x 480 y 400A00 Rev. 1.0 PIN FUNCTIONS +IN, -IN Input power pins +OUT, -OUT Output power pins. Module cannot sink current. ENABLE This pin turns the supply on and off. The pin is both an input and an output and can provide the following features:  Delayed Start: upon application of voltage (>UVLO) to the module power input and after t off, the ENABLE pin will source a constant 90μA current.  Output enable: When ENABLE is allowed to pull up above the enable threshold, the ENABLE pin will pull up to 5.0V with 1.8mA source capability, and the module will be enabled.  Output disable: ENABLE may be pulled down externally in order to disable the module. Pull down resistance should be less than 235Ω to SGND.  Fault detection flag: The ENABLE 5.0V voltage source is internally turned off when a fault condition is latched. ENABLE control should be implemented using an open collector configuration. It is not recommended to drive this pin externally. VAUX: Auxiliary Voltage Source Use this pin to power external devices with a non-isolated

9.0 V supply, with up to 5 mA load capability, switched with

ENABLE input. Do not place a capacitor over 0.04 µF on this pin. SGND: Signal Ground This is a low current pin which provides a Kelvin connection to the PRM’s internal signal ground. Use this pin as the ground reference for external circuitry and signals to avoid voltage drops caused by high currents on power returns. In array configurations, SGND pins should be star connected at a single point. A series resistor (~1Ω) to the star location is recommended to decouple return currents. VC: VTM Control This output pin is used to temporarily provide V CC voltage to connected VTMs during start up. The pulse is nominally 14V, 10 ms wide. A VTM can self-power once its input voltage reaches 26V. The PRM output must be checked to make sure it reaches this threshold voltage before the VC pulse expires. TRIM The TRIM pin is used to select the operating mode and to trim the PRM output when Adaptive Loop operating mode is selected. The TRIM pin has an internal pull-up to V CC_INT through a 10 kΩ resistor. Operating Mode Select: If TRIM is pulled below 0.45 V during the first startup after VIN is applied, Remote Sense / Slave operation is selected. Otherwise, Adaptive Loop operation is selected. This selection persists until VIN is removed from the part, and is not changed by fault or disable events. ‐ Output Voltage Trim: Sets the output voltage of the PRM in Adaptive Loop operation. If TRIM is permitted to pull up to 3.20 V or higher during start up, trim is disabled, and the output is set to the nominal of 48 V. If TRIM is held between 1.00 V to 2.75 V during start up, trim is enabled, and the output is scaled by a factor of 20 resulting in an output voltage range of 20 V to 55 V. This selection persists until the PRM is restarted with the ENABLE pin, or due to fault auto-recovery. AL: Adaptive Loop (Adaptive Loop operation) This input pin allows you to set the Adaptive Loop load line. Every volt on this pin represents 0.5 Ω of positive output slope. There is an internal 10 kΩ pullup resistor to V CC_INT. If AL is permitted to pull up to 3.20 V or higher during start up, the Adaptive Loop load line is disabled. This selection persists until the PRM is restarted with the ENABLE pin, or due to fault auto-recovery. VT: VTM Temperature (Adaptive Loop operation) This pin is used in the Adaptive Loop compensation algorithm to account for the VTM output resistance variation as a function of temperature. The VTM TM pin provides this voltage, scaled as the temperature in K (Kelvin) divided by 100, so 25 °C is 2.98 V. Leave disconnected or pull below 1.9V to disable. The adjustment is fixed at 0.3 %/°C relative to the value at 25 °C

26 - PRM48A x 480 y 400A00 Rev. 1.0 REF: Reference (Adaptive Loop operation) This output pin allows you to monitor the internal reference voltage in Adaptive Loop operation. During normal operation it represents the output voltage scaled by a factor of 20. In Adaptive Loop operation this pin is for monitoring purposes only and should not be driven or loaded externally. REF_EN: Reference Enable (Remote Sense operation) In Remote Sense operation this pin outputs a regulated 3.25V, 4mA voltage source. It is enabled only after successful start up of the PRM powertrain REF_EN is intended to power the output current transducer and also the voltage reference for the external control loop. Powering the reference generator with REF_EN helps provide a controlled start up, since the output voltage of the system is able to track the reference level as it comes up. SHARE (Adaptive Loop and Slave operation) This bus sets the output current level for all the PRM modules when operating in an array (master-slave configuration). Connect them together among the modules in the shared bus. One PRM should be configured as a master by connecting TRIM for Adaptive Loop operation. All other PRMs should be configured as slaves by pulling their respective TRIM pins low. This pin can be used to monitor the error voltage externally. 0 to 100% load is represented by a voltage between 0.79 V and 7.40. CONTROL NODE (Remote Sense operation) In Remote Sense operation, this is the input to the modulator which determines the powertrain timing and ultimately the module output power. An internal 0.5 mA current sink is always active. The bi-directional buffer between CONTROL NODE and the modulator has two states. In normal operation, CONTROL NODE will be above the 0.79 V switching threshold, and will dr ive the modulator through the buffer. An internal 7.4V clamp determines the maximum output power that can be requested of the modulator. When CONTROL NODE falls below 0.79 V, the converter will stop switching. An internal circuit clamps the modulator input to 0.79 V, and a buffer will source up to 2.5 mA out of the pin at that clamp level. For this reason, the output impedance of the amplifier driving CONTROL NODE must be taken into account. A rail-to-rail operational amplifier with low output impedance is always recommended. The powertrain small signal (plant) response consists of a single pole determined by the load resistance, the powertrain equivalent output resistance, and the total output capacitance (internal and external to the module). Both the modulator gain and the equivalent output resistance vary as a function of line, load and output voltage. As the lo ad increases, the powertrain pole moves to higher frequency. As a result, the closed loop crossover frequency will be the highest at full load and lowest at minimum load. Figure 24 shows a reference AC small-signal model. Figure 24 – PRM48A[x]480[y]400A00 AC small signal model IFB: Current Feedback (Remote Sense operation) In Remote Sense operation, IFB is the input for the module output overcurrent protection an d current limit features. A voltage proportional to the powertrain output current must be applied to IFB in order for over current protection to operate properly. If the IFB voltage exceeds the IFB pin’s overcurrent protection threshold, the powertrain will st op switching. If the IFB voltage falls below the overcurrent pr otection threshold within t BLANK time, then the powertrain will i mmediately resume switching. Otherwise a fault is detected. The current limit threshold for the IFB pin is set lower than the protection threshold. When the IFB pin average voltage exceeds the current limit threshold, an internal integrator will activate a clamp amplifier which overrides the modulator input maximum level. This causes th e powertrain to maintain a constant output current. The bandwidth of this current lim it integrator is significantly slower than that of the CONT ROL NODE input. Therefore this current limit cannot be used in lieu of properly compensating the (external) control loop to avoid exceeding maximum current or power ratings for the device. VCN · GCN COUT_INT ICN_Low RCN rEQ_OUT rEQ_IN VIN CIN_INT

27 - PRM48A x 480 y 400A00 Rev. 1.0 DESIGN GUIDELINES The PRM48A[x]480[y]400A00 regulator is specifically designed to provide a controlled Factorized Bus distribution voltage for powering downstream VTM Transformer — fast, efficient, isolated, low noise Point-of-Load (POL) converters. The PRM48A[x]480[y]400A00 can be configured for two operating modes depending on the type of regulation required. In Adaptive Loop operation the regulation circuitry is enabled within the device and regulates the voltage at the output terminals. The PRM48A[x]480[y]400A00 has a programmable Adaptive Loop load line which can be used to compensate for downstream VTM output resistance allowing for precise point of load regulation without the need for remote sensing. In Remote Sense operation, the internal regulation circuitry is disabled and the voltage regulation circuitry is provided externally allowing for remote sensing directly at the point of load. In certain applications Remote Sense operation can improve regulation accuracy, and allow for operating with high amounts of load capacitance and optimizing load transient response. Operating Mode Selection The operating mode is selected through use of the TRIM pin. When the part is first enabled after V IN is applied, the TRIM voltage is sampled. The TRIM pin has an internal pull up resistor to VCC_INT, so unless external circuitry pulls the pin voltage lower, it will float up to VCC_INT. If TRIM is pulled lower than 0.45V during the first startup after V IN is applied, the part will be configured for Remote Sense / Slave operation, where the internal voltage regulation circuitry is disabled. In this case, for all subsequent operation the part will output a voltage dependent on the SHARE / CONTROL NODE voltage provided externally (either from an external regulation circuit or master PRM). To configure the part for Remote Sense or Slave operation, connect the TRIM pin to SGND. It is recommended to make this connection through a 0Ω jumper for troubleshooting purposes. If the sampled TRIM voltage is higher than 0.55V during the first startup after V IN is applied, then the part will be configured for Adaptive Loop operation, and the internal voltage regulation circuitry is enabled. The PRM will output a voltage dependent on the TRIM voltage, and will remain in this mode for as long as VIN is applied. To configure the part for Adaptive Loop operation, leave the TRIM pin disconnected, or apply a voltage/resistance within the specified range. The operating mode is detected and latched during the first start up after V IN is applied. This selection persists until VIN is removed from the part, and is not changed by fault or disable events. Changing the operating mode can only be done by removing VIN. DESIGN GUIDELINES (Adaptive Loop operation) In Adaptive Loop operation, the internal voltage control circuitry is enabled and the voltage at the output terminals is regulated. The part is nominally set to provide a fixed 48V output, and the TRIM pin can be used to adjust the output over the range of 20 V to 55 V. When used with a VTM, the AL pin provides ability to program an Adaptive Loop load line to compensate for the output resistance (R OUT) of a downstream VTM, while the VT pin provides temperature compensation to account for changes in the VTM ROUT over temperature. Trim Mode and Output Trim Control (Adaptive Loop operation) In Adaptive Loop operation, during any start up and after ENABLE transitions high, the TRIM pin voltage is sampled to determine if trim is active or inactive. If the sampled TRIM voltage is higher than 3.20V then the PRM will disable trim. In this case, for all subsequent operation the output voltage will be programmed to the nominal output of 48V and the TRIM pin will be ignored during normal operation. If the sampled TRIM voltage is between 1.0 V and 3.10 V then the PRM will activate trim mode and it will remain in this mode as long as the PRM is operating. This selection persists until the PRM is restarted with the ENABLE pin, or due to fault auto-recovery.

30 - PRM48A x 480 y 400A00 Rev. 1.0 Setting the Adaptive Loop Load Line (Adaptive Loop operation) To determine an appropriate value for the compensation slope LL_AL) it helps to reflect the VTM’s output resistance to the input side of the VTM. A resistance on the output side of the VTM is scaled by the VTMs transformer ratio (KVTM) squared as defined by equation (2): ଵ ௄ೇ೅ಾ ሻଶ (2) Where ROUT_VTM is the VTM output resistance at 25°C KVTM is the VTM transformer ratio VIN/VOUT For our hypothetical VTM from above (with KVTM = 1/4 and ROUT_VTM = 10mΩ) the output resistance reflected over to the input would be equal to 160 mΩ. For this example, RLL_AL should be set to -160 mΩ to approximately cancel at 25°C the inherent load line from the VTM. R LL_AL is set by the voltage difference between the AL pin and SGND pin, VAL, per the following formula: VAL ≤ 3.10V Where VAL is the voltage on the AL pin VAL is sampled by a 10-bit ADC, whose input is connected to VCC_INT through a 10 kΩ pull up resistor. This pull up disables the AL engine when the AL pin is left open. VAL can be actively set with a DAC that is ground referenced to SGND. VAL can be passively set by connecting a resistor, RAL, from AL to SGND such that the voltage divider made with VCC_INT and the 10 kΩ pull up yields the desired VAL. The formula for calculating this resistor is provided in Equation (4). ஺௅ ൌ ଵ଴௞ஐ ∙௏ಲಽ (4) Figure 29: AL Connections Similar to TRIM, AL is sampled during every start up to determine if the Adaptive Loop load line is enabled or disabled. If the AL pin is allowed to pull up to 3.20V or higher during start up, then then the PRM will disable the Adaptive Loop load line as long as the PRM remains operating. In this case, for all subsequent operation the output voltage will be remain at the set voltage, and the AL pin will be ignored. This selection persists until the PRM is restarted with the ENABLE pin, or due to fault auto-recovery. When AL is enabled, the voltage at this pin is sampled at 120 µs intervals to determine the load line. The load line can be adjusted during normal operation, however it is not recommended to use this pin in an external analog feedback loop. Adaptive Loop Temperature Compensation (Adaptive Loop operation) By connecting the VT pin of the PRM to the VTM’s TM pin, the PRM is able to monitor the internal temperature of the VTM. Knowing the VTM’s internal temperature and the temperature coefficient of the VTM’s R OUT, which is preprogrammed into the PRM’s microcontroller, the AL engine is able to scale the nominal value of RLL_AL (set by the AL pin) to track the VTM’s ROUT over temperature. In this way the output resistance of the PRM can be tuned to cancel the output resistance of the VTM with the addition of a single resistor across the AL pin and a connection of the VTM’s TM pin to the PRM’s VT pin. The VTM TM voltage is equal to the VTM internal sensed temperature in Kelvin divided by 100. For a temperature range of -55 °C to 125 °C the TM voltage will range from 2.18 V to 3.98 V. The Adaptive Loop temperature compensation is pre-programed into the internal microcontroller and is 0.3 %/°C assuming the VT pin is connected to the TM pin of a compatible VTM The TM pin has an internal pull down to SGND, and temperature compensation is disabled for VT voltages less than 1.9V. To disable temperature compensation, leave the VT pin unconnected and open circuit. When disabled, the temperature defaults 25 °C. VAL SGND VCCINT 10K AL Mi c ro Controller RAL

33 - PRM48A x 480 y 400A00 Rev. 1.0 Arrays (Adaptive Loop / Slave operation) In Adaptive Loop operation a master-slave configuration is used for arrays. Up to 5 PRMs of the same type may be placed in parallel to expand the power capacity of the system. One PRM is designated as the master and contains the active control loop which considers control pin inputs and drives SHARE. The other PRMs listen to SHARE and act as slave powertrains only. The following high-level guidelines must be followed in order for the resultant system to start up and operate properly, and to avoid overstress or exceeding any absolute maximum ratings.  One PRM must be designated as a master through configuring the TRIM pin voltage within the recommended range.  All other PRMs must be designated as slave PRMs by tying TRIM pins to SGND. It is recommended to make this connection through a 0Ω jumper for troubleshooting purposes.  All PRMs in the array must be powered from a common power source so that the input voltage to each PRM is the same. The IN pins of all PRMs must be connected together.  An independent fuse for each PRM +IN connection is required to maintain safety certifications (see Fusing section).  An independent inductor for each PRM +IN connection is recommended when used in an array, to control circulating currents among the PRM inputs and reduce the impact of beat frequencies.  Mismatches in both inductance, and resistance from the common power source to each PRM should be minimized.  ENABLE pins must be connected together for start up synchronization and proper fault response of the array.  SHARE pins must be connected together to enable sharing. The bandwidth requirements of SHARE are low enough that the bus can be considered a lumped element, rather than a transmission line, and so star connections to the master PRM with stubs, as well as daisy chain connections are permitted.  The resistances between slave unit SHARE pins and the master’s should be well matched, to avoid introducing additional sharing mismatches. The SHARE bus should not be routed under any PRM. SHARE bus parasitic capacitance to +IN or +OUT should be minimized.  SGND of the master PRM is the reference for all control loop functions. The SGND pins of each slave PRMs should be connected to the SGND reference node on the board through a 1 Ω resistor.  When operating within an array, the master PRM is rated for full power while the slave PRMs are de-rated to the array rated power and current values provided for Slave operation(P OUT_ARRAY,IOUT_ARRAY). The number of PRMs required to achieve a given array capacity must consider these de-ratings to avoid overstressing any PRM in the array.  Adaptive Loop design procedures above will hold for an array, in general, although some parameters must be scaled against the number of PRMs in the system. Arrays of more than 5 PRMs may be possible through use of external circuitry. Please contact Vicor Applications for assistance with array sizing above 5 units.

35 - PRM48A x 480 y 400A00 Rev. 1.0 Figure 36: Remote Sense Example VS PR+IN -IN IF RE SG -OUT +OUTF1 I sense IC Vref C1 R3 Vref ICVref CIN_INT COUT_INT COUT_EXTCIN_EXT RS VAUX CONTROL NODE IFB REF_EN SGND PRM TM Regulator

phase should be greater than 45º where the gain crosses 0dB. than -10dB where the phase crosses 0º. have a slope of -20dB/decade at the crossover frequency. Figure 36. In this example, it is assumed that the maximum

37 - PRM48A x 480 y 400A00 Rev. 1.0 Midband Gain Design: R1,R3 (Remote Sense operation) With reference to Figure 37: curve ABC is the:  minimum output voltage in the application  maximum input voltage expected in the application  maximum load PRM open loop response, and is where the maximum crossover frequency occurs. In order for the maximum crossover frequency to occur at the design choice F CMAX, the compensation gain must be equal and opposite of the powertrain gain at this freque ncy. For stability purposes, the compensation should be in the Mid-band (J-K) at the crossover. Using Equation (8), the mid-band gain can be selected appropriately. Compensation Zero Design :C1 (Remote Sense operation): With reference to Figure 37: curve EFG is the:  maximum output voltage in the application  minimum input voltage expected in the application  minimum load in the application PRM open loop response, and is where the minimum crossover frequency F CMIN occurs. Based on stability criteria, the compensation must be in the mid-band at the minimum crossover frequency, therefore F CMIN will occur where EFG is equal and opposite of GMB. C1 can be selected using Equation (9) so that FZ1 occurs prior to FCMIN. High Frequency Pole Design: C2 (Remote Sense operation): Using Equation (10), C2 should be selected so that F P2 is at least one decade above F CMAX and prior to the gain bandwidth product of the operational amplifier (10MHz for this example). For applications with a higher desired crossover frequency the use of a high gain bandwidth product amplifier may be necessary to ensure that the real pole can be set at least one decade above the maximum crossover frequency. Figure 37 – Reference asymptotic Bode plot for the considered system Open Loop Gain vs. Frequency -40 -20 Frequency, Log scale (y-intercept is application specific) Gain (dB) PRM Open Loop Max Load A B E F I J K L Compensation Gain Application's op-amp G·BW C G FCMAX FCMIN PRM Open Loop Min Load

38 - PRM48A x 480 y 400A00 Rev. 1.0 Arrays (Remote Sense operation) In Remote Sense operation up to 10 PRMs of the same type may be placed in parallel to expand the power capacity of the system. All PRMs within the array are configured for Remote Sense operation and are driven by an external control circuit which considers the control inputs and drives the CONTROL NODE bus. The following high-level guidelines must be followed in order for the resultant system to start up and operate properly, and to avoid overstress or exceeding any absolute maximum ratings.  All PRMs must be configured for Remote Sense operation by tying TRIM pins to SGND. It is recommended to make this connection through a 0Ω jumper for troubleshooting purposes.  All PRMs in the array must be powered from a common power source so that the input voltage to each PRM is the same.  An independent fuse for each PRM +IN connection is required to maintain safety certifications (see Fusing section).  An independent inductor for each PRM +IN connection is recommended when used in an array, to control circulating currents among the PRM inputs and reduce the impact of beat frequencies.  Mismatches in both inductance, and resistance from the common power source to each PRM should be minimized.  ENABLE pins must be connected together for start up synchronization and proper fault response of the array.  Reference supply to the control loop voltage reference and current sense circuitry must be enabled when all modules’ REF_EN pins have reached their operational voltage levels.  A single external control circuit must be implemented as described in the Remote Sense operation design guidelines. The control circuit should drive the CONTROL NODE bus.  CONTROL NODE pins must be connected together to enable sharing. The bandwidth requirements of CONTROL NODE are low enough that the bus can be considered a lumped element, rather than a transmission line, and so star connections as well as daisy chain connections are permitted.  Each PRM must have its own local current shunt and current sense circuitry to drive its IFB pin.  The resistances between CONTROL NODE pins should be well matched, to avoid introducing additional sharing mismatches. The CONTROL NODE bus should not be routed under any PRM. Parasitic capacitance to +IN or +OUT should be minimized.  One PRM should be designated to provide the SGND reference, VAUX, and REF_EN voltages for the external circuitry.  The SGND pins of all other PRMs should be connected to the SGND reference node on the board through a 1 Ω resistor.  When operating within an array, the PRMs are de- rated to the array rated power and current values provided for Remote Sense operation (P OUT_ARRAY, IOUT_ARRAY). The number of PRMs required to achieve a given array capacity must consider these de-ratings to avoid overstressing any PRM in the array.  When using VAUX to power external circuitry, total current draw including CONTROL NODE sink currents must be taken into account to ensure the maximum VAUX current is not exceeded. Arrays of more than 5 PRMs may require additional circuitry to provide the required source current. Contact Vicor Applications Engineering for more information.

40 - PRM48A x 480 y 400A00 Rev. 1.0 Note that during the bursts of switching, the powertrain frequency is constant, but the number of pulses as well as the time between bursts is variabl e. The variability depends on many factors including input voltage, output voltages, load impedance, and error amplifier output impedance. In burst mode, the gain of the SHARE/CONTROL NODE input to the plant which is modeled in the previous sections is time varying. Therefore the small si gnal analysis cannot be directly applied to burst mode operation. Input and Output filter design Figures 14 and 15 provide the total input and output charge per cycle, as well as switching frequency, of the PRM at full load under various input and output voltages conditions. Figure 13 provides the effectiv e internal capacitance of the module. A conservative estima te of input and output peak- peak voltage ripple at nominal line and trim is provided by equation (12): EXTINT SW FL TOT CC f IQ V  4.0 (12) QTOT is the total input (Fig. 14) or output (Fig. 15) charge per switching cycle at full load, while C INT is the module internal effective capacitance at the considered voltage (Fig. 13) and C EXT is the external effective c apacitance at the considered voltage. Input filter stability The PRM can provide very high dynamic transients. It is therefore very important to ve rify that the voltage supply source as well as the interconnecting line are stable and do not oscillate. For this purpose, the converter dynamic input impedance magnitude INEQr _ is provided in Figures 21, 22, 23. It is recommended to provide adequate design margin with respect to the stability condition s illustrated in the previous sections. Inductive source and local, external input decoupling capacitance with negligible ESR (i.e.: ceramic type) The voltage source impedance can be modeled as a series R LINE LLINE circuit. The high performance ceramic decoupling capacitors will not significantly damp the network because of their low ESR; therefore in order to guarantee stability the following conditions must be verified: INEQEXTININTIN line line rCC LR  (13) INEQline rR _ (14) It is critical that the line source impedance be at least an octave lower than the converter’s dynamic input resistance (14). However, R LINE cannot be made arbitrarily low otherwise equation (13) is violated and the system will show instability, due to under-damped RLC input network. Inductive source and local, external input decoupling capacitance with significant R CIN_EXT ESR (i.e.: electrolytic type) In order to simplify the analysis in this case, the voltage source impedance can be modeled as a simple inductor L LINE. Notice that, the high performance ceramic capacitors CIN_INT within the PRM should be included in the external electrolytic capacitance value for this purpose. The stability criteria will be EXTINCINEQ Rr __  (15) INEQ CEXTIN line rRC L EXTIN _ _ (16) Equation (16) shows t hat if the aggregate ESR is too small – for example by using very high quality input capacitors (CIN_EXT) – the system will be under-damped and may even become destabilized. Again, an oc tave of design margin in satisfying (15) should be considered the minimum. Layout Considerations Application Note AN:005 details board layout recommendations using V•I Chip components, with details on good power connections, reducing EMI, and shielding of control signals and techniques to reference them to SGND. Avoid routing control signals (EN ABLE, TRIM, AL etc.) directly underneath the PRM. It is critical that all control signals (aside from VC and VT) are referenced to SGND, both for routing and for pull-down and bypassing purposes. VC and VT provide control and feedback from a VTM, and must be referenced to – OUT of the PRM (-IN of the VTM) SGND is connected to –IN internally to the PRM. SGND should not be tied to any other ground in the system.

41 - PRM48A x 480 y 400A00 Rev. 1.0 Input Fuse Recommendations A fuse should be incorporated at the input to each PRM, in series with the +IN pin. A 15A or smaller input fuse (Littlefuse NANO2® 451/453 series) is required to safety agency conditions of acceptability. Al ways ascertain and observe the safety, regulatory, or other agency specifications that apply to your specific application. Thermal Considerations V•Ichip TM products are multi-chip modules whose temperature distribution varies greatly for ea ch part number as well as with the input / output conditions, thermal management and environmental conditions. Maintaining the top of the PRM48A[x]480[y]400A00 case to less than 100ºC will keep all junctions within the V•I Chip module below 125ºC for most applications. The percent of total heat dissipated through the top surface versus through the J-lead is entirely dependent on the particular mechanical and thermal environment. The heat dissipated through the top surface is typically 60%. The heat dissipated through the J-lead onto the PCB board surface is typically 40%. Use 100% top surface dissipation when designing for a conservative cooling solution. It is not recommended to use a V•I Chip module for an extended period of time at full load without proper heat sinking.

42 - PRM48A x 480 y 400A00 Rev. 1.0 PRODUCT OUTLINE DRAWING AND REOMMENDED LAND PATTERN – SMD(F)

43 - PRM48A x 480 y 400A00 Rev. 1.0 PRODUCT OUTLINE DRAWING AND REOMMENDED LAND PATTERN – THROUGH HOLE(T)

44 - PRM48A x 480 y 400A00 Rev. 1.0

REVISION HISTORY

Revision Date Description Page Number(s) 1.0 11/12/12 Final approved datas heet for initial release. n/a

45 - PRM48A x 480 y 400A00 Rev. 1.0 Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems. Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make changes to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls are used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. Specifications are subject to change without notice. Vicor’s Standard Terms and Conditions All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request. Product Warranty In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the “Express Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment and is not transferable. UNLESS OTHERWISE EXPRESSLY STATED IN A WRITTEN SALES AGREEMENT SIGNED BY A DULY AUTHORIZED VICOR SIGNATORY, VICOR DISCLAIMS ALL REPRESENTATIONS, LIABILITIES, AND WARRANTIES OF ANY KIND (WHETHER ARISING BY IMPLICATION OR BY OPERATION OF LAW) WITH RESPECT TO THE PRODUCTS, INCLUDING, WITHOUT LIMITATION, ANY WARRANTIES OR REPRESENTATIONS AS TO MERCHANTABILITY, FITNESS FOR PARTICULAR PURPOSE, INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT, OR ANY OTHER MATTER. This warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. Vicor shall not be liable for collateral or consequential damage. Vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes no liability for applications assistance or buyer product design. Buyers are responsible for their products and applications using Vicor products and components. Prior to using or distributing any products that include Vicor components, buyers should provide adequate design, testing and operating safeguards. Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Life Support Policy VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used herein, life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Per Vicor Terms and Conditions of Sale, the user of Vicor products and components in life support applications assumes all risks of such use and indemnifies Vicor against all liability and damages. Intellectual Property Notice Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Interested parties should contact Vicor's Intellectual Property Department. The products described on this data sheet are protected by the following U.S. Patents Numbers: 7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for use under 6,975,098 and 6,984,965. Vicor Corporation

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Product Information

PRM48AF480M400A00 specifications and overview.

Summary

PRM??Regulator

Description

PRM??Regulator

Source title PRM48AF480M400A00 Datasheet(PDF) - Vicor Corporation

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