405EX AMCC | Alldatasheet
Document overview
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Technical content
Features
- AMCC PowerPC ® 405 32-bit RISC processor core operating from 333MHz to 667MHz including 16KB I- and D-caches with parity checking
- On-chip 128-bit processor local bus (PLB) operating up to 200MHz
- On-chip 32-bit peripheral bus (OPB) operating up to 100 MHz
- External 8-,16-, or 32-bit peripheral bus (EBC) operating up to 100MHz
- External bus master (EBM) operating up to 100MHz
- On-chip Security feature with True Random Number generation
- Eight- and 16-bit NAND Flash interface
- Inter-chip connectivity (SCP and IIC)
- Boot from NOR Flash on the external peripheral bus or NAND Flash on the NAND Flash interface
- DMA (4-channel) support for all on-chip slaves and external bus, UARTs, and devices on the EBC
- DDR1/2 SDRAM interface operating up to 400 Mbps
- Two one-lane PCI Express interfaces operating up to 2.5 Gbps
- Two Gigabit Ethernet interfaces (half- and full- duplex) to external PHY (GMII/RGMII)
- USB 2.0 OTG port configurable as either Host or Device
- Programmable universal interrupt controller (UIC)
- General Purpose Timer (GPT)
- Up to two serial ports (16750 compatible UART)
- Two IIC interfaces operating up to 400kHz and supporting all standard IIC EEPROMs
- One SCP (SPI) synchronous full-duplex channel operating up to 25 MHz
- General purpose I/Os (GPIOs), each with programmable interrupts and outputs
- Supports JTAG for board-level testing
- System power mana gement, low power dissipation and small form factor
- Available in a RoHS comp liant (lead-free) package
Description
With speeds up to 667MHz, a flexible off-chip memory architecture, and a diverse communications package that includes PCI Express, USB 2.0 OTG, and 10/100/1000 Ethernet, the PowerPC 405EX embedded processor provides a low power and small footprint system-on-a-chip (SOC) solution for a wide range of high performance, cost-constrained embedded applications. This includes wireless LAN applications, security appliances, internet appliances, line cards, and intelligent USB peripherals. It is an easily programmable general purpose, 32-bit RISC controller that offers an upgrade path for applications in need of performance and connectivity improvements. Technology: Cu-08 CMOS, 90nm Package: 388-ball, 27mm × 27mm, enhanced plastic ball grid array (EPBGA), 1mm ball pitch Power consumption (est.): less than 2W, typical Voltages required: 3.3V, 2.5V, 1.8V (DDR2 SDRAM only), and 1.2V
PPC405EX – PowerPC 405EX Embedded Processor
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Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table of Contents
PPC405EX – PowerPC 405EX Embedded Processor
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Revision 1.09 - August 21, 2007 Preliminary Data Sheet Ordering, PVR, and JTAG Information This section provides the part number nomenclature. For availability, contact your local AMCC sales office. The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. See the PPC405EX Embedded Processor User’s Manual for details about accessing these registers. Order Part Number Key Product Name Order Part Number (see Notes:) Package Rev Level PVR Value JTAG ID PPC405EX PPC405EX-SpAfffTx 27mm, 388-ball, EPBGA A 0x12911477 0x1405B1E1 PPC405EX PPC405EX-NpAfffTx 27mm, 388-ball, EPBGA A 0x12911475 0x1405B1E1 Notes: 1. S = security feature present, N = security feature not present 2. p = Package: S = lead-free (RoHS compliant), P = leaded 3. A = Chip revision level A 4. fff = Processor frequency 333 = 333MHz 400 = 400MHz 533 = 533MHz 666 = 667MHz 5. T = Case temperature range, -40 °C to +85°C 6. x = Shipping package type Z = tape-and-reel blank = tray AMCC Part Number PPC405EX-SSA667TZ Chip Package Processor Speed (MHz)Security Case Temperature Range Shipping Package Revision Level Note: The example P/N above has the security featur e, is lead-free, capable of running at 667MHz, and is shipped in tape-and-reel packaging.
Figure 1. PPC405EX Embedded Controller Functional Block Diagram provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
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the use of mtdcr and mfdcr instructions. Table 1. System Memory Address Map (4GB System Memory)
- If peripheral bus boot is selected, peripheral bank 0 is au tomatically configured at reset to the address range listed above.
- After the boot process, software may reas sign the boot memory regions for other uses.
- PCI Express can use PLB address range 1 0000 0000 to FFFF FF FF FFFF FFFF even though the CPU can not access it.
Table 2. DCR Address Map
- A DCR address is 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or one kiloword
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Revision 1.09 - August 21, 2007 Preliminary Data Sheet Power PC 405 Processor The PPC405 processor is a fixed-point, 32-bit RISC unit. Features include:
- Five-stage pipeline with single-cycle execution of most instructions, including loads and stores
- Separate, configurable 16 KB D- and I-caches, both two-way set associative
- Thirty-two 32-bit general purpose registers (GPRs)
- Unaligned load/store support
- Hardware multiply/divide
- Parity detection and reporting for the instruction cache, data cache, and translation look-aside buffer (TLB)
- Double word instruction fetch from cache
- Translation of the four GB logical address space into physical addresses
- Built-in timer and debug support
- Power management
- DCR interface is 32 bits wide
- Selectable processor vs. bus clock ratios (N:1 ratio only, where N =1, 2, 3,or 4 ) Internal Buses The PPC405EX contains four internal buses: the processor local bus (PLB), the Advanced High-Performance Bus (AHB), the on-chip peripheral bus (OPB), and the device control register (DCR) bus. High performance devices such as the processor, the DDR SDRAM memory controller, PCI Express, the Ethernet MAL, and DMA utilize the PLB. Lower bandwidth I/O interfaces such as communications and timer interfaces utilize the OPB. The daisy- chained DCR bus provides a lower bandwidth path for passing status and control information between the processor and the other on-chip peripheral functions. PLB The Processor Local Bus (PLB) is a high-performance on-chip bus used to connect PLB-equipped master and slave devices to the PPC405 CPU. It provides a 128-bit data path with 64-bit addressing and operates up to 200MHz. There are bridges between the PLB and the OPB. Features include:
- Separate and simultaneous 6.4GB/s read and write data paths
- Decoupled address and data buses
- Address pipelining
- Late master request abort capability
- Hidden (overlapped) bus request/grant protocol
- Bus arbitration-locking mechanism
- Byte-enable capabilit y allows for unaligned half word transfers and 3-B transfers
- Support for 32- and 64-B burst transfers
- Read word address capability
- Sequential burst protocol
- Guarded and unguarded memory transfers
- Simultaneous control, address, and data phases
- DMA buffered, flyby, peripheral-to-memory, memory-to-peripheral, and DMA memory-to-memory operations AHB The Advanced High-Performance Bus (AHB) is dedicated to the USB OTG 2.0. Features include:
- 32-bit data path
- 32-bit address
- Synchronous to the PLB
- From 60MHz to 100MHz.
PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 AMCC Proprietary 9 Preliminary Data Sheet OPB The OPB provides 32-bit address and data interfaces, and operates up to 100MHz. There are bridges between the OPB and the PLB. Features include:
- Pipelined read support
- Dynamic bus sizing
- Single-cycle data transfer between masters and slaves DCR Bus The daisy-chained DCR bus provides a path for passing status and control information between the processor core and the other on-chip cores. All DCRs are 32 bits in width with 10-bit addressing. External Bus Controller The external bus controller (EBC and EBM ) transfers data between the PLB and external memory or peripheral devices attached to the external peripheral bus. The EBC provides direct attachment of memory devices such as ROM and SRAM, DMA device paced memory devices, and DMA peripheral devices. Features include:
- From 60MHz to 100 MHz speed
- Data bus is 8, 16, or 32 bits with a 27-bit address bus
- Up to four chip selects
- Arbitration and multi-master supported
- Flash ROM interface
- Boot from EBC (including NAND Flash interface) support
- Direct support for 8-,16-, or 32-bit SRAM and external peripherals
- External bus master support NAND Flash Controller The NAND Flash controller (NDFC) provides a simple interface between the External Bus Controller (EBC) and a variety of NAND Flash-based storage devices. Features include:
- Attachment as internal EBC slave device
- Eight- and 16-bit NAND Flash interface
- Up to four banks of NAND Flash supported
- Device sizes of 4MB to 256MB (32Mb to 2Gb) supported
- 512B + 16B or 2kB + 64B device page sizes supported
- ECC generation - hamming code, single-bit correction, double-bit detection (SEC/DED)
- Eight-bit command write, address write, and data read/write
- Interrupt on device ready (after long page write or block erase operations)
- Boot from NAND – Executes up to 4KB of boot code out of first block – Automatic page read accesses performed based on device configuration and read address DMA Controller The Direct Memory Access (DMA) controller is a Processor Local Bus (PLB) master that enables faster data transfer between memory and peripherals than is possible under program control. The 4-channel DMA controller handles data transfers between memory and peripherals and from memory-to-memory. Each channel has an independent set of registers needed for data transfer: a control register, a source address register, a destination address register, and a transfer count register.
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Revision 1.09 - August 21, 2007 Preliminary Data Sheet Features include:
- Memory-to-memory transfers
- Buffered memory-to-peripheral transfers
- Buffered peripheral-to-memory transfers
- Four independent DMA channels
- Scatter/gather capability for dynamically programming multiple DMA transfers
- Programmable address increment or decrement
- Internal data buffering
- Can transfer data to/from any PLB slave, including the external bus USB 2.0 OTG Interface One USB 2.0 On-the-Go (OTG) controller that can be configured as either a Host or Device port. Features include:
- Low- (Host only), Full- and High-Speed support
- Internal DMA to optimize performance and offload the CPU
- Up to two IN/OUT Endpoints in Device mode (one can be isochronous)
- Supports maximum packet size of 1024B (isochronous) and 512B (bulk)
- Support for isochronous traffic
- Three packets per microframe (24MB/s throughput)
- Eight KB buffer
- ULPI SDR interface DDR1/2 SDRAM Controller The Double Data Rate 1/2 (DDR1/2) SDRAM memory controller supports industry standard discrete devices that are compatible with both the DDR1 or DDR2 specifications. The correct I/O supply voltage must be provided for the two types of DDR devices: DDR1 devices require +2.5V and DDR2 devices require +1.8V. Global memory timings, address and bank sizes, and memory addressing modes are programmable. Features include:
- 16- or 32-bit memory interface
- Optional 8-bit error checking and correcting (ECC)
- 1.6-GB/s peak data rate
- Two memory banks of up to 1 GB each
- Maximum capacity of 2GB
- Support for one memory bank of 2GB with CAS latencies of 2, 2.5, or 3
- Clock frequencies from 133MHz (266Mbps) to 200MHz (400Mbps) supported (Faster parts may be used, but must be clocked no faster than 200MHz)
- Page mode accesses (up to 16 open pages) with configurable paging policy
- Programmable address mapping and timing
- Software initia ted self-refresh
- Power management (self-refresh, suspend)
- Two regions (two chip se lects, one clock driver) PCI Express The PCI Express single-lane interfaces include the following features: Features include:
- Compliant with PCI Express base specification 1.1
- Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream) – Applications compliant with MSI rules are limited to one End Point port per PPC405EX
PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 AMCC Proprietary 11 Preliminary Data Sheet
- PCI-Express to PCI-Express opaque (Non-Transparent) bridge
- Power Management
- Supports one virtual channel (VC0) with no Traffic Class (TC) filtering
- Maximum Payload block size 256B
- Supports up to 512B maximum Read request size
- Requests supported: – Up to two posted outbound Write requests (memory and messages) – Up to two posted inbound Write requests – Up to two outbound Read requests outstanding on PCI Express – Up to two inbound Read requests outstanding on PCI Express – Outbound I/O request as a PCI Express Root Port – Inbound I/O request as a PCI Express End Point
- Buffering in each PCI Express Port for the following transaction types: – 1KB Replay buffer: up to eight in flight transactions – 512B for Outbound posted Writes – 512B for Outbound Reads completion – 512B for Inbound posted Writes – 512B for Inbound Reads completion
- Parity checking on each buffer
- POM Programmable Outbound Memory Regions: 3 Memory , 1 I/O, 1 Message, 1 config, 1 Internal Regs
- PIM Programmable Inbound Memory Region s: 4 Memory, 1 I/O, 1 Expansion ROM
- INTx Interrupts support (PCI legacy): – Up to four INTx Termination for Root Port s. A/B/C/D interrupts are wired to the UIC – A/B/C/D INTx types Generation for Endpoints
- MSI - Message Signaled Interrupts – MSI Generation for End Point – MSI Termination for Root Ports – MSI_X Termination for Root Ports Security Function The built-in security function is a cryptographic engine attached to the 128-bit PLB with built-in DMA and interrupt controllers. Features include:
- Federal Information Processing Standard (FIPS) 140-2 design
- Support for an unlimited number of Security Associations (SA)
- Different SA formats for each supported protocol (IPsec, SSL/TLS/DTLS, MACSec, SGT L2/L3 and sRTP)
- Internet Protocol Security (IPSec) features – Full packet tran sforms (ESP & AH) – Complete header and trailer processing (IPv4 and IPv6) – Multi-mode automatic padding – "Mutable bit" handler for AH, including IPv4 option and IPv6 extension headers
- Secure Socket Layer (SSL), Transport Layer Security (TLS), and Datagram Transport Layer Security (DTLS) – Packet transforms – One-pass hash-then-encrypt or decrypt-then-hash for SSL, TLS and DTLS packet transforms using ARC4 Stream Cipher
- Secure Real-Time Protocol (sRTP) features – Packet transforms – ROC removal and TAG insertion – Variable bypass offset of header length per packet
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Revision 1.09 - August 21, 2007 Preliminary Data Sheet
- Media Access Control Security (MACSec) features – Cipher suit e GCM-AES-128 – Header insertion and removal – Integrity and confidentiality with MSDU
- SGT L2 supported features: – GCM-AES with 128-bit key. – Integrity only and with confidentiality of MSDU
- ICV generation and validation SGT L3 supported features – AES-GCM, AES-GMAC with 12 8, 192 and 256 bit key.
- IPsec/SSL security acceleration engine
- DES, 3DES, AES, ARC-4, AES-GCM, an d GMAC-AES encryption/decryption
- MD-5, SHA-1, and SHA-256 hashing
- Public key acceleration for RSA, DSA and Diffie-Hellman
- Combined encryption-hash and hash-decryption with the AES-CCM algorithm.
- True or pseudo random number generators – Non-deterministic true random numbers – Pseudo random numbers with lengths of 8B or 16B – ANSI X9.17 Annex C compliant using a DES algorithm
- Interrupt controller – Fifteen programmable, maskable interrupts – Initiate commands via an input interrupt – Sixteen programmable interrupts indicating completion of certain operations – All interrupts mapped to one level- or edge-sensitive programmable interrupt output
- DMA controller – Autonomous, 4-channel – 1024-words (32 bits/word) per DMA transfer – Scatter/gather capability wit h byte aligned addressing – Byte reverse capability on SA and descriptors UART The Universal Asynchronous Receiver/Transmitter (UART) interface provides four configurations:
- One 8-signal port
- Two 4-signal ports.
- Two 2-signal ports
- One 4-signal port and one 2-signal port The UART performs serial-to-parallel conversion on data received from a peripheral device or a modem, and parallel-to-serial conversion on data received from the processor. Features include:
- Compatible with the16750
- All six software modem control functions (CTS, RTS, DSR, DTR, RI, DCD) on UART0
- Programmable auto flow (data flow controlled by RTS and CTS signals)
- Characters can be 5, 6, 7, or 8 bits
- Programmable start, stop, parity bit insertion
- Sixty-four byte FIFOs for buffering Tx and Rx data
- LIN sub-bus specification compliant - line break generation/detection and false start bit detection
- Programmable internal/ext ernal loopback capabilities
- Low Power and Sleep mode
- Register conformance (after reset) to configuration of the NS16450 register set
- Hold and shift registers (eliminate need for precise synchronization between processor and serial data in character mode)
- Complete status reporting
- Full prioritized inte rrupt system controls
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- Independently controlled transmit, receiv e, line status, and data set interrupts
- Programmable baud generator (divides seri al clock input and generates 16x clock)
- Ability to add/delete standard asynchronous communication bits such as start, stop, and parity to/from serial data
- Even, odd, or no-parity bit generation and detection
- Stop bit generation of 1, 1.5, or 2 bits
- Variable baud rate
- Internal diagnostic capability
- Loopback controls for isolating communications link faults
- Break, parity, overrun, framing error simulation
- OPB interface with optional DMA support IIC Bus Interface The Inter-Integrated Circuit (IIC) interface provides a Philips I2C® compatible interface operating up to 400kHz either as a master, a slave, or both with a bootstrap controller (BSC) included. During chip reset, the bootstrap controller can read configuration data from an IIC compatible memory device (e.g., EEPROM). This data can be used to replace the default configuration settings provided by the chip. Features include:
- Two IIC channels
- Compliant with Philips Semiconductors I2C Specification, dated 1995
- Operation at 100kHz or 400kHz
- Byte (8-bit) data
- Addresses are 10 or 7 bits
- Slave Transmit and Receive
- Master Transmit and Receive
- Multiple bus masters supported
- Programmable as master, slave, or master/slave
- Boot parameters read from IIC attached me mory (Port 0) with IIC bootstrap controller
- OPB slave interface is 32 bits wide Serial Communication Port Interface (SCP/SPI) The Serial Communication Port (SCP) (also known as the Serial Peripheral Interface or SPI) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on the serial port supporting a three-wire interface (receive, transmit, and clock), and is a slave on the OPB. Features include:
- One SCP channel, full duplex synchronous
- S C P m a s t e r
- Up to 25MHz
- Programmable internal loopback capabilities
- Multi-master protocol supported
- Independent masking of all in terrupts (master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, receive FIFO overflow)
- Dynamic control of serial bit rate of data transfer (serial-master mode only)
- Data Item size for each data transfer under programmer control (4-to-16 bits)
- OPB slave interface is 32 bits wide
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Revision 1.09 - August 21, 2007 Preliminary Data Sheet General Purpose I/O (GPIO) Controller The GPIO controller enables multiplexing of module I/O pins with multiple functions within the chip. That is, a single package pin can be assigned to multiple I/O functions. Which function the pin is assigned to is determined by register bit settings controlled by software. This significantly reduces the number of package pins needed to support multiple I/O groups. Features include:
- Up to 32 GPIOs available – GPIOs are multiplexed with alternate functions – If not in use for dedicated functions, I/Os are available as GPIOs
- Direct control of all functions from registers programmed by means of OPB bus master accesses
- Time multiplexing of controller outputs to module outputs
- Programmable conversion of module outputs to open-dr ain outputs (enables sharing of active low outputs externally)
- Time multiplexing of module inputs to controller inputs Universal Interrupt Controller (UIC) The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the PPC405 processor. Features include:
- Ten external interrupt sources supported
- Generate interrup t on level (high or low) or edge (rising or falling)
- Programmable as synchronous (edge-capture or level-se nsitive) or asynchronous (edge- or level-sensitive triggering)
- Each interrupt source/bit programmable as critical or non critical
- DCR bus interface is 32 bits wide
- Optional interrupt handler vector generation – Programmable vector base address – Programmable vector offset size – Programmable interrupt priority ordering
- Programmable polarity for all interrupt types
- Interrupts of the same type do not need to be in contiguous bit positions
- Status registers provide: current state of all interrupts, current state of enabled interrupts Gigabit Ethernet The Ethernet support provides two Gigabit (10/100/1000 Mbps) interfaces (GMII/RGMII ). Features include:
- ANSI/IEEE Std. 802.3 and I EEE 802.3u supplement compliant
- Half-duplex and full-duplex supported
- Receive FIFOs are 512 bytes with programmable thresholds
- FCS control for transmit/receive packets
- Multiple packet handling in transmit and receive FIFOs
- Unicast, multicast, broadcast, and promiscuous address filtering
- Two 256-bit hash filters for unicast and multicast frames
- Automatic retransmission of collided frames
- Runt frame rejection
- Programmable inter-frame gap
- IEEE 802.3x compliant for frame-based flow control mechanism, including self-assembled control frame transmitting)
- Wake-on-LAN and Power-over-Internet supported
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- Programmable internal/ext ernal loopback capabilities
- OPB slave (MAC) and PLB master (MAL) interfaces are 32 bits wide
- Extensive error/status vector ge neration for each processed packet
- VLAN tag ID supported (according to IEEE Draft 802.3ac/D1.0 standard)
- Programmable automatic source address in clusion/replacement for transmit packets
- Programmable automatic Pad/FCS stripping for receive packets
- Programmable VLAN Tag inclusion/replacement for transmit packets
- Half- or full-duplex GMII/RGMII
- Jumbo frames support
- Memory Access Layer (M AL) provides DMA capability to Ethernet channel
- Interrupt coalescence support for two transmit and two receive channels General Purpose Timer (GPT) The GPT provides a time base counter and system timers in addition to those defined in the processor. Features include:
- 32-bit time base counter driven by the OPB clock
- Seven 32-bit compare timers JTAG Features include:
- IEEE 1149.1 te st access port
- JTAG Boundary Scan Description Language (BSDL) Refer to http://www.amcc.com/Embedded/Partners for a list of AMCC partners supplying probes for use with the JTAG interface.
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Figure 2. Package 27mm, 388-Ball EPBGA
1.0 Basic
Notes: 1. All dimensions are in mm.
- Package conforms to JEDEC MS-034C
- Package available in leaded or lead-free versions
indicated interface group begin. Table 3. Signals Listed Alphabetically (Sheet 1 of 13)
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Table 3. Signals Listed Alphabetically (Sheet 2 of 13)
Table 3. Signals Listed Alphabetically (Sheet 3 of 13)
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Table 3. Signals Listed Alphabetically (Sheet 4 of 13)
Table 3. Signals Listed Alphabetically (Sheet 5 of 13)
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Table 3. Signals Listed Alphabetically (Sheet 6 of 13)
Table 3. Signals Listed Alphabetically (Sheet 7 of 13)
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Table 3. Signals Listed Alphabetically (Sheet 8 of 13)
Table 3. Signals Listed Alphabetically (Sheet 9 of 13)
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Table 3. Signals Listed Alphabetically (Sheet 10 of 13)
Table 3. Signals Listed Alphabetically (Sheet 11 of 13)
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Table 3. Signals Listed Alphabetically (Sheet 12 of 13)
Table 3. Signals Listed Alphabetically (Sheet 13 of 13)
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Listed Alphabetically” on page 17. The following table lists the signals by ball assignment. Table 4. Signals Listed by Ball Assignment (Sheet 1 of 7)
Table 4. Signals Listed by Ball Assignment (Sheet 2 of 7)
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Table 4. Signals Listed by Ball Assignment (Sheet 3 of 7)
Table 4. Signals Listed by Ball Assignment (Sheet 4 of 7)
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Table 4. Signals Listed by Ball Assignment (Sheet 5 of 7)
Table 4. Signals Listed by Ball Assignment (Sheet 6 of 7)
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Table 4. Signals Listed by Ball Assignment (Sheet 7 of 7)
“Signals Listed Alphabetically” on page 17, for the pin (ball) number to which each signal is assigned. cases, the signal names shown in this table are not accompanied by signal names that might share the same pin. use of these pins for strapping is not considered multiplexing since the strapping function is not programmable. outputs must never be tied together and terminated through a common resistor. Table 5. Pin Groups
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The following table provides a description of the I/O signals on the PPC405EX. Table 6. Signal Functional Description (Sheet 1 of 7)
- Receiver input has hysteresis.
- Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
- Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
- If not used, must pull up.
- If not used, must pull down.
- Strapping input during reset; pull up or pull down as required.
GMII: Transmit clock for GMII 1000Mbps.
and the impedance calibration circuitry. Table 6. Signal Functional Description (Sheet 2 of 7)
- Receiver input has hysteresis.
- Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
- Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
- If not used, must pull up.
- If not used, must pull down.
- Strapping input during reset; pull up or pull down as required.
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on the setting of bits in the GPIO registers. on the setting of bits in the GPIO registers. Table 6. Signal Functional Description (Sheet 3 of 7)
- Receiver input has hysteresis.
- Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
- Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
- If not used, must pull up.
- If not used, must pull down.
- Strapping input during reset; pull up or pull down as required.
Table 6. Signal Functional Description (Sheet 4 of 7)
- Receiver input has hysteresis.
- Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
- Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
- If not used, must pull up.
- If not used, must pull down.
- Strapping input during reset; pull up or pull down as required.
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Read/Busy. If low, indicates that Read/Erase command is in process. Table 6. Signal Functional Description (Sheet 5 of 7)
- Receiver input has hysteresis.
- Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
- Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
- If not used, must pull up.
- If not used, must pull down.
- Strapping input during reset; pull up or pull down as required.
- Two 2-pin (pull up DCD, DSR, CTS and RTS)
PHY, the next byte is available. Table 6. Signal Functional Description (Sheet 6 of 7)
- Receiver input has hysteresis.
- Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
- Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
- If not used, must pull up.
- If not used, must pull down.
- Strapping input during reset; pull up or pull down as required.
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Table 6. Signal Functional Description (Sheet 7 of 7)
- Receiver input has hysteresis.
- Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
- Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
- If not used, must pull up.
- If not used, must pull down.
- Strapping input during reset; pull up or pull down as required.
Table 7. Absolute Maximum Ratings operating at these maximum ratings.
- The analog voltages can be derived from the +1.2V and +2.5V supplies, but must be filtered as shown below before entering
out and connected to the digital ground plane at the filter capacitor. Keep all wire lengths as short as possible.
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Table 8. Package Thermal Specifications
- For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:
a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. b. TA = TC – PxθCA, where TA is ambient temperature and P is power consumption. c. TCMax = TJMax – PxθJC, where TJMax is maximum junction temperature and P is power consumption.
Table 9. Recommended DC Operating Conditions (Sheet 1 of 2) conditions can affect device reliability.
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- LPDL is least positive down level; MPUL is most positive up level.
Table 10. I/O Input Capacitance Table 9. Recommended DC Operating Conditions (Sheet 2 of 2) conditions can affect device reliability.
Table 11. Typical DC Power Supply Requirements with DDR1 SDRAM
- Values are estimates and subject to change.
- DDR1 running at 333MHz., PLB running at 166MHz.
- DDR1 running at 400MHz., PLB running at 200MHz.
- DDR1 running at 355MHz., PLB running at 177MHz.
- DDR1 running at 333MHz., PLB running at 166MHz.
Table 12. Typical DC Power Supply Requirements with DDR2 SDRAM
- Values are estimates and subject to change.
- DDR2 running at 333MHz., PLB running at 166MHz.
- DDR2 running at 400MHz., PLB running at 200MHz.
- DDR2 running at 355MHz., PLB running at 177MHz.
- DDR2 running at 333MHz., PLB running at 166MHz.
Table 13. DC Power Supply Loads with DDR1 SDRAM
- Typical and Maximum values ar e estimates and subject to change.
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load shown in the figure to the right. Table 14. DC Power Supply Loads with DDR2 SDRAM
- Typical and Maximum values ar e estimates and subject to change.
Table 15. System Clocking Specifications
Figure 3. Clocking Waveform
PPC405EX – PowerPC 405EX Embedded Processor
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Revision 1.09 - August 21, 2007 Preliminary Data Sheet Spread Spectrum Clocking Care must be taken if using a spread spectrum clock generator (SSCG) with the PPC405EX. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is called tracking skew. The PLL bandwidth and phase angle determine how much tracking skew exists between the SSCG and the PLL for a given frequency deviation and modulation frequency. If using an SSCG with the PPC405EX the following conditions must be met:
- The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC405EX with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency.
- The maximum frequency de viation must not exceed −3%, and the modulation frequency must not exceed 40kHz. In some cases, on-board PPC405EX peripherals impose more stringent requirements (see Note 1).
- Use the peripheral bus clock for logic that is synchron ous to the peripheral bus because this clock tracks the modulation. Notes: 1. The serial port baud rates are synchronous to the mo dulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur, assuming that the connected device is running at precise baud rates. If an external serial clock is used, baud rate is unaffected by the modulation. 2. Ethernet operation is unaffected. 3. IIC operation is unaffected. Caution: The system designer must ensure that any SSCG used with the PPC405EX meets these requirements and does not adversely affect other aspects of the system.
Table 16. Peripheral Interface I/O Clock Timings maximum OPB clock frequency is 100MHz.
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Figure 4. Input Setup and Hold Timing Waveform Figure 5. Output Delay and Float Timing Waveform
Table 17. I/O Specifications—All CPU Speeds (Sheet 1 of 2)
- Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
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Table 17. I/O Specifications—All CPU Speeds (Sheet 2 of 2)
- Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
Table 18. I/O Specifications—333 MHz to 667 MHz CPU
- PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
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same frequency as the PLB clock signal and is in phase with the PLB clock signal. SDRAM Controller chapter in the PPC405EX Embedded Processor User’s Manual). The signals are terminated as indicated in Figure 6 for the DDR timing data in the following sections. Figure 6. DDR SDRAM Simulation Signal Termination Model Extended Mode Register (EMR) in order to optimize the data transmission during memory write operations. Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data. factors, including the type of memory used and the board layout.
obtained using a simulation that assumes a model as shown in Figure 6. Table 19. DDR SDRAM Output Driver Specifications Table 20. DDR SDRAM Write Operation Conditions
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The following diagram illustrates the relationship among the signals involved with a DDR write operation. Figure 7. DDR SDRAM Write Cycle Timing Note: The timing data in the following tables is based on simulation runs using Einstimer. Table 21. I/O Timing—DDR SDRAM T DS
- All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle.
signal. The Data must be centered to these edges for correct operation. The PPC405EX can delay with very fine granularity the DQS through register programming. path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency. The data is stored in the eight Flip Flops of the Stage 1, such that it can be transferred later within a 8x period. Table 22. I/O Timing—DDR SDRAM T Table 23. I/O Timing—DDR SDRAM Write TimingT SD and THD
- TSD and THD are measured under worst case conditions.
- Clock speed for the values in the table is 200MHz.
- The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns).
- To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.5 ns from the values in the table and add 1/4
of the cycle time for the lower clock frequency (for example, TSD − 1.25 + 0.25TCYC).
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Figure 8. DDR SDRAM Read Data Path The following diagram illustrates the relationship of the signals involved with a DDR read operation. Figure 9. DDR SDRAM Memory Data and DQS
routing. It is recommended that the signal length for all of the DQS signals be matched. Table 24. I/O Timing—DDR SDRAM Read Timing T SD and THD
- TSD and THD are measured under worst case conditions.
- Clock speed for the values in the table is 200MHz.
- The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns).
- To obtain adjusted TSD and THD values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4
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Figure 10. DDR SDRAM Read Cycle Timing—Example
The following describes the method by which initial chip settings are established when a system reset occurs. strapping options. The signal names assigned to the pins for normal operation appear below the pin number. Table 25. Strapping Pin Assignments Note: See the PPC405EX Embedded Processor User’s Manual for option descriptions and other details regarding the boot process.
PPC405EX – PowerPC 405EX Embedded Processor
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Revision 1.09 - August 21, 2007 Preliminary Data Sheet Revision Log Date Version Contents of Modification 02/27/2007 1.00 Initial creation of document. 03/01/2007 1.01 Updates following review of initial document. 03/22/2007 1.02 Change package drawing to eliminate confusion. Expand system memory map. Define FSource0 signal as Reserved. Add Recommended Operating Conditions data. Add thermal data. Misc. updates and additions. 04/24/2007 1.03 Misc. updates and additions including some limited timing data. 05/24/2007 1.04 Correct one of three ball numbers assigned to PerData28. Swap four balls between V DD and GND. Swap one ball between OVDD and SVDD. Correct typographical errors in Table 3. Add missing alphabetical entries for PerAddr05, NAND Flash, and IIC1. Add output current values to Tables 15 and 16. 06/04/2007 1.05 Input various review comments. Update Table 6 Notes column. Update Block Diagram. Swap SAVDD an EAVDD signal name assignments on package balls. Add two UART configurations. Add DDR SDRAM section extracted from 460EX with changes appropriate for 405EX. Update timing information for all interfaces. Add power values. Update I/O capacitance values. 06/07/2007 1.06 Remove Confidential status. Input various review comments. 06/28/2007 1.07 Input review comments and corrections. Change default signals for GPIO balls to GPIO00–GPIO27 signals. Eliminate confusing terminology in initialization section. 07/12/2007 1.08 Change voltage names so that SDRAM voltage is always SV DD for both DDR1 and DDR2 types. Six voltage pins originally labeled SVDD changed to EOVDD. 08/21/2007 1.09 Update GMCRefClk specific ations (rise time, jitter, etc.)
PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 AMCC Proprietary 67 Preliminary Data Sheet Applied Micro Circuits Corporation
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