PPC405EP AMCC | Alldatasheet

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Technical content

Features

  • AMCC PowerPC ® 405 32-bit RISC processor core operating up to 333MHz with 16KB D- and I-caches
  • PC-133 synchronous DRAM (SDRAM) inter- face - 32-bit interface for non-ECC applications
  • 4KB on-chip memory (OCM)
  • External peripheral bus - Flash ROM/Boot ROM interface - Direct support for 8- or 16-bit SRAM and external peripherals - Up to five devices
  • DMA support for memory and UARTs. - Scatter-gather chaining supported - Four channels
  • PCI Revision 2.2 compliant interface (32-bit, up to 66MHz) - Asynchronous PC I Bus interface - Internal or external PCI Bus Arbiter
  • Two Ethernet 10/100Mbps (full-duplex) ports with media independent interface (MII)
  • Programmable interrupt controller supports seven external and 19 internal edge-triggered or level-sensitive interrupts
  • Programmable timers
  • Software accessible event counters
  • Two serial ports (16750 compatible UART)
  • One IIC interface
  • General purpose I/O (GPIO) available
  • Supports JTAG for board level testing
  • Internal processor local bus (PLB) runs at SDRAM interface frequency
  • Supports PowerPC processor boot from PCI memory

Description

Designed specifically to address embedded applications, the PowerPC 405EP (PPC405EP) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O. Technology: CMOS SA-27E, 0.18 μm (0.11 μm L eff) Package: 31mm, 385-ball, enhanced plastic ball grid array (E-PBGA) Power (typical): 0.72W at 266MHz

PPC405EP – PowerPC 405EP Embedded Processor

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Revision 1.07 – September 10, 2007 Data Sheet Table of Contents

PPC405EP – PowerPC 405EP Embedded Processor Revision 1.07 – September 10, 2007 AMCC 3 Data Sheet List of Figures List of Tables

PPC405EP – PowerPC 405EP Embedded Processor

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Revision 1.07 – September 10, 2007 Data Sheet Ordering, PVR, and JTAG Information This section provides the part number nomenclature. For availability, contact your local AMCC sales office. The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. Refer to the PowerPC 405EP Embedded Processor User’s Manual for details on accessing these registers. Order Part Number Key Product Name Order Part Number1, 2 Processor Frequency Package Rev Level PVR Value JTAG ID PPC405EP PPC405EP-3GB133C 133MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3GB133CZ 133MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3LB133C 133MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3LB133CZ 133MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3GB200C 200MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3GB200CZ 200MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3LB200C 200MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3LB200CZ 200MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3GB266C 266MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3GB266CZ 266MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3LB266C 266MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3LB266CZ 266MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3GB333C 333MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3GB333CZ 333MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3LB333C 333MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 PPC405EP PPC405EP-3LB333CZ 333MHz 31mm, 385 ball E-PBGA B 0x51210950 0x20267049 Notes: 1. Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray. 2. Package type G contains lead; package type L is lead-free. Part Number PPC405EP-3GB333Cx Package Processor Speed (MHz)Grade 3 Reliability Operational Case Temperature Shipping Package Blank = Tray Z = Tape and reel (-40°C to +85°C)Range Revision Level

Figure 1. PPC405EP Embedded Controller Functional Block Diagram way to create complex ASICs using IBM CoreConnectTM Bus Architecture.

66 MHz max (async)

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the use of mtdcr and mfdcr instructions. Table 1. System Memory Address Map (4GB System Memory)

  1. When peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above.
  2. If PCI boot is selected, a PLB-to-PCI mapping is automat ically configured at reset to the address range listed above.
  3. After the boot process, software may reas sign the boot memory regions for other uses.
  4. All address ranges not listed above are reserved.

Table 2. DCR Address Map

  1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit

(word) register, or 1 kiloword (KW) (which equals 4 KB).

PPC405EP – PowerPC 405EP Embedded Processor

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Revision 1.07 – September 10, 2007 Data Sheet On-Chip Memory (OCM) The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the processor core. Features include:

  • Low-latency access to critical instructions and data
  • Performance identical to cache hits without misses
  • Contents change only under program control PLB to PCI Interface The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC processor and local memory. This interface is compliant with version 2.2 of the PCI Specification. Features include:
  • internal pci bus arbiter for up to three external devices at PCI bus speeds up to 66MHz. Internal arbiter use is optional and can be disabled for systems which employ an external arbiter.
  • PCI bus frequency up to 66MHz - Asynchronous operation from 1/8 PLB frequency to 66MHz maximum
  • 32-bit PCI address/data bus
  • Power Management: - PCI Bus Power Management v1.1 compliant
  • Supports 1:1, 2:1, 3:1, 4:1 clock ratios from PLB to PCI
  • Buffering between PLB and PCI: - PCI target 64-byte write post buffer - PCI target 96-byte read prefetch buffer - PLB slave 32-byte write post buffer - PLB slave 64-byte read prefetch buffer
  • Error tracking/status
  • Supports PCI target side configuration
  • Supports processor access to all PCI address spaces: - Single-beat PCI I/O reads and writes - PCI memory single-beat and prefetch-burst reads and single-beat writes - Single-beat PCI configuration reads and writes (type 0 and type 1) - PCI interrupt acknowledge - PCI special cycle
  • Supports PCI target access to all PLB address spaces
  • Supports PowerPC processor boot from PCI memory

PPC405EP – PowerPC 405EP Embedded Processor Revision 1.07 – September 10, 2007 AMCC 9 Data Sheet SDRAM Memory Controller The PPC405EP Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to two physical banks. Up to 256MB per bank are supported, up to a maximum of 51 2MB. Memory timings, address and bank sizes, and memory addressing modes are programmable. Features include:

  • 11x8 to 13x11 addressing for SDRAM (2 banks)
  • 32-bit memory interface support
  • Programmable address compare for each bank of memory
  • Industry standard 168-pin DIMMS ar e supported (some configurations)
  • Up to 133MHz memory supported by the 266MHz processor
  • Up to 111MHz memory supported by the 333MHz processor
  • 4MB to 256MB per bank
  • Programmable address mapping and timing
  • Auto refresh
  • Page mode accesses with up to 4 open pages
  • Power management (self-refresh) External Peripheral Bus Controller (EBC)
  • Supports five banks of ROM, EPROM, SRAM, Flash memory, or slave peripherals
  • Up to 66MHz operation
  • Burst and non-burst devices
  • 8- and 16-bit byte-addressable data bus width support
  • Latch data on Ready, synchronous or asynchronous
  • Programmable 2K clock time-out counter with disable for Ready
  • Programmable access timing per device - 0–255 wait states for non-bursting devices - 0–31 burst wait states for first access and up to 7 wait states for subsequent accesses - Programmable CSon, CSoff relative to address - Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS
  • Programmable address mapping
  • Peripheral Device pacing with external “Ready” DMA Controller
  • Supports memory-to-memory transfers
  • Four channels
  • Scatter/gather capability for prog ramming multiple DMA operations
  • 32-bit addressing
  • Address increment or decrement
  • Internal 32-byte data buffering capability

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Revision 1.07 – September 10, 2007 Data Sheet Serial Interface

  • One 8-pin UART and one 2-pin (Tx and Rx only) UART interface provided
  • Internal serial clock to allows a wide range of baud rates
  • Register compatibility wit h NS16750 register set
  • Complete status reporting capability
  • Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
  • Fully programmable serial-i nterface characteristics
  • Supports DMA using internal DMA engine IIC Bus Interface
  • Compliant with Phillips® Semiconductors I2C Specification, dated 1995
  • Operation at 100kHz or 400kHz
  • 8 - b i t d a t a
  • 10- or 7-bit address
  • Slave transmitter and receiver
  • Master transmitter and receiver
  • Multiple bus masters
  • Supports fixed V DD IIC interface
  • Two independent 4 x 1 byte data buffers
  • Twelve memory-mapped, fully prog rammable configuration registers
  • One programmable interrupt request signal
  • Provides full management of all IIC bus protocol
  • Programmable error recovery General Purpose IO (GPIO) Controller
  • Controller functions and GPIO registers are pr ogrammed and accessed via memory-mapped OPB bus master accesses
  • All GPIOs are pin-shared with other functions. DCRs co ntrol whether a particular pin that has GPIO capabil- ities acts as a GPIO or is used for another purpose.
  • Each GPIO output is separately pr ogrammable to emulate an open-drain driver (i.e., drives to zero, three- stated if output bit is 1) Universal Interrupt Controller (UIC) The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the local PowerPC processor. Features include:
  • Supports seven external and 19 internal interrupts
  • Edge-triggered or level-sensitive
  • Positive or negative active
  • Non-critical or critical interrupt to processor core
  • Programmable critical interrupt priority ordering
  • Programmable critical interrupt ve ctor for faster vector processing

PPC405EP – PowerPC 405EP Embedded Processor Revision 1.07 – September 10, 2007 AMCC 11 Data Sheet 10/100 Mbps Ethernet MAC

  • Two ports capable of handling full/half duplex 100Mbps and 10Mbps operation
  • Uses the medium independent in terface (MII) to the physical layer (PHY not included on chip) JTAG
  • IEEE 1149.1 te st access port
  • IBM RISCWatch debugger support
  • JTAG Boundary Scan Description Language (BSDL)

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Figure 2. 31mm, 385-Ball E-PBGA Package

1.27 TYP

15.5 TYP

2.36 REF

Notes: 1. All dimensions are in mm.

  1. Package available in leaded and lead-free configurations.

the indicated interface group begin. Table 3. Signals Listed Alphabetically (Sheet 1 of 10)

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Table 3. Signals Listed Alphabetically (Sheet 2 of 10)

Table 3. Signals Listed Alphabetically (Sheet 3 of 10)

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Table 3. Signals Listed Alphabetically (Sheet 4 of 10)

Table 3. Signals Listed Alphabetically (Sheet 5 of 10)

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Table 3. Signals Listed Alphabetically (Sheet 6 of 10)

Table 3. Signals Listed Alphabetically (Sheet 7 of 10)

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Table 3. Signals Listed Alphabetically (Sheet 8 of 10)

Table 3. Signals Listed Alphabetically (Sheet 9 of 10)

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Table 3. Signals Listed Alphabetically (Sheet 10 of 10)

Table 4. Signals Listed by Ball Assignment (Sheet 1 of 6)

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Table 4. Signals Listed by Ball Assignment (Sheet 2 of 6)

Table 4. Signals Listed by Ball Assignment (Sheet 3 of 6)

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Table 4. Signals Listed by Ball Assignment (Sheet 4 of 6)

Table 4. Signals Listed by Ball Assignment (Sheet 5 of 6)

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Table 4. Signals Listed by Ball Assignment (Sheet 6 of 6)

Listed Alphabetically” on page 13 for the pin (ball) number to which each signal is assigned. selection than would otherwise be possible. use of these pins for strapping is not considered multiplexing since the strapping function is not programmable. Table 5. Pin Summary

PPC405EP – PowerPC 405EP Embedded Processor

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Revision 1.07 – September 10, 2007 Data Sheet Unused I/Os Strapping of some pins may be necessary when they are unused. Although the PPC405EP requires only the pull- up and pull-down terminations as specified in the “Signal Functional Description” on page 31, good design practice is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral, SDRAM, and PCI buses should be configured and terminated as follows:

  • Peripheral interface—PerAddr03:31, PerData00:15, and a ll of the control signals are driven by default. Pull up PerReady.
  • SDRAM—Program SDRAM0_CFG[EMDULR]=1 and SDRA M0_CFG[DCE]=1. This causes the PPC405EP to actively drive all of the SDRAM address, data, and control signals.
  • PCI—The PCI pull-up requirements given in the Sign al Functional Description apply only when the PCI interface is being used. When the PCI bridge is unused, configure the PCI controller to park on the bus and actively drive PCIAD31:00, PCIC3:0/BE3:0, and the remaining PCI control signals by doing the following: - Strap the PPC405EP to disable the internal PCI arbiter. - Individually pull up PCISErr , PCIPErr, PCITRDY, and PCIStop through 3.3kΩ resistors to +3.3V. - Pull up PCIReq1:2 through a 3.3kΩ resistor to +3.3V. - Pull down PCIReq0 /Gnt through a 1kΩ resistor to GND. External Bus Control Signals All peripheral bus control signals (PerCS0:4, PerR/W, PerWBE0:1, PerOE, PerWE, PerBLast) are set to the high- impedance state when ExtReset = 0. In addition, as detailed in the PowerPC 405EP Embedded Processor User’s Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals between transactions. As a result, a pull-up resistor should be added to those control signals where an undriven state may affect any devices receiving that particular signal. The following table lists all of the I/O signals provided by the PPC405EP. Please refer to “Signals Listed Alphabetically” on page 13 for the pin number to which each signal is assigned.

Table 6. Signal Functional Description (Sheet 1 of 6) Secondary multiplexed signals are shown in brackets.

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
  3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Bus Control Signals” on page 30.

PCI Address/Data Bus. Multiplexed address and data bus. Type 0 configuration transactions. PCI parity. Parity is even across PCIAD00:31 and PCIC3:0/BE3:0. PCIParity is valid one cycle after either an address or data phase. PCIParity on the next PCI bus clock. command encoding and claims the transaction. PCIPErr is used for reporting data parity errors on PCI transactions. which bad parity is detected.

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when external arbiter is used. informs the PHY that an error was detected. Management Data Clock. The MDClk is sourced to the PHY. Table 6. Signal Functional Description (Sheet 2 of 6) Secondary multiplexed signals are shown in brackets.

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
  3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Bus Control Signals” on page 30.
  1. MemData00 is the most significant bit (msb).
  2. MemData31 is the least significant bit (lsb).
  3. MemAddr12 is the most significant bit (msb).
  4. MemAddr00 is the least significant bit (lsb).

PerData00:15 Peripheral data bus. transfer, allowing partial word transactions. To access this function, software must toggle a DCR bit. Table 6. Signal Functional Description (Sheet 3 of 6) Secondary multiplexed signals are shown in brackets.

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
  3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Bus Control Signals” on page 30.

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[PerBLast] Used to indicates the last transfer of a memory access. [UART0_DCD] UART0 Data Carrier Detect. [UART0_DSR] UART0 Data Set Ready. [UART0_DTR] UART0 Data Terminal Ready. [UART0_RI] UART0 Ring Indicator. [UART1_Rx] UART1 Serial Data In. [UART1_Tx] UART1 Serial Data Out. Table 6. Signal Functional Description (Sheet 4 of 6) Secondary multiplexed signals are shown in brackets.

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
  3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Bus Control Signals” on page 30.

(two states; 0 or open circuit). Table 6. Signal Functional Description (Sheet 5 of 6) Secondary multiplexed signals are shown in brackets.

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
  3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Bus Control Signals” on page 30.

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  1. For a chip mounted on a JEDEC 2S2P card without a heat sink.
  2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:

a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. b. TA = TC – P×θCA, where TA is ambient temperature and P is power consumption. Table 7. Absolute Maximum Ratings operating at these maximum ratings. Note: All specified voltages are with respect to GND. Table 8. Package Thermal Specifications Table 6. Signal Functional Description (Sheet 6 of 6) Secondary multiplexed signals are shown in brackets.

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
  3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Bus Control Signals” on page 30.

c. TCMax = TJMax – P×θJC, where TJMax is maximum junction temperature and P is power consumption. Table 9. Recommended DC Operating Conditions (Sheet 1 of 2) conditions can affect device reliability.

  1. PCI drivers meet PCI specifications.
  2. See “5V-Tolerant Input Current” on page 38.

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Figure 3. 5V-Tolerant Input Current Table 10. Input Capacitance Table 9. Recommended DC Operating Conditions (Sheet 2 of 2) conditions can affect device reliability.

  1. PCI drivers meet PCI specifications.
  2. See “5V-Tolerant Input Current” on page 38.

Table 11. DC Electrical Characteristics

  1. The maximum current and power values listed above are not guaranteed to be the highest obtainable. These values are

applications under the Linux operating system. SDRAM while the internal DMA controller further increases SDRAM bus traffic.

  1. AV DD should be derived from VDD using the following circuit:

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Revision 1.07 – September 10, 2007 Data Sheet Test Conditions Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table “Recommended DC Operating Conditions.” For all signals other than PCI signals, AC specifications are characterized at OV DD = 3V and TC = 85°C with the 50pF test load shown in the figure at right. For PCI signals there are two different test load circuits, one for the rising edge and one the falling edge as shown in the figures at right. Output Pin 50pF All signals other than PCI Output Pin 10pF 25Ω Output Pin 10pF 25Ω OVDD PCI Rising edge PCI Falling edge

Figure 4. Clocking Waveform Table 12. Clocking Specifications

333.33 MHz

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Revision 1.07 – September 10, 2007 Data Sheet Spread Spectrum Clocking Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405EP. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the PPC405EP the following conditions must be met:

  • The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC405EP with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency.
  • The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed 40kHz. In some cases, on-board PPC405EP peripherals impose more stringent requirements (see Note 1).
  • Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock tracks the modulation.
  • Use the SDRAM MemClkOut since it also tracks the modulation. Notes: 1. The serial port baud rates are synchronous to the modu lated clock. The serial port has a tolerance of approx- imately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaf- fected by the modulation. 2. Operation of the PPC405EP PCI Bridge is unaffected by the use of an SSCG. The PCI controller must be operated in asynchronous mode. When in asynchronous mode, the PCI bus clock must be driven into the PPC405EP PCIClk input. In this configuration the PCI controller supports the

66.66 MHz PCI clock specification which specifies a ma ximum frequency deviation of -1% at a modulation of

between 30 kHz and 33 kHz. 3. Ethernet operation is unaffected. 4. IIC operation is unaffected. Caution: It is up to the system designer to ensure that any SSCG used with the PPC405EP meets the above requirements and does not adversely affect other aspects of the system.

Table 13. Peripheral Interface Clock Timings

  1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405EP Embedded Processor

User’s Manual for more information.

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Figure 5. Input Setup and Hold Timing Waveform Figure 6. Output Delay and Float Timing Waveform

Table 14. I/O Specifications—Group 1 (Sheet 1 of 2)

  1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns
  2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter

selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User’s Manual.

1 OPB clock

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Table 14. I/O Specifications—Group 1 (Sheet 2 of 2)

  1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns
  2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter

selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User’s Manual.

Table 15. I/O Specifications—Group 2

  1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
  2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
  3. SDRAM interface hold times are guaranteed at the PPC405EP package pin. System designers must use the PPC405EP IBIS

the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.

  1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
  2. IOH is specified at 2.4V and IOL is specified at 0.4V.

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The following describes the method by which initial chip settings are established when a system reset occurs. strapping options. The signal names assigned to the pins for normal operation appear below the pin number. values are covered in detail in the PowerPC 405EP Embedded Processor User’s Manual. reset state and will not boot. Table 16. Strapping Pin Assignments

PPC405EP – PowerPC 405EP Embedded Processor Revision 1.07 – September 10, 2007 AMCC 49 Data Sheet Document Revision History Revision Date Description 1.01 07/30/04 Initial Release 1.02 01/10/05 Add lead-free part num bers and clean up AMCC conversion. 1.03 05/01/07 Add information on connection of target device IDSEL to the addess bus. Modify description of TRST signal. Remove note on TrcClk concerning initilization. 1.04 06/01/07 Update package thickness values (package drawing). Add Logo View to package drawing. 1.05 07/18/07 Add instructions to PHY clock signals indi cating they must be present even if interface is not used. 1.06 09/06/07 Correct AMCC phone numbers. 1.07 09/10/07 Change TestEn signal fr om active low to active high.

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Revision 1.07 – September 10, 2007 Data Sheet Applied Micro Circuits Corporation

215 Moffett Park Drive, Sunnyvale, CA 94089

Phone: (408) 542-8600 — (800) 840-6055 — Fax: (408) 542-8601 http://www.amcc.com AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially co mply with the latest available datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service wi thout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any lia- bility arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the ri ght to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED , INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2007 Applied Micro Circuits Corporation.