PPC405CR AMCC | Alldatasheet

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Features

  • P o w e r P C® 405 32-bit RISC processor core operating up to 266MHz - Memory Management Unit - 16KB instruction and 8KB data caches - Multiply-Accumulate (MAC) function, including fast multiply unit - Programmable Timers
  • Synchronous DRAM (SDRAM) interface oper- ating up to 133MHz - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications
  • External Peripheral Bus - Flash ROM/Boot ROM interface - Direct support for 8-, 16-, or 32-bit SRAM and external peripherals - Up to eight devices - External Mastering supported
  • DMA support for external peripherals, internal UART and memory - Scatter-gather chaining supported - Four channels
  • Programmable Interrupt Controller supports interrupts from a variety of sources - Supports 7 external and 10 internal interrupts - Edge triggered or level-sensitive - Positive or negative active - Non-critical or critical interrupt to processor core - Programmable critical interrupt priority ordering
  • Two serial ports (16550 compatible UART)
  • One IIC interface
  • General Purpose I/O (GPIO) available
  • Supports JTAG for board level testing
  • Internal Processor Local Bus (PLB) runs at SDRAM interface frequency

Description

The PowerPC 405CR (PPC405CR) is a 32-bit RISC embedded controller. High performance, peripheral integration, and low cost make the device ideal for wired communications, network printers, and other computing applications. This device is an easy upgrade for systems based on PowerPC 403xx embedded processors, while provid- ing a base for custom chip designs. The controller is powered by a PPC405 embedded core. This core tightly couples a 266 MHz CPU, MMU, instruction and data caches , and debug logic. Fine- tuning of the core reduces data transfer overhead, minimizes pipeline stalls, and improves performance. The PPC405CR employs the IBM CoreConnect ™ bus architecture. This architecture, as implemented on the PPC405CR, consists of a 64-bit, 133-MHz Processor Local Bus (PLB) and a 32-bit, 66-MHz On-Chip Peripheral Bus (OPB). High-performance peripherals attach to the PLB and less performance-critical periph- erals attach to the OPB. Technology: CMOS SA-12E 0.25 µm (0.18 µm L eff) Package: 27mm, 316-ball enhanced plastic ball grid array (E-PBGA) Power (estimated): Typical 0.8W, Maximum 2.0W at 200MHz.

PPC405CR – PowerPC 405CR Embedded Processor

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Revision 1.02 – January 11, 2005 Data Sheet Ordering, PVR, and JTAG Information This section provides the part numb ering nomenclature for th e PPC405CR. For availability, contact your local AMCC sales office. Each part number contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) is software accessible and contains additional information about the revi- sion level of the part. Refer to the PPC405CR Embedded Processor User’s Manual for details on the register content. Part Number Key Product Name Order Part Number1, 2 Processor Frequency Package Rev Level PVR Value JTAG ID PPC405CR PPC405CR-3BC133C 133MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049 PPC405CR PPC405CR-3BC133CZ 133MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049 PPC405CR PPC405CR-3KC133C 133MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049 PPC405CR PPC405CR-3KC133CZ 133MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049 PPC405CR PPC405CR-3BC200C 200MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049 PPC405CR PPC405CR-3BC200CZ 200MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049 PPC405CR PPC405CR-3KC200C 200MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049 PPC405CR PPC405CR-3KC200CZ 200MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049 PPC405CR PPC405CR-3BC266C 266MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049 PPC405CR PPC405CR-3BC266CZ 266MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049 PPC405CR PPC405CR-3KC266C 266MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049 PPC405CR PPC405CR-3KC266CZ 266MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049 Notes: 1. Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray. 2. Package type B contains lead; package type K is lead-free. Part Number PPC405CR-3BC266Cx Package (E-PBGA) Processor SpeedGrade 3 Reliability Operational Case Temperature Revision Level Shipping Package Blank = Tray Z = Tape and reel (-40°C to +85°C)Range 200MHz 266MHz 133MHz

Figure 1. PPC405CR Embedded Controller Functional Block Diagram way to create complex ASICs using IBM CoreConnect™ Bus Architecture.

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Table 1. System Memory Address Map (4GB System Memory)

  1. When peripheral bus boot is selected, Peripheral bank 0 is automatically configured at reset to the address range listed above.
  2. After the boot process, software may reassign the boot memory region for other uses.
  3. All address ranges not listed above are reserved.

Table 2. DCR Address Map

  1. DCR address space is addres sable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit

(word) register, or 1 kiloword (KW) (which equals 4 KB).

PPC405CR – PowerPC 405CR Embedded Processor Revision 1.02 – January 11, 2005 AMCC 7 Data Sheet SDRAM Memory Controller The PPC405CR Memory Controller core provides a low latency access pa th to SDRAM memory. A variety of sys- tem memory configurations are supported. The memory controller supports up to four logical banks. Up to 256MB per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and memory addressing modes are programmable. Features include:

  • 11x8 to 13x11 addressing for SDRAM (2- and 4-bank)
  • 32-bit memory interface support
  • Programmable address compare for each bank of memory
  • Industry standard 168-pin DIMMS ar e supported (some configurations)
  • 4MB to 256MB per bank
  • Programmable address mapping and timing
  • Auto refresh
  • Page mode accesses with up to 4 open pages
  • Power Management (self-refresh)
  • Error Checking and Correction (ECC) support - Standard SEC/DED coverage - Aligned nibble error detect - Address error logging External Peripheral Bus Controller (EBC)
  • Supports eight banks of ROM, EPROM, SRAM, Flash memory, or slave peripheral I/O
  • Up to 66MHz operation
  • Burst and non-burst devices
  • 8-, 16-, 32-bit byte-addressable data bus width support
  • Programmable 2K clock time-out counter with disable for Ready
  • Programmable access timing per device - 0–255 wait states for non-burst devices - 0–31 burst wait states for first access and up to 7 wait states for subsequent accesses - Programmable CSon, CSoff relative to address - Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS
  • Programmable address mapping
  • Peripheral device pacing with external “Ready”
  • External master interface - Write posting from external master - Read prefetching on PLB for external master reads - Bursting capable from external master - Allows external master access to all non-EBC PLB slaves - External master can control EBC slaves for own access and control DMA Controller
  • Supports the following transfers: - Memory-to-memory transfers - Buffered peripheral to memory transfers

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Revision 1.02 – January 11, 2005 Data Sheet - Buffered memory to peripheral transfers

  • Four channels
  • Scatter/Gather capability for pr ogramming multiple DMA operations
  • 8-, 16-, 32-bit peripheral support (OPB and external)
  • 32-bit addressing
  • Address increment or decrement
  • Internal 32-byte data buffering capability
  • Supports internal and external peripherals
  • Support for memory mapped peripherals
  • Support for peripherals running on slower frequency buses UART
  • One 8-pin UART and one 4-pin UART interface provided
  • Selectable internal or external serial clock to allow wide range of baud rates
  • Register compatibility wit h NS16550 register set
  • Complete status reporting capability
  • Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
  • Fully programmable serial-i nterface characteristics
  • Supports DMA using internal DMA engine IIC Bus Interface
  • Compliant with Phillips® Semiconductors I2C Specification, dated 1995
  • Operation at 100kHz or 400kHz
  • 8 - b i t d a t a
  • 10- or 7-bit address
  • Slave transmitter and receiver
  • Master transmitter and receiver
  • Multiple bus masters
  • Supports fixed V DD IIC interface
  • Two independent 4 x 1 byte data buffers
  • Twelve memory-mapped, fully prog rammable configuration registers
  • One programmable interrupt request signal
  • Provides full management of all IIC bus protocol
  • Programmable error recovery General Purpose IO (GPIO) Controller
  • Controller functions and GPIO registers are pr ogrammed and accessed via memory-mapped OPB bus master accesses.
  • All GPIOs are pin-shared with other functions. DCRs co ntrol whether a particular pin that has GPIO capabil- ities acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with: - 7 of 8 chip selects. - All seven external interrupts. - All nine instruction trace pins.
  • Each GPIO output is separately programmable to emulat e an open-drain driver (two states, drive to zero or open circuit).

PPC405CR – PowerPC 405CR Embedded Processor Revision 1.02 – January 11, 2005 AMCC 9 Data Sheet Universal Interrupt Controller (UIC) The Universal Interrupt Controller (U IC) provides the control, status, an d communications necessary between the various sources of interrupts and the local PowerPC processor. Features include:

  • Supports 7 external and 10 internal interrupts
  • Edge triggered or level-sensitive
  • Positive or negative active
  • Non-critical or critical interrupt to PPC405 processor core
  • Programmable critical interrupt priority ordering
  • Programmable critical interrupt ve ctor for faster vector processing JTAG
  • IEEE 1149.1 te st access port
  • IBM RISCWatch debugger support
  • JTAG Boundary Scan Description Language (BSDL)

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Figure 2. 27mm, 316-Ball E-PBGA Package

1.27 TYP

27.0 REF

2.65 MAX

7.5 TYP

15.0 TYP

Notes: 1. All dimensions are in mm.

  1. Package available in leaded and lead-free configurations.

signals in the indicated interface group begin. Table 3. Signals Listed Alphabetically

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Table 3. Signals Listed Alphabetically (Sheet 2 of 7)

Table 3. Signals Listed Alphabetically (Sheet 3 of 7)

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Table 3. Signals Listed Alphabetically (Sheet 4 of 7)

Table 3. Signals Listed Alphabetically (Sheet 5 of 7)

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  1. Other reserved pins are not connected internally within the chip and

should not have signals, voltage, or ground applied to them. Table 3. Signals Listed Alphabetically (Sheet 6 of 7)

Table 3. Signals Listed Alphabetically (Sheet 7 of 7)

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Table 4. Signals Listed by Ball Assignment (Sheet 1 of 3)

Table 4. Signals Listed by Ball Assignment (Sheet 2 of 3)

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Table 4. Signals Listed by Ball Assignment (Sheet 3 of 3)

lowing table provides a summary of the number of package pins associated with each functional interface group. example, GPIO1[TS1E]). Active-low signals (for example, RAS) are marked with an overline. It is expected that in any single app lication a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. and received by the EBC in the PPC405CR. are not multiplexed pins since the function of the pins is not programmable. Table 5. Pin Summary

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Revision 1.02 – January 11, 2005 Data Sheet If your system-level test meth odology permits, input-only signals c an be connected together and terminated through either a common resistor or directly to +3.3V or GND. When a resistor is used , its value must ensure that the grouped I/Os reach a valid logic zero or logic one stat e when accounting for the total input current into the PPC405CR. Unused I/Os Strapping of some pins may be necessary when they are unused. Although the PPC405CR requires only the pull- up and pull-down terminations as specified in the “Signal Functional Description” on page 23, good design practice is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral and SDRAM buses should be configured and terminated as follows:

  • Peripheral interface—PerAddr0:31, PerData0:31, and a ll of the control signals are driven by default. Termi- nate PerReady high and PerError low.
  • SDRAM—Program SDRAM0_CFG[EMDULR]=1 and SDRA M0_CFG[DCE]=1. This causes the PPC405CR to actively drive all of the SDRAM address, data, and control signals. External Bus Control Signals All peripheral bus control signals (PerCS0:7 , PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck, ExtAck ) are set to the high-impedance state when ExtReset =0. In addition, as detailed in the PowerPC 405CR Embedded Processor User’s Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals between transact ions and/or when an external master owns the peripheral bus. As a result, a pull- up resistor should be added to those control signals where an undriven state may affect any devices receiving that particular signal. The following table lists all of the I/O signals provided by the PPC405CR. Please refer to “Signals Listed Alphabet- ically” on page 11 for the pin number to which each signal is assigned.

Table 6. Signal Functional Description (Sheet 1 of 5) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
  3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull-up or pull-down required.
  7. Pull-up may be required. See “External Bus Control Signals” on page 22.
  8. MemData0 is the most significant bit (msb).
  9. MemData31 is the least significant bit (lsb).
  10. MemAddr12 is the most significant bit (msb).
  11. MemAddr0 is the least significant bit (lsb).

mode, otherwise used by external master. Note: PerData0 is the most significant bit (msb) on this bus. master mode, otherwise used by external master. Note: PerAddr0 is the most significant bit (msb) on this bus. external bus master owns the external interface.

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master, it enables the selected device to drive the bus. indicates a write to memory. Table 6. Signal Functional Description (Sheet 2 of 5) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
  3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull-up or pull-down required.
  7. Pull-up may be required. See “External Bus Control Signals” on page 22.

individually connected to either UART. Table 6. Signal Functional Description (Sheet 3 of 5) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
  3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull-up or pull-down required.
  7. Pull-up may be required. See “External Bus Control Signals” on page 22.

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(two states, 0 or open circuit). Table 6. Signal Functional Description (Sheet 4 of 5) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
  3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull-up or pull-down required.
  7. Pull-up may be required. See “External Bus Control Signals” on page 22.

Table 6. Signal Functional Description (Sheet 5 of 5) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
  3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull-up or pull-down required.
  7. Pull-up may be required. See “External Bus Control Signals” on page 22.

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Table 7. Absolute Maximum Ratings Note: All specified voltages are with respect to GND. Figure 3. Package Thermal Specifications

  1. For a chip mounted on a JEDEC 2S2P card without a heat sink.
  2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:

a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. b. TA = TC – P×θCA, where TA is ambient temperature and P is power consumption. c. TCMax = TJMax – P×θJC, where TJMax is maximum junction temperature and P is power consumption.

Table 8. Recommended DC Operating Conditions conditions can affect device reliability.

  1. See “5V-Tolerant I/O Input Current” on page 30

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Figure 4. 5V-Tolerant I/O Input Current Table 9. Input Capacitance

+85°C with the 50pF test load shown in the figure at right. Table 10. DC Electrical Characteristics

  1. Maximum power is characterized at V DD = 2.7V, OVDD = 3.6V, TC = 85°C, across the silicon process (worse case to best case), while
  2. AV DD should be derived from VDD using the following circuit:

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Figure 5. Timing Waveform Table 11. Clocking Specifications

PPC405CR – PowerPC 405CR Embedded Processor Revision 1.02 – January 11, 2005 AMCC 33 Data Sheet Spread Spectrum Clocking Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405CR. This controller uses a PLL for clock generation inside the chip. The accu racy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle dete rmine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the PPC405CR the following conditions must be met:

  • The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC405CR with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency.
  • The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed 40kHz. In some cases, on-board PPC405CR peripherals impose more stringent requirements (see Note 1).
  • Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock tracks the modulation.
  • Use the SDRAM MemClkOut since it also tracks the modulation. Notes: 1. The serial port baud rates are synchronous to the modu lated clock. The serial port has a tolerance of approx- imately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaf- fected by the modulation. 2. IIC operation is unaffected. Caution: It is up to the system designer to ensure th at any SSCG used with the PPC405CR meets the above requirements and does not adversely affect other aspects of the system.

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Table 12. Peripheral Interface Clock Timings frequency is 50MHz for 200MHz parts and 66.66MHz.for 266MHz parts.

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  1. See “Test Conditions” on page31 for output capacitive loading.
  2. I/O H is specified at 2.4V; I/O L is specified at 0.4V

Table 13. I/O Specifications—All speeds

Table 14. I/O Specifications—133 and 200MHz

  1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
  2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
  3. SDRAM interface hold times are guaranteed at the PPC405CR package pin. System designers must use the PPC405CR

and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.

  1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
  2. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.

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Table 15. I/O Specifications—266MHz

  1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
  2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
  3. SDRAM interface hold times are guaranteed at the PPC405CR package pin. System designers must use the PPC405CR

and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.

  1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
  2. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.

tions and strapping options. The signal names assigned to the pins for normal operation follow the pin number. Table 16. Strapping Pin Assignments (Sheet 1 of 2)

2 C16

2 B16

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  1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the

documents area of the AMCC PowerPC web site.

  1. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “Clocking
  2. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by using

three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs. Table 16. Strapping Pin Assignments (Sheet 2 of 2)

PPC405CR – PowerPC 405CR Embedded Processor Revision 1.02 – January 11, 2005 AMCC 41 Data Sheet Document Revision History Revision Date Description 1.01 08/05/04 Initial release 1.02 01/11/05 Add lead-free part numbers.

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Revision 1.02 – January 11, 2005 Data Sheet Applied Micro Circuits Corporation 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data sheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service wi thout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any lia- bility arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the ri ght to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED , INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2005 Applied Micro Circuits Corporation.