PN7160

NXP Semiconductors

Near Field Communication (NFC) controller Rev. 4.0 - 5 September 2024

Manufacturer: NXP Semiconductors

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Document overview

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PDF pages: 67

Technical content

Datasheet sections

1 Introduction
2 General description
3 Features and benefits
4 Applications
5 Quick reference data
6 Firmware versions
6.1 Firmware version and model ID retrieval
7 Ordering information
8 Marking
8.1 Marking VFBGA64
8.2 Marking HVQFN40
9 Block diagram
10 Pinning information
10.1 Pinning
11 Functional description
11.1 System modes
11.1.1 System power modes
11.1.2 PN7160 power states
11.1.2.1 Hard Power Down (HPD) state
11.1.2.2 Standby state
11.1.2.3 Active state
11.1.2.4 Polling loop
11.2 Host interfaces
11.2.1 I2C-bus interface
11.2.1.1 I2C-bus configuration
11.2.2 Serial Peripheral Interface bus (SPI-bus)
11.2.2.1 Features
11.2.2.2 SPI-bus configuration options
11.2.2.3 SPI-bus functional description
11.3 PN7160 clock concept
11.3.2 Integrated PLL to make use of external
11.3.4 Low-power 370 kHz oscillator
11.4 Power concept
11.4.1 PMU functional description
11.4.2 DSLDO: Dual Supply LDO
11.4.3 TXLDO
11.4.3.1 Configuration 1: the battery voltage is
11.4.3.2 Configuration 2: an extra external voltage is
11.4.3.3 TXLDO limiter
11.4.3.4 TXLDO: configuration
11.4.4 Very low-power RF field detector
11.5 Reset and download concept
11.5.1 Resetting PN7160
11.5.2 Power-up sequences
11.5.2.1 VBAT is set up before VDD(PAD)
11.5.2.2 VDD(PAD) and VBAT are set up at the
11.5.2.3 PN7160 has been enabled before
11.5.3 Power-down sequences
11.5.4 Download mode
11.6 Contactless Interface Unit
11.6.1 Reader/Writer communication modes
11.6.1.1 R/W mode for NFC Forum Type 1 and
11.6.1.2 R/W mode for NFC Forum Type 3 Tag,
11.6.1.3 R/W mode for NFC Forum type 4 Tag (T4T)
11.6.1.4 R/W mode for NFC Forum Type 5 Tag
11.6.2 ISO/IEC 18092, Ecma 340 NFCIP-1
11.6.2.1 Active communication mode
11.6.2.2 Passive communication mode
11.6.2.3 NFCIP-1 framing and coding
11.6.2.4 NFCIP-1 protocol support
11.6.3 Card mode
11.6.3.1 NFC Forum T4T, ISO/IEC 14443A
11.6.3.2 NFC Forum T4T, ISO/IEC 14443B card
11.6.4 Frequency interoperability
12 Limiting values
13 Recommended operating conditions
14 Thermal characteristics
15 Characteristics
15.1 Current consumption characteristics
15.2 Functional block electrical characteristics
15.2.1 Reset via VEN
15.2.2 Power-up timings
15.2.3 Power-down timings
15.2.4 Download mode timings
15.2.5 I2C-bus timings
15.2.6 SPI-bus timings
15.2.7 Active load modulation phase
15.3 Pin characteristics
15.3.1 NFC_CLK_XTAL1 and XTAL2 pins
15.3.2 VEN input pin characteristics
15.3.3 Output pin characteristics for IRQ, CLK_
15.3.4 Output pin characteristics for TX_PWR_
15.3.5 Output pin characteristics for DCDC_EN
15.3.6 Input pin characteristics for DWL_REQ,
15.3.7 Input pin characteristics for RXN and RXP

PN7160_PN7161 Near Field Communication (NFC) controller Rev. 4.0 — 5 September 2024 Product data sheet

1 Introduction

This data sheet describes the PN7160 and PN7161 NFC controllers with NCI interface and integrated firmware. The PN7161 supports all features of PN7160 plus "Enhanced Contactless Polling" (ECP) by Apple (see Ref. [13]). Please note, that the ECP feature is available after formal authorization only. In the following document PN7160 refers to PN7160 and PN7161, otherwise stated. This data sheet requires additional documents for functional chip description and design in. Refer to the references listed in this document for full list of documentation provided by NXP.

2 General description

A low PCB footprint and a reduced external Bill of Material
An optimized architecture for low-power consumption in different modes (Standby, low-power polling loop)
A highly efficient integrated power management unit allowing direct supply from an extended battery supply range (2.8 V to 5.5 V).
Support of an external DC-to-DC like NXP PCA941xA (with x = 0, 1 and 2), to provide more output power. PN7160 embeds a new generation RF contactless front-end, supporting various transmission modes according to NFCIP-1 (see Ref. [9]) and NFCIP-2 (see Ref. [11]), ISO/IEC14443 (see Ref. [3]) , ISO/IEC 15693 (see Ref. [10]), MIFARE and FeliCa specifications. This new contactless front-end design brings a major performance step-up with on one hand a higher sensitivity and on the other hand the capability to work in active load modulation communication enabling the support of small antenna form factor. It also allows to provide a higher output power by supplying the transmitter output stage from 2.7 V to 5.25 V.
Enhanced Dynamic LMA (DLMA) to optimize and to enhance load modulation amplitude depending on external field strength. It allows higher range communication distance in card mode.
Independent LMA phase adjustment by step of 5° for type A, B and F
Dynamic power control which allows to make use of the maximum power in reader mode without exceeding the maximum power allowed by the standard in 0 distance.
Card mode receiver sensitivity of 20 mV(p-p)
Support of single ended receiver
1.3 W output transmitter power Supported transmission modes are listed in Figure 1. For contactless card functionality, the PN7160 can act autonomously if previously configured by the host in such a manner. PICC functionality can be supported without host being turned on. CARD (PICC) T4T - ISO/IEC 14443 A T4T - ISO/IEC 14443 B READER (PCD - VCD) ISO/IEC 14443 A ISO/IEC 14443 B ISO/IEC 15693 MIFARE 1K / 4K MIFARE DESFire Sony FeliCa(1) NFC FORUM NFC-IP MODES READER FOR NFC FORUM TAGS 1 TO 5 P2P ACTIVE

106 TO 424 kbps

According to ISO/IEC 18092 (Ecma 340) standard.

NXP Semiconductors PN7160_PN7161 Near Field Communication (NFC) controller

3 Features and benefits

Highly integrated demodulator and decoder
Buffered output drivers to connect an antenna with minimum number of external components
Integrated RF level detector
Integrated Polling Loop for automatic device discovery
RF protocols supported – ISO/IEC 14443A, ISO/IEC 14443B PICC mode – ISO/IEC 14443A, ISO/IEC 14443B PCD mode designed according to NFC Forum digital protocol T4T platform and ISO-DEP (see Ref. [1]) – FeliCa PCD mode – MIFARE PCD encryption mechanism (MIFARE 1K/4K) – NFC Forum tags T1T, T2T, T3T, T4T and T5T (see Ref. [1]) – NFCIP-1, NFCIP-2 protocol (see Ref. [9] and Ref. [11]) – Only up to Frimware version 12.50.0A: NFC Forum certification for P2P, reader and card mode (see Ref. [1]) – ISO/IEC 15693/ICODE VCD mode (see Ref. [10]) – NFC Forum-compliant embedded T4T for NDEF short record – Support for "Enhanced Contactless Polling" by Apple (see Ref. [13]) (PN7161 only)
Supported host interfaces – NCI 2.0 protocol interface according to NFC Forum standardization (see Ref. [2]) – I2C-bus High-speed mode (see Ref. [4]) – SPI-bus (see Ref. [5])
Flexible clock supply concept to facilitate PN7160 integration – Internal oscillator for 27.12 MHz crystal connection – Integrated PLL unit to make use of device reference clock and facilitate PN7160 integration
Integrated power management unit – Direct connection to a battery (2.5 V to 5.5 V voltage supply range) – Support different low-power states configuration: Hard Power-Down state and Standby state activated by firmware – Autonomous mode when host is shut down
Automatic wake-up via RF field, internal timer, and host interfaces
Integrated non-volatile memory to store data and executable code for customization – Anti tearing support to recover from tearing events
Standards compliance – NFC Forum Device Requirements (see Ref. [1]) – NCI 2.0 PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4.0 — 5 September 2024 Document feedback

NXP Semiconductors PN7160_PN7161 Near Field Communication (NFC) controller

4 Applications

Mobile devices
Portable equipment (personal digital assistants, tablet, notebook, wearable)
Consumer devices
Smart home gateways PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4.0 — 5 September 2024 Document feedback

5 Quick reference data

3.6 V; T = 25 °C

Table 1. Quick reference data [1] VSS represents VSS(PAD) and VSS(TX). kbit/s will affect the performance. [3] External clock on NFC_CLK_XTAL1 must be LOW. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

NXP Semiconductors PN7160_PN7161 Near Field Communication (NFC) controller

6 Firmware versions

6.1 Firmware version and model ID retrieval

It is possible to identify a dedicated installed firmware version. In addition, the product versions PN7160 and PN7161 can be differentiated thanks to the model ID.

model ID value 0x61 indicates PN7160
model ID value 0x71 indicates PN7161 The 9th byte of the CORE_RESET_NTF indicates the model ID. The 10th, 11th, and 12th bytes of the CORE_RESET_NTF indicate the installed FW version. Example: The model ID is retrieved from the CORE_RESET_NTF following CORE_RESET_CMD/RSP sequence (first NCI exchanges when initializing PN7160/PN7161). In the following NCI exchange sequence: >> 20 00 01 00 // CORE_RESET_CMD << 40 00 01 00 // CORE_RESET_RSP << 60 00 09 02 00 20 04 04 71 12 50 05 // CORE_RESET_NTF The 9th byte of the CORE_RESET_NTF indicates the model ID (0x71 in the example above == PN7161) . The 10th, 11th, and 12th bytes od the CORE_RESET_NTF indicate the FW version (0x12, 0x50, 0x05 point to FW version 12.50.05). 6.2 Version 12.50.0E Changes in this version:
Fixed stability issues during handling of RF_DEACTIVATE_CMD (to IDLE) and RF_DEACTIVATE_ RSP. 6.3 Version 12.50.0D Changes in this version:
Added support for custom cards with specific SAK value. API added is: 0xA0 0x6E. 6.4 Version 12.50.0C Changes in this version:
Added support for dynamic ECP configuration. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4.0 — 5 September 2024 Document feedback

NXP Semiconductors PN7160_PN7161 Near Field Communication (NFC) controller 6.5 Version 12.50.0B Changes in this version:

Optimized the flash contents, removed not required features for longer serviceability of PN7160: – Type-F card mode support removed. – Support for P2P not claimed. 6.6 Version 12.50.0A Changes in this version:
T4T Card emulation (NFCEE_NDEF) update. (Now allowing NDEF WRITE from RF side, working with TagWriter application on Android). 6.7 Version 12.50.09 Changes in this version:
NDEF write from NFC supported, when the device is in Autonomous NDEF mode.
ECP supported in EMVCo profile (PN7161 only).
Optimized card removal procedure when ECP is enabled (PN7161 only).
Added PRBS support for ISO/IEC 15693.
This version is not available on hardware, only as a firmware update file. 6.8 Version 12.50.08 Changes in this version:
Resolved an issue in which the IC is hung with RF ON when a Type B card is placed during the discovery process when ECP is enabled for NFC Forum profile. 6.9 Version 12.50.07 Changes in this version:
ECP is supported in EMVCo profile. 6.10 Version 12.50.06 Changes in this version:
Changes to support NFC Forum CR12.
Added helper command to configure the Dynamic Power Control (DPC).
This version is not available on hardware, only as a firmware update file. 6.11 Version 12.50.05 Initial version Production samples will have 12.50.05 firmware. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4.0 — 5 September 2024 Document feedback

7 Ordering information

Table 2. Ordering information [1] x: A = I2C-bus interface; B = SPI-bus interface. [2] y: correspond to firmware variant. [3] zz: correspond to package variant. HN = HVQFN40 package; EV = VFBGA64 package. Table 3. Product variants PN7160 PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

8 Marking

8.1 Marking VFBGA64

Figure 2. PN7160 package marking (top view)

diffusion center code: – S: Power chip (PTCT)
assembly center code: – S: ATKH
RoHS compliancy indicator: – D: Dark Green; fully compliant RoHS and no halogen and antimony
manufacturing year and week, 3 digits: – Y: year – WW: week code
product life cycle status code: – X: means not qualified product – nothing means released product

8.2 Marking HVQFN40

Figure 3. PN7160 Package marking HVQFN40 (top view)

diffusion center code: – S: Power chip (PTCT)
assembly center code: – S: ATKH
RoHS compliancy indicator: – D: Dark Green; fully compliant RoHS and no halogen and antimony
manufacturing year and week, 3 digits: – YY: year – WW: week code
product life cycle status code: – X: means not qualified product – nothing means released product

9 Block diagram

40 MHz

10 Pinning information

10.1 Pinning

Figure 5. PN7160 pinning VFBGA64 (bottom view) Figure 6. PN7160 pinning HVQFN40 i.c. 11 - - - Internally Connected. To be left open. Table 7. PN7160 pin description PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

VDD 27 - Must be connected to AVDD and DVDD. VFBGA package: internally connected. VDD(D) 31 C7 P n/a Digital supply voltage for decoupling. Must be connected to VDD and VDD(A). Table 7. PN7160 pin description...continued PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

i.c. - A4 Must be connected to ground. i.c. - A7 Must be connected to ground. i.c. - G1 Must be connected to ground. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

11 Functional description

specific product features. This IC is fully user controllable by the firmware interface described in Ref. [6]. Figure 7. PN7160 connection in mobile system

11.1 System modes

11.1.1 System power modes

4 power modes are specified: Full power mode, Autonomous mode, Low-power mode and Power Off mode. In case of reset via VEN pin the AutoMode bit value is kept unchanged. host communication is available. Table 8. System power modes description PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

When VBAT goes OFF, AutoMode = 0.

Figure 8. System power mode diagram Table 9. System power modes configuration Table 10. System power modes description

11.1.2 PN7160 power states

status of the system. Thus extend the power modes. 3 power states are specified: Hard Power Down (HPD), Standby, Active. consumption. The system mode is in Power Off. Table 11. PN7160 power states PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

system mode is Low-power mode or Full power mode. defined: Idle, Listener and Poller. The system mode is Full power mode. Table 11. PN7160 power states...continued consumption (polling loop mode). Refer to Table 1 for targeted current consumption in here described states. The PN7160 is designed to allow the host controller to have full control over its functional states.

11.1.2.1 Hard Power Down (HPD) state

these signals are under host control, the PN7160 has no influence on entering or exiting this state.

11.1.2.2 Standby state

switch to Standby state autonomously (if configured by host). This state is independent of the VDD(PAD) value.

Host interface wake-up event (I2C-bus, SPI-bus)
Host interface wake-up via WKUP_REQ pin
Antenna RF level detector
Internal timer event when using polling loop (370 kHz Low-power oscillator is enabled) If wake-up event occurs, PN7160 will switch to Active state. Any further operation depends on software configuration and/or wake-up source.

11.1.2.3 Active state

Listener the PN7160 is active and is listening to external device. The RF interface is activated. Table 12. Functional modes in active state PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

not be used with VBAT < 2.8 V. VDD(PAD) is within its operational range (see Table 1). Standby state to save energy.

11.1.2.4 Polling loop

supported by PN7160 can be independently enabled within this polling loop.

Listening phase. The PN7160 can be in Standby power state or Idle mode (called pause in Figure 9; no communication is on-going) or Listener mode (called Emulation in Figure 9; card / target communication is started)
Polling phase. The PN7160 is in Poller mode aaa-016741 Emulation Pause Type A Type B Type F @424 Type F @212ISO15693 Listening phase Polling phase

Figure 9. Polling loop: all phases enabled Listener mode (Emulation) when RF field is detected. When in Polling phase, PN7160 goes to Poller mode. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

consumption is around 100 μA depending on RF matching conditions. Figure 10. Polling loop: low-power RF polling Detailed description of polling loop configuration options is given in Ref. [6].

11.2 Host interfaces 2

I2C-bus Target Interface, up to 3.4 MBaud
SPI-bus Target Interface, up to 7 MBaud Only one host interface can be active at a time, as the pins are shared for all interfaces. The selection between interfaces is fused during IC manufacturing so that different ordering numbers for the I2C-bus and SPI-bus version are in place. The host interfaces are woken-up in the following way:
wake-up with WKUP_REQ input pin
I2C-bus: wake-up on I2C-bus address
SPI-bus: transition of NSS serial
data received on RX line 2 Updated the terms "Master/Slave" to "Controller/Target" to align with the recommendation of the NXP - I2C standards organization. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4.0 — 5 September 2024 Document feedback

line IRQ is provided which Active state is programmable. See Ref. [6] for more information.

11.2.1 I2C-bus interface2

and target address recognition.

Support target I2C-bus
Standard, Fast and High-speed modes supported
Wake-up of PN7160 on its address only
Serial clock synchronization can be used by PN7160 as a handshake mechanism to suspend and resume serial transfer (clock stretching) The I2C-bus interface module meets the I2C-bus specification Ref. [4] except General call, 10 bit addressing and Fast mode Plus (Fm+).

11.2.1.1 I2C-bus configuration

configured in EEPROM settings, functionality of the interface pins changes as described in Table 13. Table 13. Functionality for I2C-bus interface [1] HIF3 and HIF4 are not fail-safe and VDD(pad) shall always be available when using the SCL and SDA lines connected to these pins. top of a fixed binary header: 0, 1, 0, 1, 0, HIF2, HIF1, R/W. Table 14. I2C-bus interface addressing PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

11.2.2 Serial Peripheral Interface bus (SPI-bus)2

11.2.2.1 Features

Synchronous, Serial, Full-Duplex communication, 7 MHz maximum
Target mode

11.2.2.2 SPI-bus configuration options2

The CPOL/CPHA EEPROM settings are fixed as specified in Table 15.

CPHA = 0: data are sampled on MOSI on the odd clock edges of SCK after NSS goes low CPOL switch: Clock POLarity
IFSEL1 = 0: the clock is idle low and the first valid edge of SCK will be a rising one

Table 15. SPI-bus configuration Table 16. Functionality for SPI-bus interface

11.2.2.3 SPI-bus functional description2

both data out and data in synchronized with the same clock signal. the data out on the targets MISO line.

Controller In Target Out (MISO) The MISO line is configured as an input in a controller device and as an output in a target device. It is used to transfer data from the target to the controller, with the most significant bit sent first. The MISO line of a target device should be placed in the high impedance state if the target is not selected. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4.0 — 5 September 2024 Document feedback

Controller Out Target In (MOSI) The MOSI line is configured as an output in a controller device and as an input in a target device. It is used to transfer data from the controller to a target, with the Most Significant Bit (MSB) sent first.
Serial Clock (SCK) The serial clock is used to synchronize data movement both in and out of the device through its MOSI and MISO lines. The controller and target devices are capable of exchanging a byte of information during a sequence of eight clock cycles. Since the controller device generates SCK, this line becomes an input on a target device and an output at the controller device.
Not Target Select (NSS) The target select input line is used to select a target device. It has to be low prior to data transactions and must stay low of the duration of the transaction. The NSS line on controller side must be tied high. Both controller and target devices must operate with the same timing. The controller device always places data on the MOSI line a half cycle before the clock edge SCK, in order for the target device to latch the data. For more information about the SPI-bus functionality, see Ref. [5].

11.3 PN7160 clock concept

27.12 MHz clock coming either/or from: – Internal oscillator for 27.12 MHz crystal connection on NFC_CLK_XTAL1 and XTAL2 pins – External reference clock on pin NFC_CLK_XTAL1. It is internally forwarded to an integrated PLL which includes a 1 GHz VCO.
13.56 MHz RF clock recovered from RF field
Low-power oscillator 40 MHz
Low-power oscillator 370 kHz 11.3.1 27.12 MHz quartz oscillator When enabled, the 27.12 MHz quartz oscillator applied to PN7160 is the time reference for the RF front end when PN7160 is behaving in Reader mode or NFCIP-1 Initiator. Therefore stability of the clock frequency is an important factor for reliable operation. It is recommended to adopt the circuit shown in Figure 11. aaa-041133 NFCC NFC_CLK_XTAL1 XTAL2 crystal

27.12 MHz cc

Figure 11. 27.12 MHz crystal oscillator connection Table 17 describes the levels of accuracy and stability required on the crystal. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 17. Crystal requirements 18092, then ± 14 kHz apply which is equivalent to ± 516 ppm.

11.3.2 Integrated PLL to make use of external clock

The 27.12 MHz of the PLL is used as the time reference for the RF front end. Figure 12. Input reference phase noise characteristics MHz, 32 MHz, 38.4 MHz and 48 MHz. Table 18. PLL input requirements PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 18. PLL input requirements...continued 18092, then ± 7 kHz apply which is equivalent to ± 516 ppm. [2] Overshoot and undershoot shall not exceed 10%. For detailed description of clock request mechanisms, refer to Ref. [6] and Ref. [7]. Low-power 40 MHz ± 2.5 % oscillator is used as system clock of the system. Output clock 40 MHz is used by default to clock the system.

11.3.4 Low-power 370 kHz oscillator

state. This allows implementation of low-power reader polling loop at application level. Moreover, this 370 kHz is used as the reference clock for write access to EEPROM memory.

11.4 Power concept

11.4.1 PMU functional description

VDDA: analog output supply voltage. It must be connected to VDDD.
VDDD: digital input supply voltage. It is internally connected to the output of the DSLDO VDD.
VDD(TX): output supply voltage for the transmitter. It is internally connected to the transmitter input supply voltage The Figure 13 describes the main blocks available in PMU: PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4.0 — 5 September 2024 Document feedback

Figure 13. PMU functional diagram

11.4.2 DSLDO: Dual Supply LDO

The input pin of the DSLDO regulator is VBAT. The output of this regulator (VDD) is internally connected to supply the internal digital blocks which are on VDDD. It must be externally de-coupled and VDDD must be connected to VDDA.

11.4.3 TXLDO

Transmitter voltage is generated by internal LDO (VDD(TX)). NFC Forum standard compliant operations. Table 19. TXLDO

11.4.3.1 Configuration 1: the battery voltage is directly used to generate the RF field

Figure 16. VDD(TX) behavior when PN7160 is in Standby state

11.4.3.2 Configuration 2: an extra external voltage is used to generate the RF field

Figure 17. VDD(UP) up to 5.8 V, VBAT up to 5.5 V Figure 18 shows the behavior of VDD(TX) depending on VDD(UP) value. Figure 18. VDD(TX) behavior when PN7160 is supply using external supply on VDD(UP) PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

In Standby state, whatever VTHRESHOLD is configured, VDD(TX) is regulated at 2.5 V as illustrated by Figure 16.

11.4.3.3 TXLDO limiter

The TXLDO includes a current limiter to avoid too high current within TX1 and TX2. reached the output current gets limited.

11.4.3.4 TXLDO: configuration

Table 20. Configurations using TXLDO configuration 1, the voltage is given by the battery then the higher voltages might not be usable. when RF emission or RF field present). Note: the signal TX_PWR_REQ is not available on the HVQFN package variant.

11.4.4 Very low-power RF field detector

NFCC should detect the presence of an external magnetic field and notify the host system about its presence. Figure 19. Internal rectifier circuit PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

11.5 Reset and download concept

11.5.1 Resetting PN7160

to know which ones are accessible to tune PN7160 to the application environment.

Pulling VEN voltage high with VBAT within its operating range Figure 20 shows reset done via VEN pin. aaa-024833 host communication possible tboottWL(VEN)VEN VDD(PAD) VBAT

Figure 20. Resetting PN7160 via VEN pin See Section 15.2.1 for the timings values.

11.5.2 Power-up sequences

different supply sequence setup and VEN reset pin.

11.5.2.1 VBAT is set up before VDD(PAD)

supplied as soon the system is supplied. As VEN pin is referred to VBAT pin, VEN shall go high after VBAT has been set. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 21. VBAT is set up before VDD(PAD)

11.5.2.2 VDD(PAD) and VBAT are set up at the same time

This is the case, when VBAT pin is connected to a PMU/regulator which also supply VDD(PAD). Figure 22. VDD(PAD) and VBAT are set up in the same time

11.5.2.3 PN7160 has been enabled before VDD(PAD) is set up or before VDD(PAD) has been cut-off

Figure 23. VDD(PAD) is set up or cut-off after PN7160 has been enabled

11.5.3 Power-down sequences

During power-down sequence, VEN shall always be set low before VDD(PAD) is shut down. Figure 24. PN7160 power-down sequence See Section 15.2.1 for the timings values.

11.5.4 Download mode

PN7160 offers the possibility to download EEPROM with upgrades using the host interface commands, see Ref. To enter this mode, the pin DWL_REQ shall be pulled to VDD(PAD) before reset via VEN pin is done. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 25. PN7160 download mode sequence

11.6 Contactless Interface Unit

following chapters give more detailed overview of selected communication modes. beside the IC settings a suitable antenna tuning is required to achieve the optimum performance.

11.6.1 Reader/Writer communication modes

PCD Reader/Writer for ISO/IEC 14443A/MIFARE (NFC Forum Types 2 and 4 Tags)
PCD Reader/Writer for NFC Forum Type 1 Tag
PCD Reader/Writer for NFC Forum Type 3 Tag
PCD Reader/Writer for ISO/IEC 14443B (NFC Forum Type 4 Tag)
VCD Reader/Writer for NFC Forum Type 5 Tag

11.6.1.1 R/W mode for NFC Forum Type 1 and 2 Tags and Type 4 Tag type A

reader to card communication scheme according to the ISO/IEC 14443A specification. parameters (the numbers take the antenna effect on modulation depth for higher data rates). PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 26. R/W mode for NFC Forum T1T, T2T and T4T type A communication diagram Table 21. Communication overview for NFC Forum T1T, T2T and T4T type A R/W mode RF-protocol, nevertheless a dedicated external host has to handle the application layer communication.

11.6.1.2 R/W mode for NFC Forum Type 3 Tag, FeliCa communication mode

Figure 27. R/W mode for NFC Forum T3T communication diagram Table 22. Communication overview for NFC Forum T3T R/W mode, FeliCa communication mode dedicated external host has to handle the application layer communication.

11.6.1.3 R/W mode for NFC Forum type 4 Tag (T4T) type B

communication table describes the physical parameters. Figure 28. R/W mode for NFC forumT4T type B communication diagram PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 23. Communication overview for NFC Forum T4T type B R/W mode protocol, nevertheless a dedicated external host has to handle the application layer communication.

11.6.1.4 R/W mode for NFC Forum Type 5 Tag

kbit/s with single subcarrier. the tags (anti-collision sequence) on its own. Figure 29. R/W mode for NFC Forum T5T communication diagram Figure 29 shows the communication schemes used. The following communication scheme is possible. Table 24. Communication overview for NFC Forum T5T R/W mode PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 24. Communication overview for NFC Forum T5T R/W mode...continued

11.6.2 ISO/IEC 18092, Ecma 340 NFCIP-1 communication modes

NFC Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication.
NFC Target: responds to NFC Initiator command either in a load modulation scheme in Passive communication mode or using a self-generated and self-modulated RF field for Active communication mode. The NFCIP-1 communication differentiates between Active and Passive communication modes.
Active communication mode means both the NFC Initiator and the NFC Target are using their own RF field to transmit data
Passive communication mode means that the NFC Target answers to an NFC Initiator command in a load modulation scheme. The NFC Initiator is active in terms of generating the RF field. PN7160 supports the Active Initiator, Active Target, Passive Initiator and Passive Target communication modes at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the NFCIP-1 standard. NFCC BATTERY target: passive or activeinitiator: active HOST NFCC BATTERY HOST aaa-041141

Figure 30. NFCIP-1 communication mode modes and data rates, for both NFC Initiator and NFC Target. Nevertheless a dedicated external host has to handle the application layer communication. support will still be available. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

11.6.2.1 Active communication mode

NFC Initiator starts the communication at selected transfer speed
NFC Target answers at the same transfer speed

Figure 31. Active communication mode Table 25. Overview for Active communication mode on FeliCa range which is narrow (8 % to 14 % ASK). To adjust the index, see [8].

11.6.2.2 Passive communication mode

NFC Initiator starts the communication at selected transfer speed
NFC Target answers using load modulation at the same transfer speed

Figure 32. Passive communication mode Table 26. Overview for Passive communication mode on FeliCa range which is narrow (8 % to 14 % ASK). To adjust the index, see Ref. [8].

11.6.2.3 NFCIP-1 framing and coding

11.6.2.4 NFCIP-1 protocol support

Transaction includes initialization, anti-collision methods and data transfer. This sequence must not be interrupted by another transaction.
PSL shall be used to change the speed between the target selection and the data transfer, but the speed should not be changed during a data transfer.

11.6.3 Card mode

and ISO/IEC 14443B interface description. Remark: PN7160 does not support a complete card protocol. This has to be handled by the host controller. Table 27, Table 28 describe the physical parameters.

11.6.3.1 NFC Forum T4T, ISO/IEC 14443A

Table 27. Overview for NFC Forum T4T, ISO/IEC 14443A card mode

11.6.3.2 NFC Forum T4T, ISO/IEC 14443B card mode

Table 28. Overview for NFC Forum T4T, ISO/IEC 14443B card mode...continued

11.6.4 Frequency interoperability

signals as it is looking from data in the field. board according to Ref. [7]. capability, see Table 17 and Table 18. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12 Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Table 29. Limiting values PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

13 Recommended operating conditions

Table 30. Operating conditions [1] VSS represents VSS(PAD) and VSS(TX). kbit/s will affect the performance. [3] External clock on NFC_CLK_XTAL1 must be LOW. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

14 Thermal characteristics

52.0 K/W

Table 31. Thermal characteristics VFBGA64 package

28.0 K/W

Table 32. Thermal characteristics HVQFN40 package Table 33. Junction Temperature Table 34. Thermal Shutdown Temperature PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

15 Characteristics

15.1 Current consumption characteristics

Table 35. Current consumption characteristics for operating ambient temperature range [1] Refer to Section 11.1.2 for the description of the power modes. [2] For transmitter current tuned at 210 mA unloaded.

15.2 Functional block electrical characteristics

15.2.1 Reset via VEN

Table 36. Reset timing

15.2.2 Power-up timings

Table 37. Power-up timings

15.2.3 Power-down timings

15.2.4 Download mode timings

Table 39. Download mode timings

15.2.5 I2C-bus timings

Here below are timings and frequency specifications. Figure 33. I2C-bus timings Table 40. High-speed mode I2C-bus timings specification Table 41. Fast mode I2C-bus timings specification PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 41. Fast mode I2C-bus timings specification...continued

15.2.6 SPI-bus timings

Figure 34. SPI-bus timing diagram Table 42. SPI-bus timings specification PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

15.2.7 Active load modulation phase

Table 43. Active load modulation phase error

15.3 Pin characteristics

15.3.1 NFC_CLK_XTAL1 and XTAL2 pins characteristics

Table 44. Input clock characteristics on NFC_CLK_XTAL1 when using PLL Table 45. Pin characteristics for NFC_CLK_XTAL1 when PLL input Table 46. Pin characteristics for 27.12 MHz crystal oscillator Table 47. PLL accuracy

15.3.2 VEN input pin characteristics

Table 48. VEN input pin characteristics...continued

15.3.3 Output pin characteristics for IRQ, CLK_REQ

Figure 35. Output timing measurement condition Table 49. Output pin characteristics for IRQ, CLK_REQ [2] Pull-down resistance is activated in HPD state. [3] Pull-down resistance can be activated by firmware in Standby state. [4] Pull-down resistance can be activated by firmware in Active state.

15.3.4 Output pin characteristics for TX_PWR_REQ

Table 50. Output pin characteristics for TX_PWR_REQ [1] TX_PWR_REQ active driving is only possible when VDD(PAD) is present. When VDD(PAD) is not present, only pull-up or pull-down resistors can be enabled. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

[3] Unless disable by firmware, pull-down resistance is always activated. [4] Can be enabled by firmware.

15.3.5 Output pin characteristics for DCDC_EN

Table 51. Output pin characteristics for DCDC_EN [1] DCDC_EN active driving is only possible when VDD(PAD) is present. When VDD(PAD) is not present, only pull-up or pull-down resistors can be enabled.

15.3.6 Input pin characteristics for DWL_REQ, WKUP_REQ

Table 52. Input pin characteristics for DWL_REQ, WKUP_REQ

15.3.7 Input pin characteristics for RXN and RXP

Table 53. Input pin characteristics for RXN and RXP...continued

15.3.8 ANT1 and ANT2 pin characteristics

Table 54. Electrical characteristics of ANT1 and ANT2

15.3.9 VDD(HF) and VDDD pins characteristics

15.3.10 Output pin characteristics for TX1 and TX2

Table 56. Output pin characteristics for TX1 and TX2 Table 57. Output resistance for TX1 and TX2

15.3.11 Input pin characteristics for HIF1 (used as SPI-bus NSS, used as I2C-bus address 0),

Table 58. Input pin characteristics for HIF1 (used as SPI-bus NSS, used as I2C-bus address 0), HIF2 (used as SPI- [1] Unless disable by firmware, extra pull-up resistance is always activated.

15.3.12 Pin characteristics for HIF3 (used as I2C-bus SDA) and HIF4 (used as I2C-bus SCL)

Table 59. Pin characteristics for HIF3 (used as I2C-bus SDA) and HIF4 (used as I2C-bus SCL) PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 59. Pin characteristics for HIF3 (used as I2C-bus SDA) and HIF4 (used as I2C-bus SCL)...continued [1] Only for pin HIF3 (I2C-bus SDA), HIF4 (I2C-bus SCL) is only used as input.

15.3.13 Pin characteristics for HIF3 (used as SPI-bus MISO)

Plastic or metal protrusions of 0.075 mm maximum per side are not included.

NXP Semiconductors PN7160_PN7161 Near Field Communication (NFC) controller

18 Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

18.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
Solder bath specifications, including temperature and impurities

18.4 Reflow soldering

Key characteristics in reflow soldering are:

Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 38) than a SnPb process, thus reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4.0 — 5 September 2024 Document feedback

Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 61 and Table 62 Package reflow temperature (°C) Volume (mm3) Package thickness (mm) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220

Table 61. SnPb eutectic process (from J-STD-020C) Table 62. Lead-free process (from J-STD-020C) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 38. Figure 38. Temperature profiles for large and small components PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

19 Abbreviations

NXP Semiconductors PN7160_PN7161 Near Field Communication (NFC) controller

20 References

[1] NFC Forum Device Requirements V2.0 [2] NFC Controller Interface (NCI) Technical Specification V2.0 [3] ISO/IEC 14443 parts 2: 2001 COR 1 2007 (01/11/2007), part 3: 2001 COR 1 2006 (01/09/2006) and part 4: 2nd edition 2008 (15/07/2008) [4] I2C Specification, UM10204 rev4 (13/02/2012) [5] SPI Motorola de-facto standard described in Motorola 68HC11 data sheet [6] UM11577 PN7161 NFC controller user manual [7] AN12988 PN7160 hardware design guide [8] AN13219 PN7160 antenna design and matching guide [9] ISO/IEC 18092 (NFCIP-1) edition, 15/03/2013. This is similar to Ecma 340. [10] ISO/IEC15693 part 2: 2nd edition (15/12/2006), part 3: 1st edition (01/04/2001) [11] ISO/IEC 21481 (NFCIP-2) edition, 01/07/2012. This is similar to Ecma 352. [12] ETSI HCI TS 102 622; UICC - Contactless Front-end (CLF) Interface; Host Controller Interface (HCI) (Release 12) [13] Apple Enhanced Contactless Polling Specification: Version 1.1. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4.0 — 5 September 2024 Document feedback

Section 6.1 "Firmware version and model ID retrieval": added PN7160_PN7161 v.3.9 08 March 2023 Product data sheet PN7160_PN7161 v.3.8 Modifications: • FeliCa card mode removed
Updated the terms "Master/Slave" to "Controller/Target" to align with the recommendation of the NXP - I2C standards organization. PN7160_PN7161 v.3.8 14 December 2022 Product data sheet PN7160_PN7161 v.3.7 Modifications: • Section 5 "Quick reference data" and Section 13 "Recommended operating conditions": Tamb updated to -30°C PN7160_PN7161 v.3.7 07 December 2022 Product data sheet PN7160_PN7161 v.3.6 Modifications: • Section 6 "Firmware versions" and Section 7 "Ordering information": updated PN7160_PN7161 v.3.6 05 September 2022 Product data sheet PN7160_PN7161 v.3.5 Modifications: • Figure 6: Description of Pin 37 updated PN7160_PN7161 v.3.5 19 August 2022 Product data sheet PN7160_PN7161 v.3.4 Modifications: • Added information about DCDC_EN pin as an alternative to the pin TX_PWR_REQ, see Section 11.4.3.4 "TXLDO: configuration"
Clarified voltage level of pin VDDD, see Table 55 PN7160_PN7161 v.3.4 04 August 2022 Product data sheet PN7160_PN7161 v.3.3 Modifications: • Functional description SPI interface: Setting of CPHA and CPOL are fixed during production and cannot be changed by customer. PN7160_PN7161 v.3.3 17 February 2022 Product data sheet PN7160_PN7161 v.3.2 Modifications: • Section 7 "Ordering information": Table 3 and Table 4 added
Section 6 "Firmware versions": added PN7160_PN7161 v.3.2 30 September 2021 Product data sheet PN7160_PN7161 v.3.1 Modifications: • Clarified pin naming TVDD vs VDD(TX) PN7160_PN7161 v.3.1 13 September 2021 Product data sheet PN7160_PN7161 v.3.0 Modifications: • Security status changed into "Company public" PN7160_PN7161 v.3.0 19 August 2021 Product data sheet PN7160_PN7161 v.2.0 Modifications: • Data sheet status changed into "Product data sheet"
Security status changed into "Company restricted" PN7160_PN7161 v.2.0 09 July 2021 Preliminary data sheet PN7160 v.1.0 Modifications: • PN7161 included
Section 14 "Thermal characteristics": updated
Some figures updated PN7160 v.1.0 08 March 2021 Objective data sheet -
Initial version

NXP Semiconductors PN7160_PN7161 Near Field Communication (NFC) controller Legal information Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL https://www.nxp.com. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at https://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4.0 — 5 September 2024 Document feedback

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NXP Semiconductors PN7160_PN7161 Near Field Communication (NFC) controller Tables Tab. 21. Communication overview for NFC Forum Tab. 22. Communication overview for NFC Forum T3T R/W mode, FeliCa communication Tab. 23. Communication overview for NFC Forum Tab. 24. Communication overview for NFC Forum Tab. 27. Overview for NFC Forum T4T, ISO/IEC Tab. 28. Overview for NFC Forum T4T, ISO/IEC Tab. 35. Current consumption characteristics for Tab. 40. High-speed mode I2C-bus timings Tab. 44. Input clock characteristics on NFC_CLK_ Tab. 45. Pin characteristics for NFC_CLK_XTAL1 Tab. 46. Pin characteristics for 27.12 MHz crystal Tab. 49. Output pin characteristics for IRQ, CLK_ Tab. 50. Output pin characteristics for TX_PWR_ Tab. 52. Input pin characteristics for DWL_REQ, Tab. 54. Electrical characteristics of ANT1 and Tab. 55. Electrical characteristics of VDD(HF) and Tab. 58. Input pin characteristics for HIF1 (used as SPI-bus NSS, used as I2C-bus address 0), HIF2 (used as SPI-bus MOSI, used as I2C- bus address 1), HIF4 (used as SPI-bus Tab. 59. Pin characteristics for HIF3 (used as I2C- bus SDA) and HIF4 (used as I2C-bus SCL) .... 52 Tab. 60. Pin characteristics for HIF3 (used as SPI- PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4.0 — 5 September 2024 Document feedback

NXP Semiconductors PN7160_PN7161 Near Field Communication (NFC) controller Figures Fig. 3. PN7160 Package marking HVQFN40 (top Fig. 15. VDD(TX) behavior when supplied from Fig. 16. VDD(TX) behavior when PN7160 is in Fig. 18. VDD(TX) behavior when PN7160 is supply Fig. 22. VDD(PAD) and VBAT are set up in the Fig. 23. VDD(PAD) is set up or cut-off after PN7160 Fig. 26. R/W mode for NFC Forum T1T, T2T and Fig. 27. R/W mode for NFC Forum T3T Fig. 28. R/W mode for NFC forumT4T type B Fig. 29. R/W mode for NFC Forum T5T Fig. 37. Package outline, HVQFN40, SOT618-1, Fig. 38. Temperature profiles for large and small PN7160_PN7161 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4.0 — 5 September 2024 Document feedback

NXP Semiconductors PN7160_PN7161 Near Field Communication (NFC) controller

15.3.11 Input pin characteristics for HIF1 (used as

SPI-bus NSS, used as I2C-bus address 0), HIF2 (used as SPI-bus MOSI, used as I2C- bus address 1), HIF4 (used as SPI-bus

15.3.12 Pin characteristics for HIF3 (used as I2C-

bus SDA) and HIF4 (used as I2C-bus SCL) .... 52

15.3.13 Pin characteristics for HIF3 (used as SPI-

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2024 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Document feedback Date of release: 5 September 2024 Document identifier: PN7160_PN7161

Product Information

PN7160 specifications and overview.

Summary

Near Field Communication (NFC) controller Rev. 4.0 - 5 September 2024

Description

Near Field Communication (NFC) controller Rev. 4.0 - 5 September 2024

Source title PN7160 Datasheet(PDF) - NXP Semiconductors

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