PMP5501G NEXPERIA | Alldatasheet

Document overview

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Technical content

1.1 General description

1.2 Features

1.3 Applications

1.4 Quick reference data

Table 1. Product overview Table 2. Quick reference data

PMP5501V_G_Y_3 © NXP B.V. 2009. All rights reserved. [1] The smaller of the two values is taken as the numerator. [2] The smaller of the two values is subtracted from the larger value. Table 2. Quick reference data …continued Table 3. Pinning Table 4. Ordering information

PMP5501V_G_Y_3 © NXP B.V. 2009. All rights reserved. [2] Reflow soldering is the only recommended soldering method. Table 5. Marking codes Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).

PMP5501V_G_Y_3 © NXP B.V. 2009. All rights reserved. [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [2] Reflow soldering is the only recommended soldering method. Table 7. Thermal characteristics Table 8. Characteristics Tamb =2 5°C unless otherwise specified.

PMP5501V_G_Y_3 © NXP B.V. 2009. All rights reserved. [1] VBEsat decreases by about 1.7 mV/K with increasing temperature. [2] VBE decreases by about 2 mV/K with increasing temperature. [3] The smaller of the two values is taken as the numerator. [4] The smaller of the two values is subtracted from the larger value. Table 8. Characteristics …continued Tamb =2 5°C unless otherwise specified.

PMP5501V_G_Y_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 28 August 2009 6 of 14 NXP Semiconductors PMP5501V; PMP5501G; PMP5501Y PNP/PNP matched double transistors Tamb =2 5°CV CE = −5V (1) Tamb = 100°C (2) Tamb =2 5°C (3) Tamb = −55 °C Fig 1. Collector current as a function of collector-emitter voltage; typical values Fig 2. DC current gain as a function of collector current; typical values IC /IB =2 0 (1) Tamb = −55 °C (2) Tamb =2 5°C (3) Tamb = 100°C IC /IB =2 0 (1) Tamb = 100°C (2) Tamb =2 5°C (3) Tamb = −55 °C Fig 3. Base-emitter saturation voltage as a function of collector current; typical values Fig 4. Collector-emitter saturation voltage as a function of collector current; typical values 006aaa540 VCE (V) −0.08 −0.12 −0.04 −0.16 −0.20 IC (A) −0.25 IB (mA) = −2.5 −0.5 −0.75 −1.0 −1.25 −1.5 −1.75 −2.0 −2.25 006aaa541 200 400 600 h FE IC (mA) (1) (2) (3) 006aaa542 IC (mA) -0.5 -0.9 -1.3 -0.3 -0.7 -1.1 VBEsat (V) -0.1 (1) (2) (3) 006aaa543 -10-1 -10 VCEsat (V) -10-2 IC (mA) (1) (2) (3)

PMP5501V_G_Y_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 28 August 2009 7 of 14 NXP Semiconductors PMP5501V; PMP5501G; PMP5501Y PNP/PNP matched double transistors VCE = −5 V; Tamb =2 5°CV CE = −5 V; Tamb =2 5°C Fig 5. Base-emitter voltage as a function of collector current; typical values Fig 6. Transition frequency as a function of collector current; typical values f = 1 MHz; Tamb =2 5°C f = 1 MHz; T amb =2 5°C Fig 7. Collector capacitance as a function of collector-base voltage; typical values Fig 8. Emitter capacitance as a function of emitter-base voltage; typical values 006aaa544 −0.6 −0.8 VBE (V) −0.4 IC (mA) IC (mA) −1 −102−10 006aaa545 102 103 fT (MHz) VCB (V) 006aaa546 C c (pF) 006aaa547 VEB (V) 0 −6−4−2 C e (pF)

PMP5501V_G_Y_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 28 August 2009 8 of 14 NXP Semiconductors PMP5501V; PMP5501G; PMP5501Y PNP/PNP matched double transistors 8. Application information 9. Package outline Fig 9. Current mirror Fig 10. Differential amplifier 006aaa524 VCC lout TR2TR1 006aaa526 IN2IN1 TR2TR1 OUT2 OUT1 Fig 11. Package outline SOT666 Fig 12. Package outline SOT353 (SC-88A) Fig 13. Package outline SOT363 (SC-88) Dimensions in mm 04-11-08 1.7 1.5 1.7 1.5 1.3 1.1 0.18 0.08 0.27 0.170.5 pin 1 index 123 456 0.6 0.5 0.3 0.1 04-11-16Dimensions in mm 0.25 0.10 0.3 0.2 1.3 0.65 2.2 2.0 1.35 1.15 2.2 1.8 1.1 0.8 0.45 0.15 13 2 06-03-16Dimensions in mm 0.25 0.10 0.3 0.2 pin 1 index 1.3 0.65 2.2 2.0 1.35 1.15 2.2 1.8 1.1 0.8 0.45 0.15 13 2 465

PMP5501V_G_Y_3 © NXP B.V. 2009. All rights reserved. [1] For further information and the availability of packing methods, seeSection14. Table 9. Packing methods Reflow soldering is the only recommended soldering method.

PMP5501V_G_Y_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 28 August 2009 10 of 14 NXP Semiconductors PMP5501V; PMP5501G; PMP5501Y PNP/PNP matched double transistors Dimensions in mm Fig 15. Reflow soldering footprint SOT353 (SC-88A) Dimensions in mm Fig 16. Wave soldering footprint SOT353 (SC-88A) msa366 1.20 2.40 0.50 (4×) 0.40 0.90 2.10 0.50 (4×) 0.60 (1×) 2.35 2.65 solder lands solder resist occupied area solder paste sot353_fw 1.3 1.3 4.5 4.9 1.5 1.5 2.5 2.25 0.85 0.85 1.225 1.225 solder lands solder resist occupied area preferred transport direction during soldering Dimensions in mm

PMP5501V_G_Y_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 28 August 2009 11 of 14 NXP Semiconductors PMP5501V; PMP5501G; PMP5501Y PNP/PNP matched double transistors Fig 17. Reflow soldering footprint SOT363 (SC-88) Fig 18. Wave soldering footprint SOT363 (SC-88) solder lands solder resist occupied area solder paste sot363_fr 2.65 2.35 0.4 (2·) 0.6 (2·) 0.5 (4·) 0.5 (4·) 0.6 (4·) 0.6 (4·) 1.5 1.8 Dimensions in mm sot363_fw solder lands solder resist occupied area preferred transport direction during soldering 5.3 1.3 1.3 1.5 0.3 1.5 4.5 2.45 2.5 Dimensions in mm

PMP5501V_G_Y_3 © NXP B.V. 2009. All rights reserved. Table 10. Revision history

  • This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content.
  • Figure 14 “Reflow soldering footprint SOT666”: updated
  • Figure 16 “Wave soldering footprint SOT353 (SC-88A)”: updated
  • Figure 17 “Reflow soldering footprint SOT363 (SC-88)”: updated
  • Figure 18 “Wave soldering footprint SOT363 (SC-88)”: updated PMP5501V_G_Y_2 20060919 Product data sheet - PMP5501G_Y_1 PMP5501G_Y_1 20060221 Product data sheet - -

PMP5501V_G_Y_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 28 August 2009 13 of 14 NXP Semiconductors PMP5501V; PMP5501G; PMP5501Y PNP/PNP matched double transistors 13. Legal information

13.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

13.2 Definitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

13.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values —Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control —This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data —The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit:http://www.nxp.com For sales office addresses, please send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

NXP Semiconductors PMP5501V; PMP5501G; PMP5501Y PNP/PNP matched double transistors © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 August 2009 Document identifier: PMP5501V_G_Y_3 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents