PMN40LN

PMN40LN NEXPERIA | Alldatasheet

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Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. use http://www.nexperia.com salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e -mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia

TrenchMOS™ logic level FET Rev. 01 — 13 November 2002 Product dataM3D302 1. Description N-channel logic level field-effect power transistor in a plastic package using TrenchMOS™ technology. Product availability: PMN40LN in SOT457 (TSOP6). 2. Features ■ TrenchMOS™ technology ■ Logic level compatible ■ Surface mount package. 3. Applications ■ Battery management ■ High speed switch ■ Low power DC to DC converter. 4. Pinning information Table 1: Pinning - SOT457 (TSOP6), simplified outline and symbol Pin Description Simplified outline Symbol 1,2,5,6 drain (d) SOT457 (TSOP6) 3 gate (g) 4 source (s) MBK092Top view 13 2 456 s d g MBB076

Philips Semiconductors PMN40LN TrenchMOS™ logic level FET Product data Rev. 01 — 13 November 2002 2 of 12 9397 750 10192 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 5. Quick reference data 6. Limiting values Table 2: Quick reference data Symbol Parameter Conditions Typ Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj≤ 150 °C - 30 V ID drain current (DC) T sp =2 5°C; VGS =1 0V - 5 . 4 A Ptot total power dissipation T sp =2 5°C - 1.75 W Tj junction temperature - 150 °C R DSon drain-source on-state resistance VGS = 10 V; ID = 2.5 A; Tj =2 5°C 3 23 8m Ω VGS = 4.5 V; ID = 2 A; Tj =2 5°C 4 04 5m Ω Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj≤ 150 °C - 30 V VDGR drain-gate voltage (DC) 25 °C ≤ Tj≤ 150 °C; RGS =2 0kΩ -3 0 V VGS gate-source voltage (DC) - ±15 V ID drain current (DC) T sp =2 5°C; VGS =1 0V ;Figure 2 and3 - 5.4 A Tsp =7 0°C; VGS =1 0V ;Figure 2 -4 A IDM peak drain current T sp =2 5°C; pulsed; tp ≤ 10 µs;Figure 3 - 21.6 A Ptot total power dissipation T sp =2 5°C; Figure 1 - 1.75 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C Source-drain diode I S source (diode forward) current (DC) Tsp =2 5°C - 1.45 A ISM peak source (diode forward) current Tsp =2 5°C; pulsed; tp ≤ 10 µs - 5.8 A

Philips Semiconductors PMN40LN TrenchMOS™ logic level FET Product data Rev. 01 — 13 November 2002 3 of 12 9397 750 10192 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Fig 1. Normalized total power dissipation as a function of solder point temperature. Fig 2. Normalized continuous drain current as a function of solder point temperature. Tsp =2 5°C; VGS = 10 V; IDM is single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 03aa17 120 0 50 100 150 200 (%) Tsp (°C) Pder 03aa25 120 0 50 100 150 200 Tsp (°C) Ider (%) P der P tot P tot 25 C°() ID I D2 5C°() 03aj86 10-2 10-1 102 10-1 1 10 10 2 VDS (V) ID (A) DC 10 ms Limit RDSon = VDS / ID 1 ms tp = 10 µ s 100 ms 100 µ s

Philips Semiconductors PMN40LN TrenchMOS™ logic level FET Product data Rev. 01 — 13 November 2002 4 of 12 9397 750 10192 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 7. Thermal characteristics

7.1 Transient thermal impedance

Table 4: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit R th(j-sp) thermal resistance from junction to solder point mounted on a metal clad board;Figure 4 --7 0 K / W Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration. 03aj85 10-1 102 10-4 10-3 10-2 10-1 1 10 10 2 tp (s) Zth(j-sp) (K/W) single pulse δ = 0.5 0.2 0.1 0.05 0.02 tp tp T P t Tδ =

Philips Semiconductors PMN40LN TrenchMOS™ logic level FET Product data Rev. 01 — 13 November 2002 5 of 12 9397 750 10192 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 8. Characteristics Table 5: Characteristics Tj=2 5°C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V (BR)DSS drain-source breakdown voltage ID = 0.25 mA; VGS =0V Tj=2 5°C 3 0 --V Tj= −55 °C 2 7 --V VGS(th) gate-source threshold voltage ID = 1 mA; VDS =V GS ;Figure 9 Tj=2 5°C 1 1.5 2 V IDSS drain-source leakage current V DS =2 4V ; VGS =0V Tj=2 5°C - 0.05 1 µA Tj= 150°C - - 500 µA IGSS gate-source leakage current V GS = ±15 V; VDS = 0 V - 10 100 nA R DSon drain-source on-state resistance VGS = 4.5 V; ID =2A ;Figure 7 and8 Tj=2 5°C - 40 45 m Ω Tj= 150°C - 64 72 m Ω VGS = 10 V; ID = 2.5 A;Figure 7 Tj=2 5°C - 32 38 m Ω Dynamic characteristics Q g(tot) total gate charge I D = 5 A; VDD =1 5V ; VGS =1 0V ;Figure 13 - 13.8 - nC Q gs gate-source charge - 1.8 - nC Q gd gate-drain (Miller) charge - 2.4 - nC C iss input capacitance V GS =0V ; VDS = 25 V; f = 1 MHz;Figure 11 - 555 - pF C oss output capacitance - 105 - pF C rss reverse transfer capacitance - 70 - pF td(on) turn-on delay time VDD =1 5V ; RL =1 2Ω ; VGS =1 0V ;RG =6 Ω -5 -n s tr rise time -7 -n s td(off) turn-off delay time - 19 - ns tf fall time -8 -n s Source-drain diode V SD source-drain (diode forward) voltage IS = 1.7 A; VGS =0V ;Figure 12 - 0.8 1.2 V

Philips Semiconductors PMN40LN TrenchMOS™ logic level FET Product data Rev. 01 — 13 November 2002 6 of 12 9397 750 10192 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Tj=2 5°CT j=2 5°C and 150°C; VDS > ID xR DSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. Tj=2 5°C Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. 03aj87 0 0.2 0.4 0.6 0.8 1 VDS (V) ID (A) 10 V 2.6 V

4.5 V5 V

VGS = 2.4 V 3.6 V 4 V 3.2 V 3 V 2.8 V 03aj89 01234 VGS (V) ID (A) VDS > ID x RDSon Tj = 150 °C 25 °C 03aj88 0 5 10 15 20 ID (A) R DSon (mΩ ) Tj = 25 °C VGS = 3.2 V 4 V 4.5 V 5 V 10 V 3.6 V 03af18 0.5 1.5 -60 0 60 120 180 Tj (°C) a a R DSon R DSon 25 C°()

Philips Semiconductors PMN40LN TrenchMOS™ logic level FET Product data Rev. 01 — 13 November 2002 7 of 12 9397 750 10192 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. ID = 1 mA; VDS =V GS Tj=2 5°C; VDS =5V Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 03aa33 0.5 1.5 2.5 -60 0 60 120 180 Tj (°C) VGS(th) (V) max typ min 03aa36 10-6 10-5 10-4 10-3 10-2 10-1 0123 VGS (V) ID (A) maxtypmin 03aj91 102 103 10-1 1 10 10 2 VDS (V) C (pF) C iss C oss C rss

Philips Semiconductors PMN40LN TrenchMOS™ logic level FET Product data Rev. 01 — 13 November 2002 8 of 12 9397 750 10192 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Tj=2 5°C and 150°C; VGS =0V I D = 5 A; VDD =1 5V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of gate charge; typical values. 03aj90 00 . 511 . 5 VSD (V) IS (A) Tj = 25 °C150 °C VGS = 0 V 03aj92 0 4 8 12 16 Q G (nC) VGS (V) ID = 5 A Tj = 25 °C VDD = 15 V

Philips Semiconductors PMN40LN TrenchMOS™ logic level FET Product data Rev. 01 — 13 November 2002 9 of 12 9397 750 10192 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9. Package outline Fig 14. SOT457 (TSOP6). REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT457 SC-74 wB Mbp D e pin 1 index A Lp Q detail X H E E v M A AB y 0 1 2 mm scale c X 13 2 456 Plastic surface mounted package; 6 leads SOT457 UNIT A 1 bp cD E H E Lp Qy wv mm 0.1 0.013 0.40 0.25 3.1 2.7 0.26 0.10 1.7 1.3 e 0.95 3.0 2.5 0.2 0.10.2 DIMENSIONS (mm are the original dimensions) 0.6 0.2 0.33 0.23 A 1.1 0.9 97-02-28 01-05-04

Philips Semiconductors PMN40LN TrenchMOS™ logic level FET Product data Rev. 01 — 13 November 2002 10 of 12 9397 750 10192 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 10. Revision history 11. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. Table 6: Revision history Rev Date CPCN Description 01 20021113 - Product data.

Philips Semiconductors PMN40LN TrenchMOS™ logic level FET © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 13 November 2002 11 of 12 9397 750 10192 Philips Semiconductors PMN40LN TrenchMOS™ logic level FET © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 13 November 2002 11 of 12 Contact information For additional information, please visithttp://www.semiconductors.philips.com. 12. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 13. Definitions Short-form specification —The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition —Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information —Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 14. Disclaimers Life support —These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes —Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).

© Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 13 November 2002 Document order number: 9397 750 10192

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Philips Semiconductors PMN40LN TrenchMOS™ logic level FET