PMB2349

PMB2349 INFINEON | Alldatasheet

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Optimized RF/IF Dual PLL Frequency Synthesizer PMB 2349 Version 1.0 Specification May 2000 Confidential TARGET SPECIFICATION

Edition 03.99 Published by Infineon Technologies AG i. Gr., SC, Balanstraße 73,

81541 München

All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits im- plemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components 1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life- support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. ABM ® , AOP® , ARCOFI® , ARCOFI® -BA, ARCOFI® -SP, DigiTape® , EPIC® -1, EPIC® -S, ELIC® , FALC® 54, FALC® 56, FALC® -E1, FALC® -LH, IDEC® , IOM® , IOM ® -1, IOM® -2, IPAT® -2, ISAC® -P, ISAC® -S, ISAC® -S TE, ISAC® -P TE, ITAC® , IWE® , MUSAC ® -A, OCTAT® -P, QUAT® -S, SICAT® , SICOFI® , SICOFI® - 2, SICOFI® -4, SICOFI® -4µC, SLICOFI® are registered trademarks of Infineon Technologies AG. ACE ™ , ASM™ , ASP™ , POTSWIRE ™ , QuadFALC™ , SCOUT ™ are trademarks of Infineon Technologies AG. CONFIDENTIAL Revision History: Current Version: May 2000 Previous Version:Data Sheet Page (in previous Version) Page (in current Version) Subjects (major changes since last revision)

Product InfoWireless Components Confidential Specification, May 2000 Package P-VQFN-24-3 PMB 2349 TARGET SPECIFICATION Product Info General Description The PMB 2349 is a RF/IF Dual-PLL frequency synthesizer implemented in Infineon’s high speed BiCMOS tech- nology B6HFC. The device contains two PLLs with integrated prescalers especially designed for use in battery powered radio equipment and mobile telephones. Primary applications are single- and dual-band digital cellular systems e.g. GSM, PCN (DCS 1800) and PCS systems.

Features

/G01 Operation range 2.7 to 5.0 V /G01 Ultra low phase noise /G01 Ultra low spurious /G01 Faster lock-in times /G01 New bipolar power modes /G01 New programmable Reference Amplifier /G01 External or internal reference cur- rent setting for PD outputs /G01 Low operating current consumption /G01 Programmable power down modes /G01 High input sensitivity and high input frequencies: PLL1 (RF): 2.8 GHz PLL2 (IF): 600 MHz /G01 Programmable dual modulus prescaler divide ratio: PLL1: 1:64/65 or 1:32/33 PLL2: 16/17 or 1:8/9 Dividing ratios: A counters: PLL1: 0 to 63 PLL2: 0 to 15 N counters: PLL1: 3 to 16,383 PLL2: 3 to 16,383 R counters 3 to 16,383 for PLL1 and PLL2 /G01 Fast phase detectors and charge pump outputs without dead zone /G01 Switchable polarity and program- mable phase detector currents /G01 Fast serial 3-wire bus interface with low threshold voltage Schmitt-Trig- ger inputs for interfacing with low voltage baseband circuits /G01 Two data registers in PLL2 for fast IF band switching /G01 A programmable output port for lock detect or general porpose (VCO switch etc.).

Ordering Information

Type Ordering Code Package PMB 2349 P-VQFN-24

1 Table of Contents

2 Product Description

Specification, May 2000

2.1 Overview

The PMB 2349 is a RF/IF Dual-PLL frequency synthesizer implemented in Infi- neon’s high speed BiCMOS technology B6HFC. The device contains two PLLs with integrated prescalers especially designed for use in battery powered radio equipment and mobile telephones. Primary applications are single- and dual- band digital cellular systems e.g. GSM, PCN (DCS 1800) and PCS systems.

2.2 Features

/G01 Operation range 2.7 to 5.0 V /G01 Ultra low phase noise /G01 Ultra low spurious /G01 Faster lock-in times /G01 New bipolar power modes /G01 New programmable Reference Amplifier /G01 External or internal reference current setting for PD outputs /G01 Low operating current consumption /G01 Programmable power down modes /G01 High input sensitivity and high input frequencies: PLL1 (RF): 2.8 GHz, PLL2 (IF): 600 MHz /G01 Programmable dual modulus prescaler divide ratio: PLL1: 1:64/65 or 1:32/33 PLL2: 16/17 or 1:8/9 Dividing ratios: A counters: PLL1: 0 to 63 PLL2: 0 to 15 N counters: PLL1: 3 to 16,383 PLL2: 3 to 16,383 R counters 3 to 16,383 for PLL1 and PLL2 /G01 Fast phase detectors and charge pump outputs without dead zone /G01 Switchable polarity and programmable phase detector currents /G01 Fast serial 3-wire bus interface with low threshold voltage Schmitt-Trigger inputs for interfacing with low voltage baseband circuits /G01 Two data registers in PLL2 for fast IF band switching /G01 A programmable output port for lock detect or general porpose (VCO switch etc.).

Specification, May 2000

2.3 Package Outlines

VQFN-24-3.eps Figure 2-1 P-VQFN-24

3 Functional Description

Specification, May 2000

3.1 Pin Configuration

Pin_config.wmf Figure 3-1 Pin Configuration PMB 2349 CP2 VPD2 BACK VCC2 VCC1 NC Rext MFO CLK BACK DA EN GND1 IF IFX GND2 RI NC VPD1 CP1 GND1 RF1 RFX GND2

Specification, May 2000

3.2 Pin Definition and Function

Table 3-1 Pin Definition and Function Pin No. Symbol Equivalent I/O-Schematic Function

23 VCC1 Positive supply voltage

1 VPD1 Positive supply voltage

2 CP1 PLL1 charge pump output

3 GND1 Ground for CMOS cir-

PLL1. AC coupling must be set up. RF frequency input (inverted) RF input with highly sen- sitive preampifier for PLL1. AC coupling must be set up GND2 Ground for bipolar cir- cuitry PD Output Equivalent ESD *2pF CP1 RF/IF RFx/IFx RF and IF Input Equivalent

Specification, May 2000 Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Function

7 EN 3-Wire bus input:

Enable input of the serial control interface with Schmitt-Trigger input stage. When EN=H the input signals CLK and DA are disabled. When EN=L the serial control interface is enabled. The received data are transferred to the registers with the positive edge of the EN-signal. DA 3-Wire bus input: Data Data input of the serial control interface with Schmitt-Trigger input stage.The serial data are read into the internal shift register with the positive edge of CLK. CLK 3-Wire bus input: Clock Clock input of the serial control interface with Schmitt-Trigger input stage MFO Lock detector output Unipolar output of the phase detector in the form of a pulse-width modulated signal. In the locked state the output signal is at H-level. In standby mode the output is resistive. For test purpose the push pull output fo is enabled. ESD *2pF 560 Ω 75k Ω Serial Control Input Equivalent CLK ESD *2pF 560 Ω 75k Ω Serial Control Input Equivalent DA ESD *2pF 560 Ω 75k Ω Serial Control Input Equivalent EN ESD *2pF LD/fo LD as Lock Detector

Specification, May 2000 Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Function

12 Rext CP & Prescaler refer-

External resistor for CP & Prescaler reference cur- rent setting. RI Reference frequency input Input with highly sensi- tive preamplifier. With small input signals AC coupling must be set up, where DC coupling can be used for large input signals. GND2 Ground for bipolar cir- cuitry IFX IF IF frequency input (inverted) IF input with highly sensi- tive preampifier for PLL2. AC coupling must be set up. IF frequency input IF input with highly sensi- tive preampifier for PLL2. AC coupling must be set up. GND1 Ground for CMOS cir- cuitry OSW Output Equivalent ESD 2pF Rext 560 Ω ESD 2pF STDBY /STDBY RI 500K Ω RI Input Equivalent RF/IF RFx/IFx RF and IF Input Equivalent

Specification, May 2000 Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Function

19 CP2 Phase detector tristate

20 VPD2 Positive supply voltage

for charge pump 2.

22 VCC2 Positive supply voltage

9+21 BACK Backplane - BIPOLAR ground recommended 13+24 NC not connected PD Output Equivalent ESD *2pF CP2

Specification, May 2000

3.3 Functional Block Diagram

Funct_block.wmf Figure 3-2 Functional Block Diagram

4 Bit

Data Reg. 2 Data Reg. 1

14 Bit

Data Reg. 2 Data Reg. 1 Modulus Control Shadow Reg. Data Reg.

6 Bit

Data Reg. Shadow Reg. Data Reg. Modulus Control Phase Detector Shift Register LD fo VCC1 PLL1 (RF) PLL2 (IF) GND2 VPD1 GND1 PD1 RF CLK EN RFX DA VCC2 GND2 VPD2 GND1 PD2 IF LD RI IFX REXT Serial Control Logic Phase Detector Shadow Reg. Mod1 Mod1 Data Reg.

Specification, May 2000

3.4 Circuit Description

3.4.1 General Description

The PMB 2349 consists of two fully programmable PLLs, one for the RF and one for the IF frequency range. Each PLL contains a high frequency dual mod- ulus prescaler, an A- and a N-counter with dual modulus control logic, a refer- ence- (R-) counter, and a phase detector with charge pump output. The two synthesizers are controlled via the common serial 3-wire interface. The reference frequency is applied at the common RI-input and divided by the R-counter of each PLL. Its maximum value is 45 MHz. The RF and IF input fre- quencies will be divided by the corresponding prescalers with a programmable 32/32 or 64/65 (RF) and 8/9 or 16/17 (IF) divide ratio and the following program- mable A/N-counters. The maximum RF frequency value is 2.8 GHz and 600 MHz for the IF frequency. The phase and frequency detectors with the charge pumps have a linear oper- ating range without a dead zone for very small phase deviations. The multifunctional output port LD/MFO can be programmed as lock detector and general purpose output.

3.4.2 Programming

Programming of the IC is done via the serial data interface. The content of the bus telegram (serial data format) is assigned to the functional units according to the address. The most significant bit (MSB) of the serial data formats is shifted first. The short control data format allows a fast PD-current change. The long control data format allows the programming of asynchronous or syn- chronous data acquisition of PLL1 (RF), 4 different PD-output current modes for the PLL1 and 1 PD-output current modes for PLL2, polarity setting of the PD- output signals, 2 standby modes, charge pump pulse width and the prescaler divide ratio. The A/N-counter data format of PLL1 contains the A/N-counter value.. The data format of PLL2 comprise the counter values as well. The R-counter data format contains the R-counter values. The PLL1 (RF) of PMB 2349 offers the possibility of synchronous counter and charge pump current programming to avoid phase errors at the phase detector when R- and A-/N-counter are programmed one after another or the charge pump current is altered.

Specification, May 2000 Asynchronous Mode: The serial data is written directly to the data registers of the addressed counter with the Enable pulse. As each counter is loading the new starting value after it is decremented to „zero“, the counters changes therefore their counter values asynchronously to the others. Synchronous Mode (only for RF): In this mode counter programming is controlled by the R- and N-counters. The serial data (exception: higher part of long control data format) is first written with the Enable pulse to the corresponding shadow registers. From there the values for R-counter, A-/N-counter and charge pump current values of short/long con- trol data format are loaded into the corresponding data register when the N- counter reaches „zero+1“. Therefore the change of all counter states is syn- chronised to the reloading of the N-counter to avoid additional phase error caused by the programming. The transfer of the charge pump current values into the corresponding data register is tied to the N-counter loading, but follows the loading of the N-data register in the distance of one N-counter dividing ratio. This guarantees that a new PD-current value becomes valid at the same time when the counters are loaded with the new data. Synchronous programming sequence: 1. Setting of synchronous counter programming by bit c13 of long control data format. 2. Programming of the R-counter, and optional short control data format. With the Enable signal data is loaded into the shadow registers. 3. Programming of the A/N-counter. Data is loaded into shadow registers, the EN-signal starts the synchronous transfer to the data registers. Synchronous data programming is of especial advantage, when large fre- quency steps are to be made in a short time. For this purpose a high reference frequency can be programmed in order to achieve rapid – “rough” – transient response. This method increases the fundamental frequency by nearly the square root of the reference frequency ratio and therefore the settling time is reduced. When rough lock is achieved, another synchronous data transfer is needed to switch back to the original channel spacing. A “fine” lock in will finish the total step response. It may not be necessary to change reference frequency, but it make sense to perform synchronous data acquisition in any case. Espe- cially for GSM, PCN (DCS 1800) and PCS systems the synchronous mode should be used to achieve best performance of the PMB 2347.

Specification, May 2000

3.4.3 Standby Condition (power down)

Each PLL of the PMB 2349 has two programmable standby modes to reduce the current consumption (standby 1, standby 2). Standby 1: The corresponding PLL is switched off, the current consumption is reduced below 1 µA. Standby 2: The corresponding counters, the charge pump and the outputs are switched off. Only the preamplifier of RI-input stays active. (See standby table)

3.4.4 Divide ratio programming

The frequency of an external VCO controlled by the PMB 2347 is given below: with . f VCO : frequency of the external VCO fRI: reference frequency N: divide ratio of the N-counter A: divide ratio of the A-swallow counter P: divide ratio of the prescaler R: divide ratio of the R-counter M=P*N+A: total divide ratio Note: for continous frequency steps following condition is necessary

3.4.5 Prescaler Divide Ratio

For the highest input frequencies of the prescalers the larger divide ratio is nec- essary: RF-PLL: 64/65 for frequencies greater 1500 MHz IF-PLL: 16/17 for frequencies greater 375 MHz fVCO PN⋅() A+[] fRI R-----f RI⋅== AN≤ PN A +⋅[] PP 1 –()⋅≥

Specification, May 2000

3.4.6 Fast wake-up programming

When the circuit is connected to the supply voltage all registers are undefined. Due to the fact that each counter is loading its new start value after it is decre- mented to „zero“, the start-up time of the counters with the programmed values is too long for some applications. If the counters are programmed in standby mode 2 and the PLLs are switched afterwards in operating mode, the counters are starting immediatly with the programmed values. Therefore following data transfer sequence is recommended:

3.4.7 Phase Detector Outputs

The timing diagram is valid for PLL1 and PLL2. Table 3-2 Fast Wake Up Data Transfer Sequence Step Serial Data Transfer Sequence

1 Long Control Word: Asynchronous Mode, Standby2

2 R-Counter

3 A-/N-Counter

4 Long Control Word: Synchronous Mode, Operating Mode

(RI:R) (RF1:M) positive Polarity N-Channel Frequency fV > fR fV leading Frequency fV = fR lock state Frequency fV < fR fV lagging fR fV RF1/2 (RF2:M) negative Polarity P-Channel Tri-State N-Channel P-Channel Tri-State

4 Applications

Applications

Specification, May 2000

4.1 Hint

More Information about “Application” see in separate Document APPLICATION NOTE PMB 2349.

5 Reference

Specification, May 2000

5.1 Electrical Data

5.1.1 Absolute Maximum Ratings

The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Table 5-1 Absolute Maximum Ratings # Parameter Symbol Limit Values Unit Remarks min max 1 Supply Voltage V CC1/2 -0.3 5.5 V 2 Input Voltage VI -0.3 VCC1/ 2+0.3 V

3 Output Voltage VO GND VCC1/2 V

4 Total power dissipation Ptot 300 mW

5 Ambient temperature TA -40 85 °C in operation

6 Storage temperature TStg -50 125 °C

7 Thermal Resistance RthJA 170 K/W

8 ESD Integrity

(according to MIL 883 Method 3015.7) except Pins Vpd1[2] and Vpd2[19] V ESD 0.5 KV preliminary

Specification, May 2000

5.1.2 Operating Range

Within the operational range the IC operates as described in the circuit description. The AC/DC characteristic limits are not guaranteed.

5.1.3 Typical Supply Current ICC

1) VCC1/2= 2.7V, R EXT = 12k, RF-/ IF- and Ri-inputs are open, 3WB optical interface, ICP1 = 4.0mA, ICP2 = 2.0mA, Iref = 100 µA Table 5-2 Operating Range, VCC1/2= 2.7V - 5.0V, TAMB =-27°C # Parameter Symbol Limit Values Unit Test Conditions L Item min max 1 Supply Voltage VCC1/2 2.7 5.0 V 2 Input frequency RF ƒRF 250 2800 MHz VCC1/2 = 3.6V

3 Input frequency IF ƒIF 100 600 MHz

4 Input reference frequencyƒRi 1 45 MHz

5 CP-output current of

/ ICP1 / 4 +20% mA

6 CP-output current of

/ ICP2 / 1 +20% mA 7 CP-output voltages VCP1/2 0.5 VPD1/2 - 0.5 V

8 Ambient temperature TA -40 85 °C

/G01 /G02 This value is guaranteed by design. Table 5-3 Typical Supply Current ICC # Parameter Symbol Limit Values Unit Test Conditions Item min typ max 1 Supply Voltage VCC1/2 2.7 V

2 Supply current:

3 PLL1 & PLL2 active ICC1/2 -20% 9402 +20% µA

Note 1)

4 PLL1 active, PLL2 standby ICC1/2 -20% 7840 +20% µA

5 PLL1 standby2, PLL2 activeICC1/2 -20% 3065 +20% µA

6 PLL1 & PLL2 standby 2 ICC1/2 120 µA

7 PLL1 & PLL2 standby 1 ICC1/2 < 1 µA

Specification, May 2000

5.1.4 AC/DC Characteristics

AC/DC characteristics involve the spread of values guaranteed within the spec- ified supply voltage and ambient temperature range. Typical characteristics are the median of the production. Table 5-4 AC/DC Characteristics with VCC1/2=2.7 .. 5.0 V, Ambient temperature TAMB = 27°C Symbol Limit Values Unit Test Conditions DI t e m min typ max Input Signals DA, CLK, EN (Schmitt-Trigger input stage) H-input voltage VIH 0.7 VCC VCC V L-input voltage VIL 0.3 VCC V Input capacity CI 5 pF H-input current IH 10 µA V I=V CC2 =3.6V 2.3 L-input current IL -10 µA V I=GND 2.4 Input Signal RI Input voltage VI 100 mVrms f= 4 - 45 MHz, VCC1 =3.6V 2.10 Slew rate 4 V/µs V CC1 =2.7 - 5.0 V Input capacity CI 3 pF H-input current IH 30 µA V I=V CC1 =3.6V 2.13 L-input current VI -30 µA V I=GND Input Signals RF Input voltage PI -10 0 dBm f = 150-500 MHz 3.1 Input voltage PI -10 0 dBm f = 500-1500 MHz 3.2 Input voltage PI -20 -10 dBm f = 1500-2500 MHz 3.3 Input voltage PI -15 -10 dBm f = 2500-2800 MHz 3.4 Input Signals IF Input voltage PI -15 +4 dBm f = 50 - 300 MHz 4.1 Input voltage PI -25 -5 dBm f = 200 - 450 MHz 4.2 Input voltage PI -25 -15 dBm f = 450 - 600 MHz 4.3

Specification, May 2000 Table 5-4 AC/DC Characteristics with VCC1/2=2.7 .. 5.0 V, Ambient temperature TAMB = 27°C (continued) Symbol Limit Values Unit Test Conditions DI t e m Output Current ICP1 "1.2 mA" ICP1 -20% 1.2 +20% mA V PD1 =3.6V, VCP1= VPD1 /2 IREF =100µA /G03 5.1 "Tristate" /ICP1 / 0.1 10*) nA /G01 5.5 Output Current ICP2 "1.0 mA" ICP2 -20% +20% mA V PD1 =3.6V, VCP2= VPD2 /2 IREF =100µA /G03 "Tristate" /ICP2 / 0.1 10*) nA /G01 Output Current Offset CP1 & CP2 CP Supply Voltage VPD1/2 2.7 3.6 5.0 VV CP1/2 = VPD1/2/2 CP Current Offsett ICP-OFF -4 0+ 1 3 % Current Mismatch "1.2 mA" ICPMM %V PD1 =3.6V, VCP1 = VPD1 /2 IREF=100 µA "2.0 mA" ICPMM % "2.8 mA" ICPMM % "4.0 mA" ICPMM % Output Rext VRext VRext 1.2 V VCC2 = 3.6V, Rext=12k 10.1 IRext IRext 100 µA VCC2 = 3.6V, Rext=12k Output Signal BSW at BSW/LD-Pin (n-channel open drain) L-output voltage VOL 0.4 VV CC1 = 2.7 - 3.6V, IOL = 0.3 mA Fall time tF 31 0 ns V CC1 = 3.6V, C I = 10pF /G01/G02 these values are guaranteed by design /G03/G02 see chapter 5.5.2 (Charge Pump Performance - Typical Performance) for VCP -range CONSERVATIVE

Specification, May 2000

5.2 Serial Control Data Format Timing

Parameter Symbol Limit Values Unit min. max. Clock frequency ƒCL 15 MHz H-pulsewidth (CLK) tWHCL 30 ns L-pulsewidth (CLK) tWLCL 30 ns Data setup tDS 20 ns Setup time Clock-Enable tCLE 20 ns Setup time Enable-Clock tECL 20 ns H-pulsewidth (Enable) tWHEN 60 ns Rise, fall time tR, tR 10 µs Propagation delay time EN-PORT tDEP 1µ s

Specification, May 2000

5.3 Serial Control Data Formats

In general each PLL can independently be addressed without affecting the other PLL (See also Test Modes). NOTE: MSB of all serial data is shifted first Table 5-6 Address of Data Formats Address Data Format Addressed PLL a2 a1 a0 0 00 Short Control Data Format PLL1 (RF) 0 10 Long Control Data Format PLL1 (RF) 1 00 A-/N-Counter PLL1 (RF) 1 10 R-Counter PLL1 (RF) 0 01 Short Control Data Format PLL2 (IF) 0 11 Long Control Data Format PLL2 (IF) 1 01 A-/N-Counter PLL2 (IF) 1 11 R-Counter PLL2 (IF) Table 5-7 Short Control Data Formats PLL 1 PLL 2 Bit Bit Function Bit Bit Function LSB 0 0a 0 Address LSB 01 a0 Address 1 0a 1 Address 10 a1 Address 2 0a 2 Address 20 a2 Address 3 c0 LD InActive 3 c0 reserved 4 c1 CP current 2 4 c1 reserved 5 c2 CP current 1 5 c2 CP current MSB c3 PLLSel 6 MSB c3 reserved Table 5-8 Long Control Data Formats PLL 1 PLL 2 Bit Bit Function Bit Bit Function LSB 0 0a 0 Address LSB 01 a0 Address 1 1a 1 Address 11 a1 Address 2 0a 2 Address 20 a2 Address 3 c0 LD inactive 3 c0 RiAmp 2 4 c1 CP current 2 4 c1 RiAmp 1 5 c2 CP current 1 5 c2 CP current 1 6 c3 PLLSel 6 c3 Data-Reg Select 7 c4 PSC Div. Ratio 7 c4 PSC Div. Ratio

Specification, May 2000 Table 5-8 Long Control Data Formats (continued) PLL 1 PLL 2 Bit Bit Function Bit Bit Function 8 c5 reserved 8 c5 MFO 9 c6 CPP width 2 9 c6 CPP width 2 10 c7 CPP width 1 10 c7 CPP width 1 11 c8 standby 2 11 c8 standby 2 12 c9 standby 1 12 c9 standby 1 13 c10 CP polarity 13 c10 CP polarity 14 c11 Mode 2 14 c11 IBip 2 15 c12 Mode 1 15 c12 IBip 1 MSB c13 Sync/Async Mode MSB c13 Rext / Rint Table 5-9 A/N-counter Data Formats PLL 1 PLL 2 Bit Bit Function Bit Bit Function LSB 0 0a 0 Address LSB 01 a0 Address 1 1a 1 Address 10 a1 Address 2 0a 2 Address 21 a2 Address

3 LSB n0

16 MSB n13 16 MSB n13

17 LSB ac0

22 MSB ac5

Specification, May 2000 Table 5-10 R-counter Data Formats PLL 1 PLL 2 Bit Bit Function Bit Bit Function LSB 0 0a 0 Address LSB 01 a0 Address 1 1a 1 Address 11 a1 Address 2 1a 2 Address 21 a2 Address

3 LSB r0

Table 5-11 Programming of Operation and Test Modes c12 Mode 1 c11 Mode 2 PLLSel Functional Mode Affected Output: 0 00 TEST MODE FVN - N/A-Counter CP1 + CP2 1 00 TEST MODE FRN - R-Counter CP1 + CP2 0 10 NORMAL OPERATION, MFO active LD / MFO Pin 1 10 NORMAL OPERATION, LD of PLL1 active LD / MFO Pin 0 01 TEST MODE FVN - N/A-Counter CP1 + CP2 1 01 TEST MODE FRN - R-Counter CP1 + CP2 0 11 NORMAL OPERATION, MFO active LD / MFO Pin 1 11 NORMAL OPERATION, LD of PLL2 active LD / MFO Pin Table 5-12 Programming of CP Current of PLL1 CP current 1 Mode 2 CP Current [mA] Remark 0 01 . 2 m A with 100µA reference current ( Rext = 12k ohms ) 1 02 . 0 m A 0 12 . 8 m A 1 14 . 0 m A

Specification, May 2000 Table 5-13 Programming of CP Current of PLL2 CP current 1 CP Current [mA] Remark

0 Tristate

with 100µA reference current1 1.0 mA Table 5-14 Programming of Charge Pump Pulse Width of both PLLs CPP width 1 CPP width 2 Pulse Width [ns] typ. Remark 0 01 . 8 n s 1 02 . 7 n s 0 13 . 6 n s 1 14 . 5 n s Table 5-15 Standby of Power Down Programming of both PLLs Control Bits Mode Affected Output Pins Z: High Impedance (Tristate) standby 1 standby 2 Pin 11 LD/fo Pin 3 CP1 Pin 18 CP2 0 0 standby1 off Z Z 1 0 standby2 off Z Z 0 1 standby1 off Z Z 1 1 Operation Mode active active active Table 5-16 Programming of Synchronous/Asynchronous Mode of PLL1 c13 Sync/Async Synchronous/Asynchronous Mode

0 Asynchronous Mode of PLL 1

1 Synchronous Mode of PLL 1

Table 5-17 Programming of PD Polarity of both PLLs Control Bit PD Polarity c10 PD Polarity 0 negative Polarity 1 positive Polarity

Specification, May 2000 Table 5-18 Programming of Prescaler Divide Ratio of both PLLs Control Bit Prescaler Divide Ratio PSC Div. Ratio

0 PLL1: 32/33 PLL2: 8/9

1 PLL1: 64/65 PLL2: 16/17

Table 5-19 Programming of PLL Select Control Bit PLL Select (LD mode) c3 of PLL1

0 PLL1 (RF)

1 PLL2 (IF)

Table 5-20 Programming of Data Register Select Control Bits IF Data Register Select c3 of PLL2

0 Data Register 1

1 Data Register 2

Table 5-21 Programming of Reference Input Amplifier - RiAmp c0 of PLL2 RiAmp 2 c1 of PLL2 RiAmp 1 RiAmp Resonance Pole Position typical Remark VCC1=VCC2= 2V7 (2V8) 0 09 . 0 M H z nominal / recommended 1 0 11.2 MHz 0 1 19.5 MHz 1 1 28.2 MHz Table 5-22 Programming of Bipolar Power Mode - IBip c11 of PLL2 IBip 2 c12 of PLL2 IBip 1 Bipolar Power Consumtion ƒRF MAX ƒIF MAX Remark 0 0 nominal 2.8 GHz 0.6 GHz nominal / recommended 1 0 nominal + 20 % 2.8 GHz 0.6 GHz not recommended 0 1 nominal - 40 % 2.0 GHz 0.4 GHz powersave mode II 1 1 nominal - 20 % 2.5 GHz 0.5 GHz powersave mode I Table 5-23 Programming of Rext / Rint Mode c13 of PLL2 Rext / Rint External or Internal Reference Resistor

0 External @ Pin 12 - recommended

1 Internal Polysilicone Resistor - not recommended

Specification, May 2000

5.4 Input Sensitivity

The following sections show the typical performance at +25°C.

5.4.1 Typical RF Sensitivity

The PLL setup is: Psc:32/33. N:3, A:1, IF-PLL is in standby mode. VCC is 2.7 V. Chip Mode is set to ’TEST MODE FVN ’. This causes the N/A divider output to be fed to the SINK part of the chargepump (source is switched off all time.) Therefore a resistor which provides a current path from pin CPx to VCP (CP supply) is needed.

5.4.2 Typical IF Sensitivity:

SENSITIVITY - 32/33 N:3 A:1 - 2V7 - Rext - RF POWER [dBm] vs RF FREQUENCY [MHz] vs IBip[%] -45 -40 -35 -30 -25 -20 -15 -10 0 500 1000 1500 2000 2500 3000 100% + Rext - Nominal Mode -40% + Rext - Powersave II -20% + Rext - Powersave I SENSITIVITY - 16/17 N:3 A:1 - 2V5 - Rext - I F POWER [dBm] vs IF FREQUENCY [MHz] vs IBip[%] -45 -40 -35 -30 -25 -20 -15 -10 0 100 200 300 400 500 600 700 800 Ibip: 100% - Rext - Nominal Ibip: -40% - Rext - Powersave II Ibip: -20% - Rext - Powersave I

Specification, May 2000

5.4.3 Typical Ri Sensitivity

The PLL setup is: R:50. VCC is 2.7V. Chip Mode is set to ’TEST MODE FRN ’. This causes the R divider output to be fed to the SOURCE part of the chargepump (sink is switched off all time.) Therefore a resistor which provides a current path from pin CPx to GND (CP gnd) is needed SENSITIVITY S1004K2#1 - R:50 - 2V7 - Rext - Ri Power [dBm] vs Ri Frequency [MHz] vs RiAmp CP->6.22kOhm->Gnd - HPcounter50ohm -65 -55 -45 -35 -25 -15 0 5 10 15 20 25 30 35 40 RiAmp=00b - RiRes=9.0MHz - Nominal RiAmp=01b - RiRes=11.2MHz RiAmp=10b - RiRes=19.5MHz RiAmp=11b - RiRes=28.2MHz

Specification, May 2000

5.5 Charge Pump Performance

5.5.1 Charge Pump Definition

Figure 5-1 Definition of Charge Pump Currents Terms and Abbreviations: VPD Supply Voltage of Charge Pump ∆Vsrc/snk Offset Voltage from GND or VPD Isnkmax Maximum Sink Current @ VPD -∆VSRC Isrcmax Maximum Source Current @ GND+∆VSNK Isnktyp Typical Sink Current @ VPD /2 Isrctyp Typical Source Current @ VPD /2 Isnkmin Minimum Sink Current @ GND+∆VSNK Isrcmin Minimum Source Current @ VPD -∆VSRC Specification of Charge Pump Characteristics: Charge Pump Output Magnitude Variation CPMV: Charge Pump Current Mismatch CPCM: ∆Vsnk VCPVPD/2 Isnkmax Isnktyp Isnkmin Isrcmin Isrctyp Isrcmax ∆Vsrc Isnkmax Isnkmin– Isnkmax Isnkmin+ Isrcmax Isrcmin– Isrcmax Isrcmin+ Isnktyp Isrctyp– Isnktyp Isrctyp+

Specification, May 2000

5.5.2 Typical Performance

VCP is intended to be within ∆VSNK and VPD −∆ VSRC System: standard GSM-application Kvco: 10MHz/V, Icp: 4mA Loopfilter (C1,R2-C2,R3,C3): 270pF,18k Ω -2.2uF,12kΩ ,100pF The following typical performance can be expected:

5.6 Threshold Voltages of Schmitt-Trigger Input

Table 5-24 Typical Performance VCP -range #1 - LIBERAL ∆VSNK = 200mV ∆VSRC = 500mV spurious suppression @200 kHz - better than -80 dB phase noise @ 1kHz / 2V7 - typical 85 dBc/Hz phase noise @ 1kHz / 3V6 - typical 88 dBc/Hz VCP -range #2 - CONSERVATIVE ∆VSNK = 600mV ∆VSRC = 900mV performance of VPD -range #1 CP current variation below +/-20% Typical Vin Thresholds of 3W-Bus 0,82 0,92 1,02 1,12 1,22 1,32 2 , 533 , 544 , 55 VCC typ. High min. typ. Low max.