PMB2240 SIEMENS | Alldatasheet
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*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 2 05.97 &RQWHQWV page
0 Revision History 3
1 General Overview 4
1.1 Features 4
1.2 Applications 4
1.3 Functional Description 4
2 Pinning 5
2.1 Pin Description 5
2.2 Pin Configuration 6
2.3 Package Outline 6
3 Functional Block Diagram 7
4 Circuit Description 8
4.1 Block Level Description 8
4.2 Supply Concept 9
4.3 Power Down Conditions 10
4.4 Matching with Timing Signals of GOLD-uC 10
5 Internal Input/Output Circuits 11
6 Electrical Characteristics 12
6.1 Absolute Maximum Ratings 12
6.2 Operational Range 13
6.3 AC/DC Characteristics 14
6.4 Typical modulator measurement results 18
7 Test Circuits 20
7.1 Test Circuit 1 20
7.2 Test board Layout top 21
7.3 Test board Top place 22
7.4 Test board Layout bottom 23
7.5 Test board Bottom place 24
8 Application 25
8.1 Frequency plan for GSM application 25
8.2 Application hint for phase adjust 26
9 S-Parameters and Input/Output impedances 27
9.1 S-Parameters: Transmit Mixer Output MO/MOX 28
9.2 S-Parameters: IF Input IF/IFX 28
9.3 S-Parameters: RF Input RFB1/RFB2 29
9.4 S-Parameters: Output to Receiver RF/RFX 30
9.5 S-Parameters: Modulator Output E/EX 31
9.6 S-Parameters: Modulatór Input LO/LOX 31
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 3 05.97 5HYLVLRQ+LVWRU\\ Changes from Data sheet PMB2240 V1.5 ( 08.96 ) to Data sheet PMB2240 V1.6 ( 5.97 ) ’DWDVKHHW9 ’DWDVKHHW9 6XEMHFW 3DJH ,WHP 3DJH ,WHP &KDQJH
1 General
4141 R e v i s e d
2 Pinning 5 2.1 5 2.1 Pin 9 changed to VCCPR; Pin 13 changed to SLEEP; Pins 17,18,20,21 changed to GND pins
3 Functional block
7 3 7 3 Prescaler with separate VCCPR-pin; Former SLEEP/PR and SLEEP/RF are merged to SLEEP; Oscillator/Buffer for RFIN removed;
4 Circuit
description
8,9,10 4 8,9,10 4 Revised
5 Internal I/O
6 Asolute Maxi-
12 6.1 12 6.1 ESD integrity revised; Item symbols revised
7 Operational
13 6.2 13 6.2 Temperature range - 30°C - 85°C
8 Prescaler 15 23 15 23 minimum H-voltage
increased to 2.3V
9 Electrical
12-18 6 12-17 6 Spec item symbols revised
10 AC/DC
14 6.3 #4 14 6.3 #4 Now referred to Test circuit 1
11 S-Parameters 27-30 9 27-31 9 Smith diagrams of
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 4 05.97 *HQHUDO2YHUYLHZ )HDWXUHV - Transmitter with I/Q modulator - Direct I/Q modulation - Generation of orthogonal carriers with possibility of phase adjust with external resistors at OFF1/OFF2 - 32dB minimum carrier rejection, 35dB minimum SSB rejection with 1 Vpp I/Q drive level - 50dB rejection of third order products with 1 Vpp I/Q drive level - -3dBm output power at 1 Vpp I/Q drive level with 200 Ohms load according testcircuit 1 - RF oscillator signal is AC-coupled to internal buffer stage (symmetrical or unsymmetrical) - The RF oscillator-signal is buffered for off-chip use, especially for receiver chip PMB2405. - Prescaler for the RF oscillator signal - Possibility to build RF-PLL with integrated prescaler + PMB2306 - Possibility to use the IF oscillator signal from the IF-VCO on PMB2405 - Possibility to use external source for IF oscillator-signal - Digital parts of fixed IF frequency PLL (fixed-PLL) for IF-VCO on PMB2405 - Supply voltage range from 2.7 V to 4.5 V - P-TQFP-48 package - Temperature range -30° to 85°C $SSOLFDWLRQV - Vector modulated digital mobile cellular systems as GSM, DAMPS, PDC,WLAN etc. - Various modulation schemes, such as PM, PSK, FSK, QAM, QPSK, GMSK etc. - Analog systems with FM and AM modulation - Space and power saving optimizations of existing discrete transmitter circuits )XQFWLRQDO’HVFULSWLRQ The PMB2240 is a single-chip transmitter which includes a prescaler for the main oscillator signal and a fixed frequency PLL for the IF oscillator. The transmitter is designed for use in conjunction with the single-chip receiver PMB2405 and the CMOS PLL PMB2306. The RF oscillator signal can be supplied from an external source symmetrically as well as unsymmetrically. The oscillator signal can be buffered for off-chip use, depending on a separate power down pin. There is a prescaler by 64/65 for the RF oscillator signal on chip, which can be used to implement a PLL together with the PMB2306. The on-chip fixed-PLL consists of the system clock divider, the IF oscillator signal divider, the phase detector and the charge pump. The IF oscillator signal divider is driven by the oscillator on the PMB2405 or by an external discrete VCO. The two oscillator signals are combined in the transmit mixer, and the image sideband and other mixing products are suppressed with an external interstage filter. The filtered signal reenters the chip at the modulator inputs LO/LOX. The modulator generates two orthogonal carriers which are mixed with the modulation signals I and Q in two Gilbert multipliers. The phase between the two carriers can be fine-adjusted to 90 ° (orthogonality) by two external resistors at OFF1/OFF2 for best SSB suppression. The outputs of the Gilbert cells are added and amplified by a linear output stage. The PMB2240 is designed for digital mobile telephones according to the GSM-Standard. The chip can also be used for other digital systems and the dual mode system. As part of the Siemens GSM/DCS chipset the derivatives PMB2245 and PMB2247 are offered for the DCS 1800 and DCS 1900 frequency range.
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 5 05.97 3LQQLQJ 3LQ’HVFULSWLRQ /c51/c76/c81/c3/c49/c82/c17 /c54/c92/c80/c69/c82/c79 /c41/c88/c81/c70/c87/c76/c82/c81 1, 44, 46 GND2 Ground for the PLL-parts and their bias
2 PUPLO2/FP Power down for fixed-PLL-dividers and phase detector
3 IF Input for external IF oscillator signal
4 IFX Input for inverted external IF oscillator signal
5 VCC2 Supply voltage for PLL parts (IF and RF) and their biasing
6 PUPLO2/BU Power down for IF/IFX input buffer
7 RF RF oscillator signal to receiver
8 RFX Inverted RF oscillator signal to receiver
9 VCCPR Separate supply voltage for RF-PLL prescaler
10 TOUT Output of RF-PLL prescaler
11 IREF/PLL Output for reference current for external RF-PLL-chip
12 FMOD Modulus control for prescaler
13 SLEEP Power down of RF oscillator input- and output buffer and the prescaler
14,17,18,20 GND3 Ground for RF oscillator + BufRX
15 VCC3 Supply voltage for BufRX and BufRF
16 RFB1 RF oscillator input buffer (inverting input)
19 RFB2 RF oscillator input buffer (non-inverting input)
21,24 GND4 Ground for internal shielding
22 LO Modulator LO frequency input
23 LOX Inverted Modulator LO frequency input
25,33 GND1 Ground for modulator and mixer parts + Bias1
26 MO Mixer output, open collector
27 MOX Inverted mixer output, open collector
28 GND5 Ground for substrate contacts in the modulator
29 QX Quadratur modulating inverting input, open base
30 Q Quadratur modulating input, open base
31 I In phase modulating input, open base
32 IX In phase inverted modulating input, open base
34 E Non-inverting output of modulator, open collector; ESD disconnected
35 EX Inverting output of modulator, open collector; ESD disconnected
36 VCC1 Supply voltage for modulator and mixer parts + Bias1
37 TREF Temperature compensated DC reference voltage output for modulator
I/Q -inputs via GMSK baseband circuit
38 TXON1 Power down for modulator and mixer parts + Bias1
39 OFF1 Phase error adjustment of orthogonal carriers with constant R
40 OFF2 Phase error adjustment of orthogonal carriers with constant R
41 T3 Test pin 3
42 PDBUFRX Power down for "BufRX"
43 n.c. not bonded
45 CHP Phase-detector output for external loop filter (charge pump)
47 RREF/PLL To be connected to GND via resistor to determine IREF for RF-PLL
48 FREF Input of system reference clock
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 6 05.97 3LQ&RQILJXUDWLRQ (top view) 3DFNDJH2XWOLQH 4XDG)ODWSDFNDJH 374)3
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 7 05.97 )XQFWLRQDO%ORFN’LDJUDP
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 8 05.97 &LUFXLW’HVFULSWLRQ %ORFN/HYHOGHVFULSWLRQ The GSM transmitter PMB2240 contains a number of functions that have been realised with multiple chips earlier: - Oscillator signal input balanced or unbalanced - RF-PLL prescaler - IF-PLL dividers and phase detection - TX - mixer - I/Q modulator The PMB2240 V1.6 is designed to be used with an external RF oscillator module. On chip this signal is AC-coupled to an internal buffer stage. Therefore the RF input is suitable for symmetrical or single ended use. There is no need for an external DC-bias of the RF input. The active parts of the IF oscillator are located on the receive chip PMB2405. A buffer BufRX, which can be powered down by pin PDBUFRX, is used to transmit the RF oscillator signal to the receiver chip to drive the RF receive mixer. A special input buffer BufTX receives the IF oscillator signal from the receive chip or an external source. The RF oscillator signal is divided by the integrated 64/65 prescaler which can be connected to the CMOS PLL circuit PMB2306 for the RF oscillator PLL. The supply pin VCCPR is a separate prescaler supply, which openes the possilility to run the prescaler and the rest of the RF synthesizer on a supply voltage that is different from the supplies of the rest of the chip. For the IF-PLL the active oscillator structures on the PMB2405 or an external VCO module can be used. The PMB2240 V1.6 contains the digital parts tor the IF oscillator PLL (fixed-PLL): the IF- frequency and system clock dividers and a phase detector plus charge pump are integrated to lock the IF oscillator to the external system clock. The oscillator signal drives the divider by 2 in front of the transmit mixer. The phase locked IF- and RF- signals are converted into the transmit band (e.g. 880 - 915 MHz for GSM) by the TX- mixer. The mixer output signal leaves the chip at MO/MOX and passes an external interstage filter to provide suppression of unwanted products. This signal reenters the chip at the modulator input LO/LOX. The LO signal is divided into two orthogonal carriers at the transmit frequency. The phase between the two carriers can be fine-adjusted to 90 ° (orthogonality) by two external resistors at OFF1/OFF2 for maximum SSB suppression. The modulator consists of two Gilbert multipliers, where the modulating signals I(t) and Q(t) are multiplied with the RF-carriers. The outputs of both Gilbert cells are added and amplified by a linear output stage. The modulated transmit signal is available at E/EX and is fed into a transmitter power amplifier.
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 9 05.97 6XSSO\\FRQFHSW There are four independent supply voltages ( VCC1-3,VCCPR ) and ground rails ( GND1-4 ) to decouple the modulator/mixer parts, the synthesizer parts, and the RFVCO parts. The supply pin VCCPR is a separate prescaler supply, which openes the possilility to run the prescaler together with the rest of the RF synthesizer on a supply voltage that is different from the supplies of the rest of the chip GND4 is a special shielding ground to decrease crosstalk between the separately supplied blocks. GND5 collects the substrate contacts in the modulator and mixer. It is recommended to connect all GND pins to a common GND on the board. In the following figure the chip schematic is partitioned according to its supply rails.
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 10 05.97 3RZHUGRZQFRQGLWLRQV The PMB 2240 has five Power down inputs. PD = Low means that the respective part of the chip is in power down mode. TXON1: Modulator, mixer, Bufmi1, Bufmi2 TXON1 /\\ PUPLO2/FP %2 divider SLEEP: BufRF, prescaler with its input buffer BufPLL PUPLO2/BU: Input buffer BufTX for external IF oscillator-signal PUPLO2/FP: fixed-PLL, (%492; %13; phase detector, charge pump) PDBUFRX /\\ SLEEP BufRX For normal operation only three modes are used: sleep mode, TX-mode, RX-mode. Depending on the application some power down-pins can be combined, and others can be fixed to supply rails. 0DWFKLQJZLWK7LPLQJ6LJQDOVRI*2/’X& In application with PMB2405 and GOLD-uC the power down pins of PMB2240 must be connected to the timing signals of GOLD-uC as follows: PMB 2240 GOLD-uC TXON1 connected to TXON1 PUPLO2/BU, PUPLO2/FP connected to PUPLO2 SLEEP, PDBUFRX connected to general purpose port pin
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 11 05.97 ,QWHUQDO,QSXW2XWSXW&LUFXLWV
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 12 05.97 (OHFWULFDO&KDUDFWHULVWLFV $EVROXWH0D[LPXP5DWLQJV The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. 3DUDPHWHU 6\\PERO /LPLW9DOXHV 8QLW 5HPDUNV PLQ PD[ 1 Supply Voltage V CC -0.3 5.0 V 2 Input/Output Voltage V IO -0.3 5.0 V
3 Open Collector Output
VOCE VCC - 1.5 V CC + 1.0 V
4 Open Collector Output
VOCM -0.3 5.0 V
5 Differential Input
(any differential Input) VID 2V
6 Junction Temperature T J -40 125 °C
7 Storage Temperature T S -55 125 °C
8 Thermal Resistance
(junction to ambient) R thJA 165 K/W
9 ESD integrity * V ESD -1000 +1000 V according
MIL-Std. 883D, method 3015.7 * exception: Pin 47 to GND and a negative Pulse to pin 11 => 800V ESD-integrity
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 13 05.97 2SHUDWLRQDO5DQJH Within the operational range the IC operates as described in the circuit description. The AC/DC characteristics limits are not guaranteed. VCC = 2.7V to 4.5V; TA = -30 to 85°C; 3DUDPHWHU 6\\PERO /LPLW9DOXHV 8QLW 5HPDUNV PLQ PD[
1 RFB1/RFB2 Input Level P RFIN -10 0 dBm
2 RFB1/RFB2 Input
3 IF/IFX Input Level P IFIN -15 0 dBm
4 IF/IFX Input Frequency f IFIN 400 600 MHz
5 LO/LOX Input Level P LO -15 0 dBm
6 LO/LOX Input Frequency f LO 800 1000 MHz
7 Mixer output Frequency
8 PD-Signals Voltage-L V PDL 00 . 8 V 9 PD-Signals Voltage-H V PDH 2.0 V CC V Note: Power levels are referred to impedance of 50 Ohms
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 14 05.97 $&’&&KDUDFWHULVWLFV AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. VCC = 2.7V/4.5V; TA = 25°C; 3DUDPHWHU 6\\P ERO /LPLW9DOXHV 8QLW 7HVW&RQGLWLRQ 7HVW FLUFXLW PLQ W\\S PD[
1 Supply Current
9.3 2.5 6.3 3.3 7.5 13.2 mA mA mA mA mA mA TXON1 & PUPLO2/FP & PUPLO2/BU & SLEEP & PDBUFRX HIGH
2 Supply Current
Ie,Iex Imo , Imox Ivcc2 Ivcc3 Ivccpr uA uA uA uA uA uA TXON1 & PUPLO2/FP & PUPLO2/BU & SLEEP & PDBUFRX LOW 7UDQVPLW0L[HU2XWSXW0202;
3 Output impedance
(open collector diff. output) see S-parameter 9.1
4 Output level P MO -18 -15 -12 dBm 900 MHz 1
5 Carrier suppression aCmix 25 30 dB 1
6 Output Frequency f MO 800 1000 MHz wanted sideband 1
,)LQSXWDW,),);
7 Input Level P IFIN -15
8 Input Frequency f IFIN 400 600 MHz 1
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 15 05.97 3DUDPHWHU 6\\PEO /LPLW9DOXHV 8QLW 7HVW&RQGLWLRQ 7HVW PLQ W\\S PD[ &LUFXLW )L[HG3// 9 lock in time t I 250 usec Application hint 10 Power on delay t po 0.3 usec Application hint
11 Input level at
VFREFI 0.4 1 2 Vpp high input levels may cause spurious problems
12 Output current at
ICHP +-450 +-600 +-750 uA 1 2XWSXWWRUHFHLYHU5)5);
13 Internal DC bias V RFDC VCC -
0.6 14 Output impedance see S-parameter 9.4
15 Output level P RFOUT -11 -8 -5 dBm f = 1200 MHz 1
5)LQSXWDW5)%5)%
16 Input Level P RFIN -10 0 dBm 1
17 Input Frequency f RFIN 900 1300 MHz 1
/2LQSXWDW/2/2; 18 Input impedance see S-parameter 9.6
19 Input Level P LO -15 0 dBm into 50 Ohm 1
20 Input Frequency f LO 800 1000 MHz 1
a IM 14 dB Application hint 3UHVFDOHU
22 Input at FMOD
VFMOD 00 . 8 V 1
23 Input at FMOD
VFMOD 2.3 V CC V1
24 Output DC level
0.7
25 Output AC
VTOUTAC 160 300 mVpp f = 13.5MHz to 20.5MHz
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 16 05.97 3DUDPHWHU 6\\PEO /LPLW9DOXHV 8QLW 7HVW&RQGLWLRQ 7HVW PLQ W\\S PD[ &LUFXLW 5HIHUHQFHFXUUHQWIRUH[WHUQDO3//
26 External voltage
VIREF/PLL 1.2 V 1
27 Current sourced
IIREF/PLL 100 360 uA dependent of resistor value at RREF/PLL *
28 Temperature
at IREF/PLL * I IREF/PLL +-2 % temperature range: -30 to 85 °C nominal current: 300uA 0RGXODWRULQSXWV,,;DQG44;
29 I-IX and Q-QX
VI-IX, VQ-QX 500 1000 mVpp
30 Recommended
I-IX and Q/QX * V DCext 15 mV
31 Reference voltage
for I,Q modulating inputs V TREF 1.25 1.35 1.45 V Reference to external GMSK basebandcircuit to bias I and Q of PMB2240 (temperature compensated)
32 Resistive load at
TREF * R TREF 3k O h m
33 Input base current II/Q_DC 1 6 12 uA
34 Differential input
resistance * R I-IX 50 kOhm at 200 kHz
35 Differential input
capacitance * C I-IX 1p F
36 Input frequency * fI-IX
10 MHz
- Design hint required by PMB2306 R19 = 6.8kΩ * R19 at pin RREF/PLL gives constant PLL reference current at pin IREF/PLL: ( R19max = open -> IIREF/PLLmin = 0, R19min = 2 KOhm -> IIREF/PLLmax =360uA)
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 17 05.97 3DUDPHWHU 6\\PEO /LPLW9DOXHV 8QLW 7HVW&RQGLWLRQ 7HVW PLQ W\\S PD[ &LUFXLW 0RGXODWRURXWSXW((;fLO = 900 MHz; fI-IX = fQ-QX =10MHz;
37 Output impedance
(open collector diff. output) see S-parameter 9.5
38 Output power P E_b -12 -9 -6 dBm cond1 ** 1
' -6 -3 0 dBm cond2 *** 1
39 Carrier suppression aCmod 26 32 dB cond1 ** 1
32 38 dB cond2 *** 1
40 Single sideband
aSSB 35 dB with 90° phase shift between I and Q; ROFF1,ROFF2 tuned to maximum SSB suppression ( appl. hint: fig.1,sec. 8.3)
41 Suppression of
a IM3 62 dB cond1 1 50 dB cond2 * 1
42 Signal to noise
ratio * S/N -139 dBc/Hz cond1 PLO = -8 dBm foffset = 20MHz -142 dBc/Hz cond2 * PLO = -8 dBm foffset = 20MHz * Design hint cond1 means VI-IX = VQ-QX = 500 mVpp * cond2 means VI-IX = VQ-QX = 1 Vpp
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 18 05.97 7\\SLFDOPRGXODWRUPHDVXUHPHQWUHVXOWV The following measurements refer to Testcircuit 1 ( item , page 21) /c19/c17/c20 /c19/c17/c21 /c19/c17/c22 /c19/c17/c23 /c19/c17/c24 /c19/c17/c25 /c19/c17/c26 /c19/c17/c27 /c19/c17/c28 /c20 /c71/c76/c73/c73/c72/c85/c72/c81/c87/c76/c68/c79/c3/c76/c81/c83/c88/c87/c3/c89/c82/c79/c87/c68/c74/c72/c3/c68/c87/c3/c44/c16/c44/c59/c3/c68/c81/c71/c3/c52/c16/c52/c59/c3/c18/c3/c57/c83/c83 /c20/c21/c25 /c20/c21/c27 /c20/c22/c19 /c20/c22/c21 /c20/c22/c23 /c20/c22/c25 /c20/c22/c27 /c20/c23/c19 /c20/c23/c21 /c20/c23/c23 /c54/c18/c49/c3/c18 /c3 /c11/c71/c37/c70/c18/c43/c93/c12 /c51/c79/c82 /c19/c17/c19/c19/c3/c71/c37/c80/c3 /c16/c27/c17/c19/c19/c3/c71/c37/c80/c3 /c48/c82/c71/c88/c79/c68/c87/c82/c85/c3/c86/c76/c74/c81/c68/c79/c3/c87/c82/c3/c81/c82/c76/c86/c72/c3/c85/c68/c87/c76/c82/c3/c54/c18/c49/c3/c89/c72/c85/c86/c88/c86/c3/c44/c15/c52/c3/c76/c81/c83/c88/c87/c3/c79/c72/c89/c72/c79 /c51/c79/c82/c3/c29/c3/c47/c50/c3/c71/c85/c76/c89/c72/c3/c79/c72/c89/c72/c79 /c19/c17/c20 /c19/c17/c21 /c19/c17/c22 /c19/c17/c23 /c19/c17/c24 /c19/c17/c25 /c19/c17/c26 /c19/c17/c27 /c19/c17/c28 /c20 /c71/c76/c73/c73/c72/c85/c72/c81/c87/c76/c68/c79/c3/c76/c81/c83/c88/c87/c3/c89/c82/c79/c87/c68/c74/c72/c3/c68/c87/c3/c44/c16/c44/c59/c3/c68/c81/c71/c3/c52/c16/c52/c59/c3/c18/c3/c57/c83/c83 /c21/c19 /c21/c24 /c22/c19 /c22/c24 /c23/c19 /c23/c24 /c24/c19 /c68/c70 /c3/c18 /c3 /c71/c37 /c51/c79/c82 /c19/c17/c19/c19/c3/c71/c37/c80/c3 /c16/c27/c17/c19/c19/c3/c71/c37/c80/c3 /c48/c82/c71/c88/c79/c68/c87/c82/c85/c3/c70/c68/c85/c85/c76/c72/c85/c3/c86/c88/c83/c83/c85/c72/c86/c86/c76/c82/c81/c3/c68/c70/c3/c89/c72/c85/c86/c88/c86/c3/c44/c15/c52/c3/c76/c81/c83/c88/c87/c3/c79/c72/c89/c72/c79 /c51/c79/c82/c3/c29/c3/c47/c50/c3/c71/c85/c76/c89/c72/c3/c79/c72/c89/c72/c79
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 19 05.97 /c19/c17/c21 /c19/c17/c22 /c19/c17/c23 /c19/c17/c24 /c19/c17/c25 /c19/c17/c26 /c19/c17/c27 /c19/c17/c28 /c20 /c71/c76/c73/c73/c72/c85/c72/c81/c87/c76/c68/c79/c3/c76/c81/c83/c88/c87/c3/c89/c82/c79/c87/c68/c74/c72/c3/c68/c87/c3/c44/c16/c44/c59/c3/c68/c81/c71/c3/c52/c16/c52/c59/c3/c18/c3/c57/c83/c83 /c23/c24 /c24/c19 /c24/c24 /c25/c19 /c25/c24 /c26/c19 /c26/c24 /c27/c19 /c44/c48 /c22/c3/c18/c3/c71/c37 /c47/c50/c3/c73/c85/c72/c84/c88/c72/c81/c70/c92 /c28/c19/c19/c17/c19/c19/c3/c48/c43/c93/c3 /c48/c82/c71/c88/c79/c68/c87/c82/c85/c3/c87/c75/c76/c85/c71/c3/c82/c85/c71/c72/c85/c3/c76/c81/c87/c72/c85/c80/c82/c71/c88/c79/c68/c87/c76/c82/c81/c3/c83/c85/c82/c71/c88/c70/c87/c3/c44/c48/c22/c3/c89/c72/c85/c86/c88/c86/c3/c44/c15/c52/c3/c76/c81/c83/c88/c87/c3/c79/c72/c89/c72/c79 /c47/c50/c3/c71/c85/c76/c89/c72/c3/c79/c72/c89/c72/c79/c3/c29/c3/c51/c79/c82/c3/c32/c3/c16/c27/c3/c71/c37/c80 /c19 /c19/c17/c24 /c20 /c20/c17/c24 /c21 /c21/c17/c24 /c3/c71/c76/c73/c73/c72/c85/c72/c81/c87/c76/c68/c79/c3/c76/c81/c83/c88/c87/c3/c89/c82/c79/c87/c68/c74/c72/c3/c68/c87/c3/c44/c16/c44/c59/c3/c68/c81/c71/c3/c52/c16/c52/c59/c3/c18/c3/c57/c83/c83 /c16/c21/c24 /c16/c21/c19 /c16/c20/c24 /c16/c20/c19 /c16/c24 /c19 /c24 /c51/c82/c88/c87/c3/c18/c3 /c71/c37/c80 /c47/c50/c3/c73/c85/c72/c84/c88/c72/c81/c70/c92 /c28/c19/c19/c17/c19/c19/c3/c48/c43/c93/c3 /c48/c82/c71/c88/c79/c68/c87/c82/c85/c3/c82/c88/c87/c83/c88/c87/c3/c83/c82/c90/c72/c85/c3/c51/c82/c88/c87/c3/c89/c72/c85/c86/c88/c86/c3/c44/c15/c52/c3/c76/c81/c83/c88/c87/c3/c79/c72/c89/c72/c79 /c47/c50/c3/c71/c85/c76/c89/c72/c3/c79/c72/c89/c72/c79/c29/c3/c51/c79/c82/c3/c32/c3/c16/c27/c3/c71/c37/c80
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 20 05.97 7HVW&LUFXLWV 7HVW&LUFXLW A V ROFF1/ROFF2 = 0 ... 600 Ohm; see application hint on page 26
GSM-Transmitter PMB 2240 V 1.6 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens Aktiengesellschaft 21 05.97
7.2 Test board Layout top, (M 2:1)
GSM-Transmitter PMB 2240 V 1.6 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens Aktiengesellschaft 22 05.97
7.3 Test board Top place
GSM-Transmitter PMB 2240 V 1.6 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens Aktiengesellschaft 23 25.02.98
GSM-Transmitter PMB 2240 V 1.6 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens Aktiengesellschaft 24 25.02.98
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 25 05.97 $SSOLFDWLRQ )UHTXHQF\\SODQIRU*60DSSOLFDWLRQ In the application the IF oscillator on the receive chip is locked at a frequency of 492 MHz by the fixed-PLL circuit. The RF oscillator module is tuned from 1126 MHz to 1206 MHz.
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 26 05.97 $SSOLFDWLRQKLQWIRUSKDVHDGMXVW The LO level for maximum SSB suppression can be tuned to every value within its operational range ( -15 dBm to 0 dBm ) by appropriate choice of ROFF1/ROFF2. At pins OFF1 and OFF2 always a resistor or a short cicuit to ground is required. The recommended range of values is: 0 > ROFF1,ROFF2 < 600 Ohm. In fig. 1 the maximum single sideband suppression (assb) is tuned to -7dBm LO input power accordinng test circuit 1. ROFF1=0 and ROFF2=200 Ohms. The LO level can vary +/- 4dB around its optimum value with assb < -35dB. 3ORG%P DVVEG% 6LQJOH6LGHEDQGVXSSUHVVLRQDVVEYHUVXVORLQSXWSRZHU3OR ILJ Phase adjust with ROFF1=short, ROFF2=200 Ohms
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 27 05.97 63DUDPHWHUVDQG,QSXW2XWSXW,PSHGDQFHV The S-parameters provided in this section are based on measurements. Measurement setup for differential in-/outputs: Port1 Port2DUT In/Out Inx/Outx The input/output impedances are calculated from these parameters. The impedances are given as equivalent circuit with lumped elements for differential and single ended in-/outputs. The high frequency in-/outputs in this section are base inputs or collector outputs. As equivalent circuit for these in-/outputs a resistor Rp in parallel to a capacitance Cp is derived: differential single endedRpd Cpd Rps Cps The S-parameters are available on disk.
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 28 05.97 7UDQVPLW0L[HU2XWSXW0202; S-parameters: f S11 S21 S12 S22 GHz MAG ANG MAG ANG MAG ANG MAG ANG Output impedance at MO/MOX: /c27/c19/c19 /c27/c24/c19 /c28/c19/c19 /c28/c24/c19 /c20/c19/c19/c19 /c73/c3/c76/c81/c3/c48/c43/c93 /c19 /c20 /c21 /c22 /c23 /c24 /c25 /c26 /c27 /c53/c3/c76 /c81/c3/c78/c50/c75/c80 /c53/c83/c71 /c53/c83/c86 /c27/c19/c19 /c27/c24/c19 /c28/c19/c19 /c28/c24/c19 /c20/c19/c19/c19 /c73/c3/c76/c81/c3/c48/c43/c93 /c19 /c19/c17/c20 /c19/c17/c21 /c19/c17/c22 /c19/c17/c23 /c19/c17/c24 /c19/c17/c25 /c19/c17/c26 /c19/c17/c27 /c19/c17/c28 /c20 /c38/c3/c76 /c81/c3/c83/c41 /c38/c83/c71 /c38/c83/c86 ,),QSXW,),); S-parameters: f S11 S21 S12 S22 GHZ MAG ANG MAG ANG MAG ANG MAG ANG Input impedance at IF/IFX: /c23/c19/c19 /c23/c24/c19 /c24/c19/c19 /c24/c24/c19 /c25/c19/c19 /c73/c3/c76/c81/c3/c48/c43/c93 /c19 /c21 /c23 /c25 /c27 /c20/c19 /c53/c3/c76 /c81/c3/c78/c50/c75/c80 /c53/c83/c71 /c53/c83/c86 /c23/c19/c19 /c23/c24/c19 /c24/c19/c19 /c24/c24/c19 /c25/c19/c19 /c73/c3/c76/c81/c3/c48 /c43/c93 /c19 /c19/c17/c21 /c19/c17/c23 /c19/c17/c25 /c19/c17/c27 /c20 /c20/c17/c21 /c20/c17/c23 /c20/c17/c25 /c38/c3/c76 /c81/c3/c83/c41 /c38/c83/c71 /c38/c83/c86
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 29 05.97 5),QSXW5)%5)% S-parameters: f S11 S21 S12 S22 GHZ MAG ANG MAG ANG MAG ANG MAG ANG Input impedance: /c28/c19/c19 /c20/c19/c19/c19 /c20/c20/c19/c19 /c20/c21/c19/c19 /c20/c22/c19/c19 /c73/c3/c76/c81/c3/c48/c43/c93 /c19 /c19/c17/c21 /c19/c17/c23 /c19/c17/c25 /c19/c17/c27 /c20 /c20/c17/c21 /c20/c17/c23 /c20/c17/c25 /c53/c3/c76 /c81/c3/c78/c50/c75/c80 /c83/c71 /c83/c86 /c28/c19/c19 /c20/c19/c19/c19 /c20/c20/c19/c19 /c20/c21/c19/c19 /c20/c22/c19/c19 /c73/c3/c76/c81/c3/c48/c43/c93 /c19 /c19/c17/c20 /c19/c17/c21 /c19/c17/c22 /c19/c17/c23 /c19/c17/c24 /c19/c17/c25 /c19/c17/c26 /c19/c17/c27 /c19/c17/c28 /c20 /c38/c3/c76 /c81/c3/c83/c41 /c38/c83/c71 /c38/c83/c86
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 30 05.97 2XWSXWWR5HFHLYHU5)5); S-parameters: f S11 S21 S12 S22 GHZ MAG ANG MAG ANG MAG ANG MAG ANG Output impedance at RF/RFX: /c28/c19/c19 /c20/c19/c19/c19 /c20/c20/c19/c19 /c20/c21/c19/c19 /c20/c22/c19/c19 /c73/c3/c76/c81/c3/c48/c43/c93 /c19 /c19/c17/c19/c24 /c19/c17/c20 /c19/c17/c20/c24 /c19/c17/c21 /c19/c17/c21/c24 /c19/c17/c22 /c19/c17/c22/c24 /c19/c17/c23 /c19/c17/c23/c24 /c19/c17/c24 /c53/c3/c76 /c81/c3/c78/c50/c75/c80 /c83/c71 /c83/c86 /c28/c19/c19 /c20/c19/c19/c19 /c20/c20/c19/c19 /c20/c21/c19/c19 /c20/c22/c19/c19 /c73/c3/c76/c81/c3/c48/c43/c93 /c19 /c19/c17/c20 /c19/c17/c21 /c19/c17/c22 /c19/c17/c23 /c19/c17/c24 /c19/c17/c25 /c19/c17/c26 /c19/c17/c27 /c19/c17/c28 /c20 /c38/c3/c76 /c81/c3/c83/c41 /c38/c83/c71 /c38/c83/c86
*607UDQVPLWWHU 30%9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 31 05.97 0RGXODWRU2XWSXW((; S-parameters: f S11 S21 S12 S22 GHz MAG ANG MAG ANG MAG ANG MAG ANG Output impedance at E/EX: /c27/c19/c19 /c27/c24/c19 /c28/c19/c19 /c28/c24/c19 /c20/c19/c19/c19 /c73/c3/c76/c81/c3/c48/c43/c93 /c19 /c20 /c21 /c22 /c23 /c24 /c25 /c26 /c27 /c53/c3/c76 /c81/c3/c78/c50/c75/c80 /c83/c71 /c83/c86 /c27/c19/c19 /c27/c24/c19 /c28/c19/c19 /c28/c24/c19 /c20/c19/c19/c19 /c73/c3/c76/c81/c3/c48/c43/c93 /c19 /c19/c17/c21 /c19/c17/c23 /c19/c17/c25 /c19/c17/c27 /c20 /c20/c17/c21 /c20/c17/c23 /c20/c17/c25 /c38/c3/c76 /c81/c3/c83/c41 /c38/c83/c71 /c38/c83/c86 0RGXODWRU,QSXW/2/2; S-parameters: f S11 S21 S12 S22 GHZ MAG ANG MAG ANG MAG ANG MAG ANG Input impedance at LO/LOX: /c27/c19/c19 /c27/c24/c19 /c28/c19/c19 /c28/c24/c19 /c20/c19/c19/c19 /c73/c3/c76/c81/c3/c48/c43/c93 /c19 /c19/c17/c21 /c19/c17/c23 /c19/c17/c25 /c19/c17/c27 /c20 /c20/c17/c21 /c20/c17/c23 /c20/c17/c25 /c20/c17/c27 /c21 /c53/c3/c76 /c81/c3/c78/c50/c75/c80 /c53/c83/c71 /c53/c83/c86 /c27/c19/c19 /c27/c24/c19 /c28/c19/c19 /c28/c24/c19 /c20/c19/c19/c19 /c73/c3/c76/c81/c3/c48/c43/c93 /c19 /c19/c17/c21 /c19/c17/c23 /c19/c17/c25 /c19/c17/c27 /c20 /c20/c17/c21 /c20/c17/c23 /c20/c17/c25 /c38/c3/c76 /c81/c3/c83/c41 /c38/c83/c71 /c38/c83/c86