PM7350-1 PMC | Alldatasheet
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PMC-990147 (P2) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 1999 PMC-Sierra, Inc. PMC-Sierra,Inc. Dual Serial Link, PHY Multiplexer PM7350 S/UNI-DUPLEX
FEATURES
- I n t egrated analog/digital device that interfaces a UTOPIA L2 bus to a serial backplane with optional 1:1 protection usin g high speed Low Voltage Differential Signal (LVDS ) serial links.
- For framers or modems without UTOPIA bus interfaces: optionally provides cell delineation (I.432) across 16 clock and data (bit serial) interfaces.
- Interworks with PM7351 S/UNI-VORTEX devices to implement a point-to-multipoint serial backplane architecture, with optional 1:1 protection of the common card.
- Interfaces to another S/UNI-DUPLEX device (via a single LVDS link) to create a simple point-to-point “UTOPIA bus extension” capability.
- Interfaces to two S/UNI-DUPLEX devices to create a 1:1 protected bus extension.
- R e quires no external memory devices.
- Low power 3.3V CMOS technology.
- Standard 5 pin P1149 JTAG port.
- 160 ball PBGA, 15mm x 15mm.
- In the LVDS receive direction: selects traffic from the LVDS link marked active and demultiplexes the individual cell streams to the appropriate PHY device.
- In the LVDS transmit direction: accepts 52-56 b yte cell streams from up to 32 UTOPIA L2 compatible PHY devices, multiplexin g into a single cell stream carried over two high speed LVDS serial interfaces.
- Cell read/write to both LVDS links available through the processor port. Provides optional hardware assisted CRC32 calculation across cells to support an embedded inter-processor communication channel across the LVDS links. PHY/FRAMER INTERFACES One of three modes can be selected:
- 8/16 bit, 33 MHz UTOPIA L2 bus master (also supports expanded length cells).
- 8/16 bit, 52 MHz extended UTOPIA L2 bus slave (compatible with PM7351 S/UNI-VORTEX ).
- 16 port, 4 pin clocked serial data interface (Tx & Rx), with integrated I.432 ATM cell delineation. LVDS INTERFACES
- Dual 4 wire LVDS serial transceivers each operating at up to 200 Mb/s.
- Operates across PCB or backplane traces, or across up to 10 meters of 4 wire twisted pair cabling for inter-shelf communications.
- F u l ly integrated LVDS clock synthesis and recovery. No external analog components are required.
- Usable bandwidth (excludes system overhead) of 186 Mb/s. LVDS TRANSMIT DIRECTION
- Simple round-robin multiplex of up to
32 PHYs (or 16 clock/data interfaces)
plus the microprocessor port’s cell transfer buffer.
- Multiplexed cell stream broadcast to both LVDS simultaneously. TXD1+ TXD1- TX8K RX8K D[7:0] RSTB RDB WRB CSB ALE A[8:0] INTB IENB JTAG Test Access Port TRSTB TMS TDI TDO IADDR[4:0] IAVALID IDAT[15:0] IPRTY ISOC ISX SCI-PHY Receive Master/ Transmit Slave OENB OADDR[4:0] OAVALID ODAT[15:0] OPRTY OSOC OSX OMASTER OFCLK SCI-PHY Transmit Master/ Receive Slave TCK Per-PHY Buffers
2 Cell
4 Cell
LTXD[15:0] LTXC[15:0] LRXC[15:0] LRXD[15:0] Elastic Store Cell Processor IBUS8 OBUS8 Time-Sliced ATM Transmission Convergence Microprocessor Interface BLOCK DIAGRAM
Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 PM7350 S/UNI-DUPLEX To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com PMC-990147 (P2) 1999 PMC-Sierra, Inc. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE Dual Serial Link, PHY MultiplexerDual Serial Link, PHY Multiplexer
- 6 bit port ID prepended to each cell for use by ATM layer to identify cell source (1 of 32 PHYs or processor).
- Back-pressure provided by far end (active link only) to prevent overflow of far end receiver. LVDS RECEIVE DIRECTION
- The LVDS link marked as "spare" is monitored for errors, PHY cells are discarded, microprocessor port cells are accepted.
- Individual PHY and microprocessor FIFO back-pressure indications are sent to the far end to prevent FIFO overflows. Per stream backpressure prevents head-of-line blockin
- Cells received from the active LVDS link are forwarded to the appropriate PHY, bit serial interface, or the microprocessor port as specified b y a 6 bit port ID added to each cell at the far end device.
APPLICATIONS
- S i ngle shelf or multi-shelf Digital Subscriber Loop Access Multiplexer (DSLAM ).
- ATM/frame/IP switch or multiservice access multiplexer.
- UMTS wireless base station and base station controller. modem #1 modem #2 modem #N UTOPIA Bus Master PM7350 S/UNI-DUPLEX Bus Slave or Bus Master PM7350 S/UNI-DUPLEX
4 Wire
INTER-SHELF UTOPIA BUS EXTENSION MULTI-SHELF 1024 LINE ATM DSLAM Common Card, working S/UNI-VORTEX S/UNI-VORTEX S/UNI-ATLAS S/UNI-PLUS processor RAM RAM /G01/G01 /G01 Common Card, spare UTOPIA Line Cards xDSL PHY xDSL PHY S/UNI-DUPLEX processor /G01/G01 /G01 Clock/Data Line Cards modem modem S/UNI-DUPLEX processor /G01 /G01 /G01 S/UNI-VORTEX S/UNI-VORTEX S/UNI-APEX S/UNI-ATLAS S/UNI-PLUS processor RAM RAM /G01 /G01 /G01 S/UNI-APEX