PM25LV512 PMC | Alldatasheet
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Technical content
512 Kbit / 1 Mbit 3.0 Volt-only, Serial Flash Memory With 25 MHz SPI Bus Interface PMC FEA TURES
- Single Power Supply Operation - Low voltage range: 2.7 V - 3.6 V
- Memory Organization - Pm25LV512: 64K x 8 (512 Kbit) - Pm25LV010: 128K x 8 (1 Mbit) Cost Effective Sector/Block Architecture - Uniform 4 Kbyte sectors - Uniform 32 Kbyte blocks (8 sectors per block) - Two blocks with 32 Kbytes each (512 Kbit) - Four blocks with 32 Kbytes each (1 Mbit) - 128 pages per block Serial Peripheral Interface (SPI) Compatible - Supports SPI Modes 0 (0,0) and 3 (1,1) High Performance Read - 25 MHz clock rate (maximum) Page Mode for Program Operations - 256 bytes per page Block Write Protection - The Block Protect (BP1, BP0) bits allow part or entire of the memory to be configured as read-only. Hardware Data Protection - Write Protect (WP#) pin will inhibit write operations to the status register
- Page Program (up to 256 Bytes) - Typical 2 ms per page program time Sector, Block and Chip Erase - Typical 40 ms sector/block/chip erase time Single Cycle Reprogramming for Status Register - Build-in erase before programming High Product Endurance - Guarantee 100,000 program/erase cycles per single sector (preliminary) - Minimum 20 years data retention Industrial Standard Pin-out and Package - 8-pin JEDEC SOIC - 8-contact WSON - Optional lead-free (Pb-free) packages GENERAL DESCRIPTION The Pm25LV512/010 are 512 Kbit/1 Mbits 3.0 Volt-only serial Flash memories. These devices are designed to use a single low voltage, range from 2.7 Volt to 3.6 Volt, power supply to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers as well. The device is optimized for use in many commercial applications where low-power and low-voltage operation are essential. The Pm25LV512/010 is enabled through the Chip Enable pin (CE#) and accessed via a 3-wire interface consisting of Serial Data Input (Sl), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are com- pletely self-timed. Block Write protection for top 1/4, top 1/2 or the entire memory array (1M) or entire memory array (512K) is enabled by programming the status register. Separate write enable and write disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Programmable Microelectronics Corp. 1 Issue Date: December, 2003, Rev: 1.3 Pm25LV512 / Pm25LV010 The Pm25LV512/010 are manufactured on PMC’s advanced nonvolatile CMOS technology, P-FLASH™. The de- vices are offered in 8-pin JEDEC SOIC and 8-contact WSON packages with operation frequency up to 25 MHz.
2Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 PIN DESCRIPTIONS LOBMYSE PYTN OITPIRCSED #ECT UPNI rofseirtiucriclanretnis'ecivedehtsetavitcawolseog#EC:elbanEpihC otnisehctiwsdnaecivedehtstcelesedhgihseog#EC.noitarepoecived tonsiecivedehtnehW.noitpmusnocrewopehtecuderotedomybdnats ehtdna,)lS(niptupnilairesehtaivdetpeccaebtonlliwatad,detceles .etatsecnadepmihgihaniniamerlliw)OS(niptuptuolaires KCST UPNIk colCataDlaireS IST UPNIt upnIataDlaireS OST UPTUOt uptuOataDlaireS DNGd nuorG ccVy lppuSrewoPeciveD #PWT UPNI lla,"1"sitibNEPWdnawolotthguorbnip#PWehtnehW:tcetorPetirW .detibihnieraretsigersutatsehtotsnoitarepoetirw #DLOHT UPNI tuohtiwecivedretsamehthtiwnoitacinummoclairesesuaP:dloH .ecneuqeslairesehtgnitteser CONNECTION DIAGRAMS 8-Pin SOIC Vcc HOLD# SCK SI SO GND WP# CE# 8-Contact WSON Vcc HOLD# SCK SI SO GND WP# CE# Top View
3Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 PRODUCT ORDERING INFORMA TION Pm25L Vxxx -25 S C E Temperature Range C = Commercial (0°C to +70°C) Package Type S = 8-pin SOIC (8S) Q = 8-contact WSON (8Q) Operating Speed
25 MHz
Pm25LV512 (512 Kbit) Pm25LV010 (1 Mbit) rebmuNtraPy cneuqerFgnitarepO) zHM(e gakcaPe gnaRerutarepmeT ECS52-215VL52mP laicremmoC )C°07+otC°0( CS52-215VL52mP ECQ52-215VL52mP CQ52-215VL52mP ECS52-010VL52mP CS52-010VL52mP ECQ52-010VL52mP CQ52-010VL52mP Environmental Attribute E = Lead-free (Pb-free) Package Blank = Standard Package
4Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 BLOCK DIAGRAM High Voltage Generator Control Logic Serial /Parallel convert Logic Address Latch & Counter 2KBit Page Buffer Status Register Memory Array Y-DECODER X-DECODER Instruction Decoder SPI Chip Block Diagram
term definitions are in the following section. MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the Pm25LV512/010 always operates as a slave. MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. contains the op-code that defines the operations to be performed. reinitialize the serial communication. Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven, High or Low as appropriate. Figure 1. Bus Master and SPI Memory Devices
Table 1. Instruction Set for the Pm25LV512/010 6800 type series of microcontrollers. SECTOR ERASE, BLOCK ERASE, CHIP ERASE, and WRSR are write instructions for Pm25LV512/010. Table 2. Product Identification (7Fh), each bit been shifted out during the falling edge of Serial Clock (SCK).
Table 4. Read Status Register Bit Definition only. The locked-out block and the corresponding status register control bits are shown in Table 5. regular memory cells (e.g., WREN, RDSR). instructions must therefore be preceded by the WREN instruction. commands. The WRDI instruction is independent of the status of the WP# pin. Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. During internal write cycles, all other commands will be ignored except the RDSR instruction. Table 3. Status Register Format
Table 6. WPEN Operation WPEN bits. In order to write the status register, the device must first be write enabled via the WREN instruction. completion of the WRSR cycle. Table 5. Block Write Protect Bits
continuous READ instruction. FR , during the falling edge of SCK (Serial Clock). READ instruction is terminated by driving CE# high. ming cycle, all commands will be ignored except the RDSR instruction. transition of the CE# pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. write disable state at the completion of the PROGRAM cycle. Table 7. Address Key
Table 8. Block Addresses every byte in all blocks that are not locked out. First, the device must be write enabled via the WREN instruction. the write disable state at the completion of the CHIP ERASE. toggle during HOLD). Inputs to the Sl pin will be ignored while the SO pin is in the high impedance state.
12Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 DC AND AC OPERA TING RANGE ABSOLUTE MAXIMUM RA TINGS (1) Notes: 1. Stresses under those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. The functional operation of the device or any other conditions under those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. Maximum DC voltage on input or I/O pins are V CC + 0.5 V. During voltage transitioning period, input or I/O pins may overshoot to VCC + 2.0 V for a period of time up to 20 ns. Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period, input or I/O pins may undershoot GND to -2.0 V for a period of time up to 20 ns. saiBrednUerutarepmeT C°521+otC°56- erutarepmeTegarotS C°521+otC°56- erutarepmeTgniredloSdaeLtnuoMecafruS egakcaPdradnatSs dnoceS3C°042 egakcaPeerf-daeLs dnoceS3C°062 sniPllAnodnuorGottcepseRhtiwegatloVtupnI )2( VotV5.0- CC V5.0+ dnuorGottcepseRhtiwegatloVtuptuOllA VotV5.0- CC V5.0+ V CC )2( V0.6+otV5.0- rebmuNtraP 010/215VL52mP erutarepmeTgnitarepO C°07otC°0 ylppuSrewoPccV V6.3-V7.2
13Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 DC CHARACTERISTICS Applicable over recommended operating range from: TAC = 0°C to +70°C, VCC = +2.7 V to +3.6 V (unless otherwise noted). lobmySr etemaraPn oitidnoCn iMp yTx aMs tinU I 1CC tnerruCdaeRevitcAccVV CC nepO=OS,zHM52taV6.3=0 15 1A m I 2CC tnerruCesarE/margorPccVV CC nePO=OS,zHM52taV6.3=5 10 3A m I 1BS SOMCtnerruCybdnatSccVV CC V=#EC,V6.3= CC 1.05 A µ I 2BS LTTtnerruCybdnatSccVV CC V=#EC,V6.3= HI Vot CC 50.03 A m IIL tnerruCegakaeLtupnIV NI VotV0= CC 1A µ IOL tnerruCegakaeLtuptuOV NI VotV0= CC T, CA C°07otC°0=1 A µ V LI egatloVwoLtupnI5 .0-8 .0V V HI egatloVhgIHtupnIV 7.0 CC V CC 3.0+V V LO egatloVwoLtuptuO V6.3<CCV<V7.2 ILO Am1.2=5 4.0V V HO egatloVhgiHtuptuOI HO Aµ001-=V CC 2.0-V
14Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 lobmySr etemaraPn iMp yTx aMs tinU fRF rofycneuqerFkcolC DAER_TSAF 05 2z HM fR snoitcurtsniDAERrofycneuqerFkcolC0 0 2z HM tIR emiTesiRtupnI 02s n tIF emiTllaFtupnI 02s n t HKC emiThgiHKCS0 2s n t LKC emiTwoLKCS0 2s n t HEC emiThgiHEC5 2s n tSC emiTputeSEC5 2s n tHC emiTdloHEC5 2s n tSD emiTputeSnIataD5 s n tHD emiTdloHniataD5 s n tSH emiTputeSdloH5 1s n tDH emiTdloH5 1s n tV dilaVtuptuO 51s n tHO emiTdloHtuptuO0 s n tZL ZwoLtuptuOotdloH 002s n tZH ZhgiHtuptuOotdloH 002s n t SID emiTelbasiDtuptuO 001s n tCE emiTesarEpihC/kcolB/retceS0 40 01s m tpp emiTmargorPegaP2 5 s m tw emitretsigeRsutatSetirW0 40 01s m AC CHARACTERISTICS Applicable over recommended operating range from TA = 0°C to +70°C, VCC = +2.7 V to +3.6 V C L = 1TTL Gate and 30 pF (unless otherwise noted).
15Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 AC CHARACTERISTICS (CONTINUED) AC WAVEFORMS (1) Note: 1. For SPI Mode 0 (0,0) OUTPUT TEST LOAD INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL VALID IN CE# V IL V IH SCK V IH V IH V OH V IL V IL V OL SI SO tCS tCKH tCKL tCEH tDHtDS tV tDIStOH HI-ZHI-Z tCH 3.3 V 1.8 K 1.3 K OUTPUT PIN 30 pF 3.0 V 0.0 V 1.5 V AC Measurement Level Input
16Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 AC CHARACTERISTICS (CONTINUED) tHD tHD tHS tHS tHZ tLZ CE# SCK HOLD# SO HOLD Timing pyTx aMs tinUs noitidnoC C NI 46 F pV NI V0= C TUO 82 1F pV TUO V0= PIN CAPACITANCE ( f = 1 MHz, T = 25°C ) Note: These parameters are characterized but not 100% tested.
17Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 TIMING DIAGRAMS SCK SI SO INSTRUCTION = 0000 0110b HI-Z CE# WREN Timing WRDI Timing CE# SCK SI SO INSTRUCTION = 0000 0100b HI-Z nnnnnnN 01 8 31 38 39 46 47 54 HIGH IMPEDANCE Manufacture ID1 Device ID Manufacture ID2 SCK CE# SI SO INSTRUCTION 1010 1011b
3 Dummy Bytes
18Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 RDSR Timing CE# SCK SI 0 12 3 56 7 8 9 10 11 12 13 144 INSTRUCTION = 0000 0101b SO 765 432 10HIGH IMPEDANCE DATA OUT MSB 0 1 2 3 5 6 7 8 9 10 11 12 13 144 15 76 54 32 10 DATA IN INSTRUCTION = 0000 0001b HIGH IMPEDANCE CE# SCK SI SO WRSR Timing READ Timing 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 36 35 37 38 ...23 22 21 3 2 1 0 765 43210 3-BYTE ADDRESS INSTRUCTION = 0000 0011b HIGH IMPEDANCE CE# SCK SI SO
19Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 PAGE PROGRAM Timing 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 2075 2076 2077 2078 2079 076 532 2 1 14 3 023 22 21 1st BYTE DATA-IN 256th BYTE DATA-IN 3-BYTE ADDRESS INSTRUCTION = 0000 0010b HIGH IMPEDANCE CE# SCK SI SO FAST READ Timing 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 ...23 22 21 3 2 1 0 3-BYTE ADDRESS INSTRUCTION = 0000 1011b HIGH IMPEDANCE CE# SCK SI SO 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 765 3 0 765 43210 HIGH IMPEDANCE CE# SCK SI SO 4 1 765 43210 DATA OUT 1 DATA OUT 2 DUMMY BYTE
20Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 BLOCK ERASE Timing CHIP ERASE Timing 01 234 56789 1 0 1 1 28 29 30 31 0123212223 ... 3-BYTE ADDRESS INSTRUCTION = 1101 1000b HIGH IMPEDANCE CE# SCK SI SO 01234567 HIGH IMPEDANCE SCK CE# SI SO INSTRUCTION = 1100 0111b 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 0123212223 ... 3-BYTE ADDRESS INSTRUCTION = 1101 0111b HIGH IMPEDANCE CE# SCK SI SO SECTOR ERASE Timing
21Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 PROGRAM/ERASE PERFORMANCE retemaraPt inUp yTx aMs krameR emiTesarErotceSs m0 40 01n oitelpmocesareotdnammocesaregnitirwmorF emiTesarEkcolBs m0 40 01n oitelpmocesareotdnammocesaregnitirwmorF emiTesarEpihCs m0 40 01n oitelpmocesareotdnammocesaregnitirwmorF emiTgnimmargorPegaPs m25 margorpotdnammocmargorpgnitirwmorF noitelpmoc retemaraPn iMp yTt inUd ohteMtseT ecnarudnE0 00,001 )2( selcyC7 11AdradnatSCEDEJ noitneteRataD0 2s raeY3 01AdradnatSCEDEJ ledoMydoBnamuH-DSE0 00,2s tloV4 11AdradnatSCEDEJ ledoMenihcaM-DSE0 02s tloV5 11AdradnatSCEDEJ pU-hctaL I+001 1CC Am8 7dradnatSCEDEJ Note: These parameters are characterized and are not 100% tested. Note: 1. These parameters are characterized and are not 100% tested. 2. Preliminary specification only and will be formalized after cycling qualification test. RELIABILITY CHARACTERISTICS (1)
22Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 End View 5.00 4.80 Top View Side View 4.00 3.80 6.20 5.80 1.75 1.35 0.25 0.10 0.51 0.33
1.27 BSC
0.25 0.19 1.27 0.40 45 º PACKAGE TYPE INFORMA TION 8-Pin JEDEC Small Outline Integrated Circuit (SOIC) Package (measure in millimeters)
23Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 PACKAGE TYPE INFORMA TION (CONTINUED) 8-Contact Ulta-Thin Small Outline No-Lead (WSON) Package (measure in millimeters) 5.00 BSC Top View Side View 0.48 0.35 6.00 BSC 0.80 0.70 0.25 0.19 1.27 BSC Bottom View Pin 1 0.75 0.50 4.00 3.40
24Programmable Microelectronics Corp. Issue Date: December, 2003, Rev: 1.3 PMC Pm25LV512/010 REVISION HISTOR Y etaD. oNnoisiveRs egnahCfonoitpircseD. oNegaP 2002,rebotcO0 .1c epSyranimilerP,noitacilbupweNl lA 2002,rebmeceD1 .1e saeleRlamroFl lA 3002,nuJ2 .1n oitpoegakcapNOSWdeddA3 2,3,2,1 3002,rebmeceD3 .1 snoitpoegakcapeerf-daeLdeddA2 1,3,1 000,05morfselcycesare/margorpdeetnarugdedargpU )yranimilerp(000,001ot 12,1 noisnemidegakcapdewarderdnadetadpU3 2,22