PM6341 PMC | Alldatasheet

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Technical content

PMC -920109(R6) E1 TRANSCEIVER © 1998 PMC-Sierra, Inc. March, 1998 PM6341 Summary Information E 1XC BLOCK DIAGRAM

FEATURES

  • Monolithic single chip device which integrates a full-featured E1 framer with on-chip analog line interface.
  • Provides frame synchronization and frame generation for a G.704/G.706

2.048 Mbit/s signal with capability to

support the optional signalling and CRC multiframes.

  • Supports HDB3 or AMI line coding and accepts gapped data streams to support higher rate demultiplexing.
  • Supports both 75 Ohm and 120 Ohm G.703 line interfaces.
  • Provides Channel Associated Signalling extraction/insertion, programmable idle code substitution, digital milliwatt code substitution, data inversion and up to 3 multiframes of signalling debounce on a per channel basis.
  • Optionally extracts/inserts the datalink from/to timeslot 16 to receive/transmit Common Channel Signalling.
  • Pin compatible with the PM4341A T1XC T1 Transceiver.
  • Software compatible with the PM6344 EQUAD E1 Framer, and PM6388 EOCTL E1 Framer.
  • Provides an 8-bit microprocessor bus interface for configuration, control and status monitoring.
  • Low-power 5V CMOS technology.
  • Available in a high density 80-pin (14 by 14mm) PQFP or in a 68-pin PLCC package.
  • E1 & E3 Multiplexers
  • Digital Loop Carriers
  • E1 Frame Relay Interfaces
  • E1 ATM UNI Interfaces
  • E1 Channel Service Units (CSUs) and Data Service Units (DSUs)
  • Digital Access and Cross-Connect Systems (DACS) and Electronic Digital Cross-Connect Systems (EDSX)
  • SDH Add/Drop Multiplexers (ADM)
  • ISDN Primary Rate Interfaces (PRI)
  • Digital Private Branch Exchanges (PBX)
  • E1 & E3 Test Equipment

APPLICATIONS

  • Provides indications of loss of signal, loss of frame alignment (OOF), loss of signalling multiframe alignment and loss of CRC multiframe alignment.
  • Declares red and AIS alarms using Q.516 recommended integration periods
  • Supports line and path performance monitoring according to ITU-T recommendations. Accumulators are provided for CRC-4 errors, Far End Block Errors, Frame sync errors, and Line Code Violations.
  • Provides an integral HDLC/LAPD interface which may be used for terminating a CCS or National Bits datalink.
  • Provides a two frame elastic store for jitter and wander attenuation.
  • Provides programmable trunk conditioning on a per channel basis. TRANSMIT SECTION
  • Supports transmission of AIS, timeslot 16 AIS, remote alarm signal or remote multiframe alarm signal.
  • Provides an integral HDLC/LAPD interface which may be used for generating a CCS or National Bits datalink.
  • Provides an integrated digital phase locked loop for generation of a low jitter transmit clock.
  • Provides a FIFO buffer for jitter attenuation and rate conversion.
  • Provides programmable trunk conditioning which forces trouble code substitution and signalling conditioning on a per channel basis. XCLK/VCLK BRFPI BRCLK BRPCM/BRDP BRSIG/BRDN BRFPO RCLKO RFP RDPCM/RPCM RDLCLK/ RDLEOM RDLSIG/ RDLINT RCLKI RDP/ RDD/ SDP RDN/RLCV/ SDN RAS REF RRC RFDL HDLC RECEIVER CDRC CLOCK AND DATA RECOVERY PMON PERF MONITOR COUNTERS SIGX SIGNALLING EXTRACT, TRUNK CONDITION ELST ELASTIC STORE BRIF BACK- PLANE RECEIVE INTER- FACE RSLC ANALOG PULSE SLICER TDP/TDD TCLKO TDN/TFLG TCLKI TAN TAP BTPCM/BTDP BTCLK BTSIG/BTDN TDLSIG/ TDLINT TDLCLK/ TDLUDR INTB D(7-0) A(7-0) RDB WRB CSB ALE RSTB BTFP TC XFDL HDLC TRANS- MITTER TRAN TRANSMITTER: FRAME GENERATION, ALARM INSERTION, TRUNK CONDITIONING LINE CODING PCSC PER-CHAN CONTR: SIGNAL, IDLE CONT DTIF DIGITAL TRANSMIT INTERFACE MPIF MICRO- PROCESSOR INTERFACE INTERNAL BUS RECEIVER TRANSMITTER XBOC BIT- ORIENTED CODE TRANS DRIF DIGITAL RECEIVE INTERFACE RBOC BIT ORIENTED CODE DETECTOR FRMR FRAMER: FRAME ALIGNMENT, ALARM DETECTION BTIF BACK- PLANE TRANS- MIT INTER- FACE TOPS TIMING OPTIONS DJAT DIGITAL JITTER ATTENUATOR XPLS ANALOG PULSE GENERATOR

All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com Head Office: PMC-Sierra, Inc. Suite 105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn:Document Coordinator PMC-920109(R6) © 1998 PMC-Sierra, Inc. March, 1998 PM6341 E1XC Summary Information TYPICAL APPLICATIONS: 1/0 CROSS-CONNECT WITH E1 INTERFACE: FULLY CHANNELIZED QUAD E1 HDLC CARD: STi1 STi6 STi7STi2 STi8STi3 STo2 STi4 STo3 STi5 Digital Crosspoint Switch STo4 STo5 STo6 STo7 STo8STo1 TAP TAN RAS REF BRPCMBRSIGBTPCMBTSIG Transmit Receive TAP TAN RAS REF BRPCMBRSIGBTPCMBTSIG PM6341 E1XC Transmit Receive TAP TAN RAS REF BRPCMBRSIGBTPCMBTSIG Transmit Receive TAP TAN RAS REF BRPCMBRSIGBTPCMBTSIG Transmit Receive PMC PM6341 E1XC PMC PM6341 E1XC PMC PM6341 E1XC PMC PM6341 E1XC PMC Packet Memory Processor PCI Bus PM7366 FREEDM-8 HDLC Controller PMC PM6341 E1XC PMC PM6341 E1XC PMC PM6341 E1XC PMC