PLC42VA12

PLC42VA12 PHILIPS | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 20

Technical content

Features

• Security fuse

APPLICATIONS

• Mealy or Moore State Machines – Synchronous – Asynchronous
• Multiple, independent State Machines
• 10-bit ripple cascade
• Sequence recognition
• Bus Protocol generation
• Industrial control
• A/D Scanning PIN CONFIGURATIONS I0/ CLK 12 13 FA and N Pack- ages N = Plastic DIP (300mil-wide) FA = Ceramic DIP with Quartz Window (300mil-wide) 1234 12 13 14 15 16 17 18 262728 A Package I0/CLK GND I9/OE VCC N/C N/C N/C N/C I1I2 B0 B1 GND I9/ OE M0 M1 M8M9VCC A = Plastic Leaded Chip Carrier (450mil-square)

ORDERING INFORMATION

DESCRIPTION ORDER CODE DRAWING NUMBER 24-Pin Ceramic Dual In-Line with window, Reprogrammable (300mil-wide) PLC42VA12FA 1478A 24-Pin Plastic Dual In-Line, One Time Programmable (300mil-wide) PLC42VA12N 0410D 28-Pin Plastic Leaded Chip Carrier, One Time Programmable (450mil-wide) PLC42VA12A 0401F PAL is a registered trademark of Advanced Micro Devices, Inc.

63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 F C J K P R CKQ P A R M R M R M R M C K J K P R CKQ J K P R CKQ J K P R CKQ NOTE: Programmable Connection Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 74 LOGIC DIAGRAM

R M C K C K C K L A J K P R CKQ J K P R CKQ J K P R CKQ J K P R CKQ J K P R CKQ J K P R CKQ P B R M R M R M R M C K C K C K C K L B P M R M P M C K C K L M L M D M D M D M D M D M D M D M D M D M D M D D I9/OE I0/CLK CK CK CK CK CK CK CK CK CK CK Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 75 LOGIC DIAGRAM (Continued)

Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 76 FUNCTIONAL DIAGRAM P63 P0 FC Ln Pn R n CK n LM n PM n RM n CK n DM n DM n DB n I9/OE I0/CLK P R J CK K Q P R J CK K Q POLARITY CLK CONTROL OMC CONFIG. POLARITY CLK CONTROL OMC CONFIG. OE n En (X2) OE n En (X2) POLARITY X2 X2 X2 X2 X2 X2 X2 X2 X2X8 X8 X8 I1 – I8 M1 – M8 M0, M9 B0 – B1

+5V C L R 1 R 2 GND M Z M Z INPUTS In In B M B M OUTPUTS C 2C 1 DUT NOTE: C 1 and C2 are to bypass VCC to GND. VCC CK OE Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 77 ABSOLUTE MAXIMUM RATINGS 1 THERMAL RATINGS SYMBOL PARAMETER RATINGS UNIT VCC Supply voltage –0.5 to +7 VDC VIN Input voltage –0.5 to VCC +0.5 VDC VOUT Output voltage –0.5 to VCC +0.5 VDC IIN Input currents –10 to +10 mA IOUT Output currents +24 mA Tamb Operating temperature range 0 to +75 °C Tstg Storage temperature range –65 to +150 °C NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. AC TEST CONDITIONS VOLTAGE WAVEFORMS MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses 90% 10% 5ns5ns 5ns 5ns 90% 10% +3.0V +3.0V tR tF TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150°C 75°C 75°C

Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 79 AC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V; R1 = 238Ω , R2 = 170Ω TEST 2 PLC42VA12 SYMBOL PARAMETER FROM TO CONDITION (CL (pF)) MIN TYP 1 MAX UNIT Set-up Time tIS1 Input; dedicated clock (I, B, M) +/– CK+ 50 23 16 ns tIS2 Input; P-term clock (I, B, M) +/–(I, B, M) +/– 50 20 13 ns tIS33 Preload; dedicated clock (M) +/– CK+ 50 10 3.5 ns tIS43 Preload; P-term clock (M) +/– (I, B, M) +/– 50 2 –1.0 ns tIS53 Input through complement array; dedicated clock (I, B, M) +/– CK+ 50 50 34 ns tIS63 Input through complement array; P-term clock (I, B, M) +/–(I, B, M) +/– 50 40 30 ns Propagation Delay tPD1 Propagation Delay (I, B, M) +/–(I, B, M) +/– 50 20 35 ns tPD2 Propagation Delay with complement array (2 passes) (I, B,) +/– (I, B, M) +/– 50 36 55 ns tCKO1 Clock to Output; Dedicated clock CK+ (M) +/– 50 13 17 ns tCKO2 Clock to output; P-term clock (I, B, M) +/– (M) +/– 50 18 27 ns tRP1 Registered operating period; Dedicated clock (tIS1 + tCKO1 ) (I, B, M) +/– (M) +/– 50 29 40 ns tRP2 Registered operating period; P-term clock (tIS2 + tCKO2 ) (I, B, M) +/– (M) +/– 50 31 47 ns tRP3 3 Register preload operating period; Dedicated clock (tIS3 + tCKO1 ) (M) +/– (M) +/– 50 16.5 27 ns tRP4 3 Register preload operating period; P-term clock (tIS4 + tCKO2 ) (M) +/– (M) +/– 50 17 29 ns tRP5 3 Registered operating period with comple- ment array; dedicated clock (tIS5 + tCKO1 ) tRP6 3 Registered operating period with complement array; P-term clock (tIS6 + tCKO2 ) tOE1 Output Enable; from /OE pin4 /OE – (M) +/– 50 10 20 ns tOE2 Output Enable; from P-term4 (I, B, M) +/–(B, M) +/– 50 12.5 25 ns tOD1 Output Disable; from /OE pin4 /OE + Outputs dis- abled 5 10 20 ns tOD2 Output Disable; from P-term4 (I, B, M) +/–Outputs dis- abled 5 14.5 25 ns tPRO 3 Preset to Output (I, B, M) +/– (M) +/– 50 25 35 ns tPPR 3 Power-on Reset (Mn = 1) VCC + (M) +/– 50 15 ns Hold Time tIH1 Input (Dedicated clock) CK+ (I, B, M) +/– 50 0 –13 ns tIH2 Input (P-term clock) (I, B, M) +/–(I, B, M) +/– 50 5 –7.5 ns tIH33 Input; from Mn (Dedicated clock) CK+ (M) +/– 50 5 –1.5 ns tIH43 Input; from Mn (P-term clock) (I, B, M) +/– (M) +/– 50 10 3.5 ns Pulse Width tCKH1 Clock High; Dedicated clock CK+ CK– 50 10 5 ns tCKL1 Clock Low; Dedicated clock CK– CK+ 50 10 5 ns tCKH2 Clock High; P-term clock CK+ CK– 50 15 7 ns tCKL2 Clock Low; P-term clock CK– CK+ 50 15 7 ns tPRH 3 Width of preset/reset input pulse (I, B, M) +/–(I, B, M) +/– 50 30 7 ns Notes on page 80.

Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 80 AC ELECTRICAL CHARACTERISTICS (Continued) 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V; R1 = 238Ω , R2 = 170Ω TEST 2 PLC42VA12 SYMBOL PARAMETER FROM TO CONDITION (CL (pF)) MIN TYP 1 MAX UNIT Frequency of Operation fCK1 Dedicated clock frequency C+ C+ 50 50 100 MHz fCK2 P-term clock frequency C+ C+ 50 33 71.4 MHz fMAX1 Registered operating frequency; Dedicated clock (tIS1 + tCKO1 ) (I, B, M) +/– (M) +/– 50 25 34.5 MHz fMAX2 Registered operating frequency; P-term clock (tIS2 + tCKO2 ) (I, B, M) +/– (M) +/– 50 21.3 32.3 MHz fMAX3 3 Register preload operating frequency; Dedicated clock (tIS3 + tCKO1 ) fMAX4 3 Register preload operating frequency; P-term clock (tIS4 + tCKO2 ) fMAX5 3 Registered operating frequency with complement array; Dedicated clock (tIS5 + tCKO1 ) fMAX6 3 Registered operating frequency with complement array; P-term clock (tIS6 + tCKO2 ) NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. These limits are not tested/guaranteed. 2. Refer also to AC T est Conditions (T est Load Circuit). 3. These limits are not tested, but are characterized periodically and are guaranteed by design. 4. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. BLOCK DIAGRAM MUX

64 LOGIC TERMS 41 CONTROL TERMS

65 X 105 PROGRAMMABLE AND ARRAY

64 X 32

(10) BYPASS K J P R L D CK JK/D OE Q Q I0/CLK I9/OE M0 – M9 B0 – B1 OMC

Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 81 OUTPUT MACRO CELL (OMC) OUTPUT SELECT MUX P R J CK K Q CLOCK SELECT MUX FROM AND ARRAY LOAD 1 M PRESET RESET CK OUTPUT ENABLE SELECT MUX 0 1 FROM OR ARRAY FROM OR ARRAY TO AND ARRAY FROM OR ARRAY TO AND ARRAY (REGISTER BYPASS) OE O E CLK M FC CONTROL JK/D MUX Output Macro Cell Configuration Philips Semiconductors unique Output Macro Cell design represents a significant advancement in the configurability of multi-function Programmable Logic Devices. The PLC42VA12 has 10 programmable Output Macro Cells. Each can be individually programmed in any of 5 basic configurations:

• Dedicated I/O (combinatorial) with feedback to AND array
• Dedicated Input
• Combinatorial I/O with feedback and Buried Register with feedback (register bypass)
• Registered Input
• Registered Output with feedback Each of the registered options can be further customized as J-K type or D-type, with either an internally derived clock (from the AND array) or clocked from an external source. With these additional programmable options, it is possible to program each Output Macro Cell in any one of 14 different configurations. These 14 configurations, combined with the fully programmable OR array, make the PLC42VA12 the most versatile and silicon efficient of all the Output Macro Cell-type PLDs. The most significant Output Macro Cell (OMC) feature is the implementation of the register bypass function. Any of the 10 J-K/D registers can be individually bypassed, thus creating a combinatorial I/O path from the AND array to the output pin. Unlike other Output Macro Cell-type devices, the register in the OMC is fully functional as a buried register. Furthermore, both the combinatorial I/O and the buried register have separate input paths (from the AND array) and separate feedback paths (to the AND array). This feature provides the capability to operate the buried register independently from the combinatorial I/O. The PLC42VA12 is ideally suited for both synchronous and asynchronous logic functions. Eleven clock sources – 10 driven from the AND array and one from an external source – make it possible to design synchronous state machine functions, event-driven state machine functions and combinatorial (asynchronous) functions all on the same chip. Sophisticated control functions support individual OE control and Reset functions from the AND array. OE control is also available from the I9/OE pin. Register Preset and Load functions are controlled from the AND array, in 2 banks of 4 for OMCs M1 – M8. Output Macro Cells M0 and M9 have individual Preset and Load Control terms. Output Polarity for the combinatorial I/O paths is configurable via 12 programmable EX-OR gates. The output of each register can be configured as inverting (active Low) or non-inverting (active High) via manipulation of the logic equations. The output of each buried register can also be configured as inverting or non-inverting via the input buffer which feeds back to the AND array.

Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 82 OUTPUT MACRO CELL PROGRAMMABLE OPTIONS OMC Programmable Options For purposes of programming, the Output Macro Cell should be considered to be partitioned into five separate blocks. As shown in the drawing titled “Output Macro Cell Programmable Options”, the programmable blocks are: Register Select Options, Polarity Options, Clock Options, OMC Configuration Options and Output Enable Control Options. There is one programmable location associated with each block except the Output Enable Control block which has two programmable fuse locations per OMC. The following drawings detail the options associated with each programmable block. The associated programming codes are also included. The table titled “Output Macro Cell Configurations” (page 87) lists all the possible combinations of the five programmable options. OUTPUT MACRO CELL REGISTER SELECT OPTIONS POLARITY OPTIONS OMC CONFIGURATION OPTIONS OUTPUT ENABLE CONTROL OPTIONS CLOCK OPTIONS OUTPUT M ARCHITECTURAL OPTIONS REGISTER SELECT OPTIONS Register Select Options Each OMC Register can be configured either as a dedicated D-type or a J-K flip-flop. The Flip-Flop Control term, Fc, provides the option to control each Register dynamically—switching from D-type to J-K type, based on the Fc control signal. Register Preset and Reset are controlled from the AND array. Each OMC has an individual Reset Control term (RMn). The Register Preset function is controlled in two banks of 4 for OMCs M1 – M3 and M4 – M8 (via the control terms PA and PB). OMCs M0 and M9 have individual control terms (PM0 and PM9 respectively). REGISTER MODE (D or JK) D-TYPE CODE A FC CONTROL P-TERM L REGISTER MODE (D or JK) JK-TYPE CODE FC CONTROL P-TERM – CK RP Q CLOCK OPTIONS OMC CONFIG. OPTIONS OUTPUT CONTROL OPTIONS RP DFROM OR ARRAY FROM AND ARRAY CK RP Q CLOCK OPTIONS OMC CONFIG. OPTIONS OUTPUT CONTROL OPTIONS RP J FROM OR ARRAY FROM AND ARRAY K Notes on page 87.

Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 83 REGISTER SELECT OPTIONS (Continued) REGISTER MODE (D or JK) DYNAMICALLY CONTROLLABLE CODE A FC CONTROL P-TERM L or H CK RP Q CLOCK OPTIONS OMC CONFIG. OPTIONS OUTPUT CONTROL OPTIONS RP DFROM OR ARRAY FROM AND ARRAY CK RP Q CLOCK OPTIONS OMC CONFIG. OPTIONS OUTPUT CONTROL OPTIONS RP J FROM OR ARRAY FROM AND ARRAY K FC FC = LOW F C = HIGH POLARITY OPTIONS (for Combinatorial I/O Configurations Only1) Polarity Options When an OMC is configured as a Combinatorial I/O with Buried Register, the polarity of the combinatorial path can be programmed as Active-High or Active-Low. A configurable EX-OR gate provides polarity control. If an OMC is configured as a Registered Output, /Q is propagated to the output pin. Note that either Q or /Q can be fedback to the AND array by manipulating the feedback logic equations. (TRUE or COMPLEMENT). POLARITY ACTIVE-HIGH (NON-INVERTING) CODE H 4 POLARITY ACTIVE-LOW (INVERTING) CODE OMC CONFIG. OPTIONS FROM OR ARRAY OUTPUT SELECT OPTIONS M OMC CONFIG. OPTIONS FROM OR ARRAY OUTPUT CONTROL OPTIONS M CLOCK OPTIONS Clock Options In the unprogrammed state, all Output Macro Cell clock sources are connected to the External Clock pin (I0/CLK pin 1). Each OMC can be individually programmed such that its P-term Clock (CKn) is enabled, thus disabling it from the External Clock and providing event-driven clocking capability. This feature supports multiple state machines, clocked at several different rates, all on one chip, or the ability to collect large amounts of random logic, including 10 separately clocked flip-flops. CLK OPTIONS EXTERNAL CLOCK (FROM PIN 1) CODE A CLK OPTIONS P-TERM CLOCK CODE CK Q CLK OMC CONFIG. OPTIONS OUTPUT CONTROL OPTIONS D (OR J) FROM OR ARRAY TO AND ARRAY (K) REGISTER SELECT OPTIONS CK Q CK OMC CONFIG. OPTIONS OUTPUT CONTROL OPTIONS D (OR J) FROM OR ARRAY TO AND ARRAY (K) REGISTER SELECT OPTIONS Notes on page 87.

Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 84 OUTPUT MACRO CELL CONFIGURATION OPTIONS COMBINATORIAL OUTPUT WITH BURIED REGISTER (D or JK) Note that an OMC can be configured as either a Combinatorial I/O (with Buried Register) or a Registered Output with feedback and it can still be used as a Registered Input. By disabling the outputs via any OE control function, the M pin can be used as an input. When the Load Control P-term is asserted HIGH, the register is preloaded from the M pin(s). When the LC P-term is Active-Low and the output is enabled, the OMC will again function as configured (either a combinatorial I/O or a registered output with feedback). This feature is suited for synchronizing input signals prior to commencing a state sequence. OMC CONFIGURATION REGISTERED INPUT CODE A or •5 LOAD CONTROL P-TERM H 6 OMC Configuration Options Each OMC can be configured as a Registered Output with feedback, a Registered Input or a Combinatorial I/O with Buried Register. Dedicated Input and dedicated I/O configurations are also possible. When the Combinatorial I/O option is selected, (the Register Bypass option), the Buried Register remains 100% functional, with its own inputs from the AND array and a separate feedback path. This unique feature is ideal for designing any type of state machine; synchronous Mealy-types that require both Buried and Output Registers, or asynchronous Mealy-types that require buried registers and combinatorial output functions. Both synchronous and asynchronous Moore-type state machines can also be easily accommodated with the flexible OMC structure. OMC CONFIGURATION CODE

• REGISTERED OUTPUT (D or JK) OMC CONFIGURATION CODE A L M CLOCK OPTIONS OUTPUT CONTROL OPTIONS TO AND ARRAY D CK Q CK Q OMC CONFIG. OPTIONS D (OR J) FROM OR ARRAY TO AND ARRAY (K) REGISTER SELECT OPTIONS M CLOCK OPTIONS CK Q D (OR J) FROM OR ARRAY TO AND ARRAY (K) REGISTER SELECT OPTIONS CLOCK OPTIONS FROM OR ARRAY OUTPUT CONTROL OPTIONS M COMBINATORIAL OPTIONS Notes on page 87.

Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 85 OUTPUT CONTROL OPTIONS Output Enable Control Options Similar to the Clock Options, the Output Enable Control for each OMC can be connected either to an external source (I9/OE, pin 13) or controlled from the AND array (P-terms DMn). Each Output can also be permanently enabled. Output Enable control for the two bi-directional I/O (B pins 10 and 11) is from the AND array only (P-terms DB0 and DB1 respectively). En FUSE ALWAYS ENABLED CODE OE CONTROL FUSE ALWAYS ENABLED CODE A En FUSE FROM P-TERM CONTROL CODE A or 0 OE FUSE FROM P-TERM CONTROL CODE En FUSE FROM OE PIN CODEOE CONTROL FUSE FROM OE PIN CODE A A OMC CONFIG. OPTIONS OE M TO AND ARRAY OMC CONFIG. OPTIONS M TO AND ARRAY OMC CONFIG. OPTIONS M TO AND ARRAY DM COMPLEMENT ARRAY DETAIL Complement Array Detail The complement array is a special sequencer feature that is often used for detecting illegal states. It is also ideal for generating IF-THEN-ELSE logic statements with a minimum number of product terms. The concept is deceptively simple. If you subscribe to the theory that the expressions (/A * /B * /C) and (A + B + C) are equivalent, you will begin to see the value of this single term NOR array. The complement array is a single OR gate with inputs from the AND array. The output of the complement array is inverted and fedback to the AND array (NOR function). The output of the array will be LOW if any one or more of the AND terms connected to it are active (HIGH). If, however, all the connected terms are inactive (LOW), which is a classic unknown state, the output of the complement array will be HIGH. Consider the product terms A, B and D that represent defined states. They are also connected to the input of the complement array. When the condition (not A and not B and not D) exists, the Complement Array will detect this and propagate an Active-High signal to the AND array. This signal can be connected to product term E, which could be used in turn to preset the state machine to known state. Without the complement array, one would have to generate product terms for all unknown or illegal states. With very complex state machines, such an approach can be prohibitive, both in terms of time and wasted resources.Notes on page 87. A B D E FCP0P1P61P62P63 TO OR ARRAY TO OMCs AND BIDIRECTIONAL I/O LM n PM n RM n

Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 86 LOGIC PROGRAMMING The PLC42VA12 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL and CUPL  design software packages also support the PLC42VA12 architecture. All packages allow Boolean and state equation entry formats. SNAP , ABEL and CUPL also accept, as input, schematic capture format. PLC42VA12 logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only. To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P , etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. Symbols for OMC configuration have been previously defined in the Architectural Options section. PROGRAMMING AND SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information. LOGIC IMPLEMENTATION “AND” ARRAY – (I), (B), (Qp) STATE DON’T CARE CODESTATE I, B, Q CODE L STATE I, B, Q CODESTATE INACTIVE 1 CODE O –H (T, FC , L, P , R, D)n I, B, Q I, B, Q I, B, Q (T, FC , L, P , R, D)n I, B, Q I, B, Q I, B, Q (T, FC , L, P , R, D)n I, B, Q I, B, Q I, B, Q (T, FC , L, P , R, D)n I, B, Q I, B, Q I, B, Q “COMPLEMENT” ARRAY – (C) ACTION TRANSPARENT CODEACTION PROPAGATE CODE ACTION GENERATE CODEACTION INACTIVE 1, 3 CODE O –A C C (Tn, FC ) C C (Tn, FC ) C C (Tn, FC ) C C (Tn, FC ) “OR” ARRAY – (J-K Type) QJ K Tn M = DISABLED ACTION HOLD CODE QJ K Tn M = DISABLED ACTION RESET CODE L QJ K Tn M = DISABLED ACTION SET CODE QJ K Tn M = DISABLED ACTION TOGGLE CODE O –H “OR” ARRAY “OR” ARRAY – (D-Type) QJ K Tn M = ENABLED Tn STATUS INACTIVE (RESET) CODE QJ K Tn M = ENABLED Tn STATUS ACTIVE (SET) CODE A Tn STATUS INACTIVE CODE Tn STATUS ACTIVE 1 CODE A Tn P, R, L (OR B) Tn P, R, L (OR B) Notes on page 87. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc.

Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 87 LOGIC IMPLEMENTATION (Continued) OUTPUT MACRO CELL CONFIGURATIONS PROGRAMMING CODES OUTPUT MACRO CELL CONFIGURATION REGISTER SELECT FUSE OMC CONFIGURATION FUSE POLARITY FUSE CLOCK FUSE Combinatorial I/O with Buried D-type register External clock source A • H or L A P-term clock source A • H or L • Combinatorial I/O with Buried J-K type register External clock source • • H or L A P-term clock source • • H or L • Registered Output (D-type) with feedback External clock source A A N/A A P-term clock source A A N/A • Registered Output (J-K type) with feedback External clock source • A N/A A P-term clock source • A N/A • Registered Input (Clocked Preload) with feedback External clock source A A or •5 Optional5 A P-term clock source A A or •5 Optional5 • OUTPUT CONTROL FUSES OUTPUT ENABLE CONTROL 8 CONFIGURATION OE CONTROL FUSE En FUSES CONTROL SIGNAL OMC controlled by /OE pin A A Output Enabled Low Output Disabled High OMC controlled by P-term • A or 0 Output Enabled High Output Disabled Low Output always Enabled A 0 Not Applicable NOTES: 1. This is the initial (unprogrammed) state of the device. 2. Any gate will be unconditionally inhibited if both the TRUE and COMPLEMENT fuses are left intact. 3. To prevent oscillations, this state is not allowed for Complement Array fuse pairs that are coupled to active product terms. 4. The OMC Configuration fuse must be programmed as Combinatorial I/O in order to make use of the Polarity Option. 5. Regardless of the programmed state of the OMC Configuration fuse, an OMC can be used as a Registered Input. Note that the Load Control P-term must be asserted Active-High. 6. Output must be disabled. 7. Program code definitions: A = Active (unprogrammed fuse) 0, • = Inactive (programmed fuse) – = Don’t Care (both TRUE and COMPLEMENT fuses unprogrammed) H = Active-High connection L = Active-Low connection 8. OE control for B0 and B1 (Pins 10 and 11) is from the AND array only.

tOD1,2 tCKL2 Gated Outputs Flip-Flop Outputs with External Clock Flip-Flop Outputs with P-term Clock 1.5V 1.5V 1.5V1.5V1.5V 1.5V VT 1.5V1.5V +3V +3V VOH VOL +3V P-TERM CK (I, B, M) M (OUTPUTS) tIH2 tIS2,6 tIS2,6 tCKH2 tRP2,6 tCKO2 tOE1,2 I, B, M (INPUTS) I, B, M, OE TERM OR OE PIN (OUTPUT ENABLE) ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ I, B (INPUTS) B, M (COMBINATORIAL OUTPUTS) I, B, M, OE TERM OR OE PIN (OUTPUT ENABLE) tPD tOE2 tOD2 1.5V 1.5V +1.5V+1.5V VT +3V VOH VOL +3V tOD1,2 tCKL1 1.5V 1.5V 1.5V1.5V1.5V 1.5V VT 1.5V1.5V +3V +3V VOH VOL +3V EXTERNAL CK M (OUTPUTS) tIH1 tIS1,5 tIS1,5 tCKH1 tRP1,5 tCKO1 tOE1,2 I, B, M (INPUTS) I, B, M, OE TERM OR OE PIN (OUTPUT ENABLE) Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 88 TIMING DIAGRAMS TIMING DEFINITIONS SYMBOL PARAMETER fCK1 Clock Frequency; External Clock fCK2 Clock Frequency; P-term Clock tCKH1 Width of Input Clock Pulse; External Clock tCKH2 Width of Input Clock Pulse; P-term Clock tCKL1 Interval between Clock pulses; External Clock tCKL2 Interval between Clock Pulses; P-term Clock tCKO1 Delay between the Positive Transition of External Clock and when M Outputs become valid. tCKO2 Delay between the Positive Transition of P-term Clock and when M Outputs become valid. tRP1 Delay between beginning of V alid Input and when the M outputs become Valid when using External Clock. tRP2 Delay between beginning of V alid Input and when the M outputs become Valid when using P-term Clock. tRP3 Delay between beginning of V alid Input and when the M outputs become Valid when using Preload Inputs (from M pins) and External Clock. tRP4 Delay between beginning of V alid Input and when the M outputs become valid when using Preload inputs (from M pins) and P-term Clock. tRP5 Delay between beginning of V alid Input and when the M outputs become Valid when using Com- plement Array and External clock. tRP6 Delay between beginning of V alid Input and when the M outputs become Valid when using Com- plement Array and P-term Clock. fMAX1 Minimum guaranteed Operating Frequency; Dedicated Clock fMAX2 Minimum guaranteed Operating Frequency; P-term Clock fMAX3 Minimum guaranteed Operating Frequency using Preload; Dedicated Clock (M pin to M pin) fMAX4 Minimum guaranteed Operating Frequency using Preload; P-term Clock (M pin to M pin) fMAX5 Minimum guaranteed Operating Frequency using Complement Array; Dedicated Clock fMAX6 Minimum Operating Frequency using Complement Array; P-term Clock tIH1 Required delay between positive transition of External Clock and end of valid input data.

Flip-Flop Input Mode (Preload) *Preset and Reset functions override Clock. However, M outputs may glitch with the first positive Clock Edge if tIS cannot be guaranteed by the user. ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ 1.5V 1.5V 1.5V1.5V 1.5V 1.5V 1.5V VOH VOL +3V +3V +5V 4.5V VCC M (OUTPUTS) I, B, M (INPUTS) P-TERM OR EXTERNAL CK tPPR tCKO1,2 tIH tIS tIS tCKH tCKL tCK1,2 ÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇ tCKH tIH3,4 (DIN) +3V +3V +3V +3V tCKL tIH3,4tIS3,4tOD1,2 VT 1.5V(FORCED D IN) tOE1,2 1.5V 1.5V 1.5V 1.5VI, B (LOAD SELECT) I, B, OE TERM OR OE PIN (OUTPUT ENABLE) L M (INPUT) P-TERM OR EXTERNAL CK Q 1.5V ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ 1.5V 1.5V1.5V 1.5V1.5V (RESET) (PRESET) (RESET) (PRESET) tIStIS* tPRH tPRO tCKO +3V +3V +3V VOH VOL I, B, M (INPUTS) P-TERM OR EXTERNAL CK PRESET/RESET (I, B, M INPUTS) Q M (OUTPUTS) Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 89 TIMING DIAGRAMS (Continued) TIMING DEFINITIONS (Continued) SYMBOL PARAMETER tIH2 Required delay between positive transition of P-term Clock and end of valid input data. tIH3 Required delay between positive transition of External Clock and end of valid input data when us- ing Preload Inputs (from M pins). tIH4 Required delay between positive transition of P-term Clock and end of valid input data when us- ing Preload Inputs (from M pins). tIS1 Required delay between begin- ning of valid input and positive transition of External Clock. tIS2 Required delay between begin- ning of valid input and positive transition of P-term Clock input. tIS3 Required delay between beginning of valid Preload input (from M pins) and positive transition of External Clock. tIS4 Required delay between beginning of valid Preload input (from M pins) and positive transition of P-term Clock input. tIS5 Required delay between beginning of valid input through Complement Array and positive transition of External Clock. tIS6 Required delay between beginning of valid input through Complement Array and positive transition of P-term Clock input. tOE1 Delay between beginning of Output Enable signal (Low) from /OE pin and when Outputs become valid. tOE2 Delay between beginning of Output Enable signal (High or Low) from OE P-term and when Outputs become valid. tOD1 Delay between beginning of Output Enable signal (HIGH) from /OE pin and when Outputs become disabled. tOD2 Delay between beginning of Output Enable signal (High or Low) from OE P-term and when Outputs become disabled. tPD Delay between beginning of valid input and when the Outputs be- come valid (Combinatorial Path). tPRH Width of Preset/Reset Pulse. tPRO Delay between beginning of valid Preset/Reset Input and when the registered Outputs become Preset (“1”) or Reset (“0”). tPPR Delay between VCC (after power-up) and when flip-flops become Reset to “0”. Note: Signal at Output (M pin) will be inverted.

Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 90 LOGIC FUNCTION 0 1 0 0 0 1 STATE REGISTER SR Sn + 1 PRESENT STATE A ⋅ B ⋅ C ⋅ . . . NEXT STATE Q2 Q1 Q0 K 0 = 0 RESET Q 1: J1 = 0 HOLD Q 2: J2 = 0 K 2 = 0 RESET Q 3: J3 = (Q3 ⋅ Q2 ⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . . NOTE: Similar logic functions are applicable for D mode flip-flops. FLIP-FLOP TRUTH TABLE OE Ln CK n Pn R n J K Q M H Hi-Z L X X X X X X L H L X X H L X X H L L X X L H X X L H L L ↑ L L L L Q Q L L ↑ L L L H L H L L ↑ L L H L H L L L ↑ L L H H Q Q H H ↑ L L L H L H* H H ↑ L L H L H L* +10V X ↑ X X L H L H X ↑ X X H L H L NOTES: 1. Positive Logic: (B0 ⋅/n636861723332000000000000B1...) 2. ↑ denotes transition for Low to High level. 3. X = Don’t care 4. * = Forced at Mn pin for loading the J-K flip-flop in the Input mode. The load control term, Ln must be enabled (HIGH) and the p-terms that are connected to the associated flip-flop must be forced LOW (disabled) during Preload. 5. At P = R = H, Q = H. The final state of Q depends on which is released first. 6. ** = Forced at Fn pin to load J/K flip-flop (Diagnostic mode). PLC42VA12 UNPROGRAMMED STATE A factory shipped unprogrammed device is configured such that all cells are in a conductive state. The following are: ACTIVE: – OR array logic terms – Output Macro Cells M1 – M8;

• D-type registered outputs (D = 0) – External clock path – Inputs: B0, B1, M0, M9 INACTIVE: – AND array logic and control terms (except flip-flop mode control term, FC ) – Bidirectional I/O (B0, B1);
• Inputs are active. Outputs are 3-Stated via the OE P-terms, D0 and D1.
• D-type registers (D = 0). – Output Macro Cells M0 and M9;
• Bidirectional I/O, 3-Stated via the OE P-terms, DM0 and DM9. The inputs are active. – P-term clocks – Complement Array – J-K Flip-Flop mode PROGRAMMING AND SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) in this data handbook for additional information. ERASURE CHARACTERISTICS (For Quartz Window Packages Only) The erasure characteristics of the PLC42VA12 devices are such that erasure begins to occur upon exposure to light with wavelength shorter than approximately 4000 Angstroms (Å). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000 – 4000Å range. Data shows that constant exposure to room level fluorescent lighting could erase a typical PLC42VA12 in approximately three years, while it would take approximately one week to cause erasure when exposed to direct sunlight. If the PLC42VA12 is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the window to prevent unintentional erasure. The recommended erasure procedure for the PLC42VA12 is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (Å). The integrated dose (i.e., UV intensity × exposure time) for erasure should be a minimum of 15Wsec/cm 2. The erasure time with this dosage is approximately 30 to 35 minutes using an ultraviolet lamp with a 12,000µW/cm 2 power rating. The device should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose a CMOS EPLD can be exposed to without damage is 7258Wsec/cm 2 (1 week @ 12000µW/cm 2). Exposure of these CMOS EPLDs to high intensity UV light for longer periods may cause permanent damage. The maximum number of guaranteed erase/write cycles is 50. Data retentions exceeds 20 years.

Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 91 PROGRAM TABLE

Philips Semiconductors Programmable Logic Devices Product specification PLC42VA12CMOS programmable multi-function PLD (42 × 105 × 12) October 22, 1993 92 SNAP RESOURCE SUMMARY DESIGNATIONS P63 P0 FC Ln Pn R n CK n LM n PM n RM n CK n DM n DM n DB n I9/OE I0/CK P R J CK K Q P R J CK K Q POLARITY CLK CONTROL OMC CONFIG. POLARITY CLK CONTROL OMC CONFIG. OE n OE n POLARITY X2 X2 X2 X2 X2 X2 X2 X2 X2X8 X8 X8 I1 – I8 M1 – M8 M0, M9 B0 – B1 DIN42 NIN42 NOR AND ANDFC CAND NTIM42 DTIM42 OR OR JKFFPR42 EXOR42 TNOO42 JKFFPR42 OR OR EXOR42 EXOR42 TNOU42 TNOU42 CK42 CK42 OEBUFF OENAND OEBUFF OENAND En (X2) En (X2)