PLC18V8Z PHILIPS | Alldatasheet
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Technical content
/C0109 /C0110 /C0114 PLC18V8Z Zero standby power CMOS versatile PAL devices Product specification Replaces data sheet PLC18V8Z35/PLC18V8ZI of Dec 19 1995, and data sheet PLC18V8Z25/PLC18V8ZI of Dec 19, 1995
1997 Aug 08
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
21997 Aug 08 853–2016 18258
DESCRIPTION
The PLC18V8Z is a universal PAL device featuring high performance and virtually zero-standby power for power sensitive applications. They are reliable, user-configurable substitutes for discrete TTL/CMOS logic. While compatible with TTL and HCT logic, the PLC18V8Z can also replace HC logic over the V CC range of 4.5 to 5.5V. The PLC18V8Z is a two-level logic element comprised of 10 inputs, 74 AND gates (product terms) and 8 output Macro cells. Each output features an “Output Macro Cell” which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. As a result, the PLC18V8Z is capable of emulating all common 20-pin PAL devices to reduce documentation, inventory, and manufacturing costs. A power-up reset function and a Register Preload function have been incorporated in the PLC18V8Z architecture to facilitate state machine design and testing. With a standby current of less than 100µA and active power consumption of 1.5mA/MHz, the PLC18V8Z is ideally suited for power sensitive applications in battery operated/backed portable instruments and computers. The PLC18V8Z is also processed to industrial requirements for operation over an extended temperature range of -40°C to +85°C and supply voltage of 4.5V to 5.5V. Ordering information can be found on the following page.
FEATURES
- 20-pin Universal Programmable Array Logic
- Virtually Zero-Standby-power – 20µA (typical)
- Available in DIP, PLCC, SOL (Small Outline), SSOP (Shrink Small Outline), and TSSOP (Thin Shrink Small Outline) packages
- Functional replacement for Series 20 PAL devices – IOL = 24mA
- Up to 18 inputs and 8 input/output macro cells
- Programmable output polarity
- Power-up reset on all registers
- Register Preload capability
- Synchronous Preset/Asynchronous Reset
- Security fuse to prevent duplication of proprietary designs
- Also available in 3V operation–the P3C18V8Z
APPLICATIONS
- Battery powered instruments
- Laptop and pocket computers
- Industrial control
- Medical Instruments
- Portable communications equipment PIN CONFIGURATIONS SP00544 10 11 D, DB, DH, N, Packages I0/CLK I8 F0 GND VCC I9/OE D = Plasitc Small Outline Large Package (300mil-wide) DB = Plastic Shrink Small Outline Package (5.3mm wide) DH = Plastic Thin Shrink Small Outline Package (4.4mm wide) N = Plastic Dual In-Line Package (DIP) (300mil-wide) 123 91 0 1 1 1 2 1 3 1920 A Package A = Plastic Leaded Chip Carrier F0 F1 F7V CC I9/ OE I0/ CLKI1I2 I8 GND PIN DESCRIPTIONS I Dedicated Input B Bidirectional input/output O Dedicated output D Registered output (D-type flip-flop) F Output/Input Macrocell CLK Clock Input OE Output Enable VCC Supply Voltage GND Ground PAL is a registered trademark of Advanced Micro Devices, Inc.
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
1997 Aug 08 3
ORDERING INFORMATION
20-Pin (300mil-wide) Plastic Dual In-Line Package, 25ns tPD PLC18V8Z25N SOT146-1 20-Pin (350mil square) Plastic Leaded Chip Carrier Package PLC18V8Z25A SOT380-1 20-Pin (300mil-wide) Plastic Small Outline Large Package PLC18V8Z25D SOT163-1 20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package PLC18V8Z25DB SOT339-1 20-Pin (4.4mm-wide) Plastic Thin Shrink Small Outline Package Commercial Tem perature Range PLC18V8Z25DH SOT360-1 20–Pin (300mil–wide) Plastic Dual In–Line Package. 35ns tPD Temperature R ange ± 5% Power Supplies PLC18V8Z35N SOT146–1 20–Pin (350mil square) Plastic Leaded Chip Carrier Package PLC18V8Z35A SOT380–1 20–Pin (300mil square) Plastic Small Outline Large Package Package PLC18V8Z35D SOT163–1 20–Pin (5.3mm–wide) Plastic Shrink Small Outline Package PLC18V8Z35DB SOT339–1 20–Pin (4.4mm–wide) Plastic Thin shrink Small Outline Package PLC18V8Z35DH SOT260–1 20-Pin (300mil-wide) Plastic Dual In-Line Package 25ns tPD PLC18V8ZIAN SOT146-1 20-Pin (350mil square) Plastic Leaded Chip Carrier Package PLC18V8ZIAA SOT380-1 20-Pin (300mil-wide) Plastic Small Outline Large Package PLC18V8ZIAD SOT163-1 20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package PLC18V8ZIADB SOT339-1 20-Pin (4.4mm-wide) Plastic Thin Shrink Small Outline Package Industrial Tem perature Range PLC18V8ZIADH SOT360-1 20–Pin (300mil–wide) Plastic Dual In–Line Package, 40ns tPD Temperature R ange ± 10% Power Supplies PLC18V8ZIN SOT146–1 20–Pin (350mil square) Plastic Leaded chip Carrier Package PLC18V8ZIA SOT380–1 20–Pin (300mil square) Plastic Small Outline Large Package PLC18V8ZZID SOT163–1 20–Pin (5.3mm–wide) Plastic Shrink Small Outline Package PLC18V8ZIDB SOT339–1 20–Pin (4.4mm–wide) Plastic Thin Shrink Small Outline Package PLC18V8ZIDH SOT360–1
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
1997 Aug 08 4
PAL DEVICE TO PLC18V8Z OUTPUT PIN CONFIGURATION CROSS REFERENCE PIN NO. PLC 18V8Z 16L8 16H8 16P8 16P8 16R4 16RP4 16R6 16RP6 16R8 16RP8 16L2 16H2 16P2 14L4 14H4 14P4 12L6 12H6 12P6 10L8 10H8 10P8
1 I0/CLK I CLK CLK CLK I I I I
19 F7 B B B D I I I O
18 F6 B B D D I I O O
17 F5 B D D D I O O O
16 F4 B D D D O O O O
15 F3 B D D D O O O O
14 F2 B D D D I O O O
13 F1 B B D D I I O O
12 F0 B B B D I I I O
11 I9/OE I OE OE OE I I I I
The Philips Semiconductors’ state-of-the-art Floating-Gate CMOS EPROM process yields bipolar equivalent performance at less than one-quarter the power consumption. The erasable nature of the EPROM process enables Philips Semiconductors to functionally test the devices prior to shipment to the customer. Additionally, this allows Philips Semiconductors to extensively stress test, as well as ensure the threshold voltage of each individual EPROM cell. 100% programming yield is subsequently guaranteed. FUNCTIONAL DIAGRAM CONFIG. CELL CONFIG. CELL I0/ CLK PROGRAMMABLE AND ARRAY
36 ROWS X 72 COLUMNS
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
1997 Aug 08 5
Pins 1 and 11 are configured as Inputs 0 and 9, respectively, via the configuration cell. The clock and OE functions are disabled. All output macro cells (OMC) are configured as bidirectional I/O, with the outputs disabled via the direc- tion term. Denotes a programmable cell location. NOTES: In the unprogrammed or virgin state: All cells are in a conductive state. All AND gate locations are pulled to a logic “0” (Low). Output polarity is inverting. 0 4 8 1 21 62 02 42 83 2 3 5 SP AR CLK OE AC1 AC2 DIR CLK F719 SP AR CLK OE AC1 AC2 DIR F618 SP AR CLK OE AC1 AC2 DIR F517 SP AR CLK OE AC1 AC2 DIR F416 SP AR CLK OE AC1 AC2 DIR F315 SP AR CLK OE AC1 AC2 DIR F214 SP AR CLK OE AC1 AC2 DIR F113 SP AR CLK OE AC1 AC2 DIR F012 SP AR I9/OE I0/CLK I I I I I I F F I I F F I I F F I I F F I I F F I I F F I I F F I I F F 7 CONFIG. CELL SP00012
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
1997 Aug 08 6
OUTPUT MACRO CELL (OMC) OE MUX CLK Q OE D F OUT MUX F MUX VCC OUTPUT POLARITY CONTROL FROM AND ARRAY S X(n) DIRECTION CONTROL TERM TO ALL OMCs TO ALL OMCs AC1 n AC2 n NOTE: Denotes a programmable cell location. FROM AND ARRAYSP AR SP00014 THE OUTPUT MACRO CELL (OMC) The PLC18V8Z series devices have 8 individually programmable Output Macro Cells. The 72 AND inputs (or product terms) from the programmable AND array are connected to the 8 OMCs in groups of 9. Eight of the AND terms are dedicated to logic functions; the ninth is for asynchronous direction control, which enables/disables the respective bidirectional I/O pin. Two product terms are dedicated for the Synchronous Preset and Asynchronous Reset functions. Each OMC can be independently programmed via 16 architecture control bits, AC1 n and AC2n (one pair per macro cell). Similarly, each OMC has a programmable output polarity control bit (Xn). By configuring the pair of architecture control bits according to the configuration cell table, 4 different configurations may be implemented. Note that the configuration cell is automatically programmed based on the OMC configuration. DESIGN SECURITY The PLC18V8Z series devices have a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary designs implemented in the device cannot be copied or retrieved.
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
1997 Aug 08 7
A single configuration cell controls the functions of Pins 1 and 11. Refer to Functional Diagram. When the configuration cell is programmed, Pin 1 is a dedicated clock and Pin 11 is dedicated for output enable. When the configuration cell is unprogrammed, Pins 1 and 11 are both dedicated inputs. Note that the output enable for all registered OMCs is common—from Pin 11 only. Output enable control of the bidirectional I/O OMCs is provided from the AND array via the direction product term. If any one OMC is configured as registered, the configuration cell will be automatically configured (via the design software) to ensure that the clock and output enable functions are enabled on Pins 1 and 11, respectively. If none of the OMCs are registered, the configuration cell will be programmed such that Pins 1 and 11 are dedicated inputs. The programming codes are as follows: Pin 1 = CLK, Pin 11 = OE L Pin 1 and Pin 11 = Input H CONTROL CELL CONFIGURATIONS FUNCTION AC1 1 AC2 N CONFIG. CELL COMMENTS Registered mode Programmed Programmed Programmed Dedicated clock from Pin 1. OE Control for all registerd OMCs from Pin 11 only. Bidirectional I/O mode1 Unprogrammed Unprogrammed Unprogrammed Pins 1 and 11 are dedicated inputs. 3-State control from AND array only. Fixed input mode Unprogrammed Programmed Unprogrammed Pins 1 and 11 are dedicated inputs. Fixed output mode Programmed Unprogrammed Unprogrammed Pins 1 and 11 are dedicated inputs. The feedback path (via F MUX ) is disabled. NOTE: 1. This is the virgin state as shipped from the factory. ARCHITECTURE CONTROL—AC1 and AC2 I CODE D OMC CONFIGURATION REGISTERED (D–TYPE) S CLK F(D), F (D)Q OE S F(B), F (B) DIR CODE B OMC CONFIGURATION CODE O OMC CONFIGURATION FIXED OUTPUT CODECONFIGURATION CELLCODE L CONFIGURATION CELLCODEOMC CONFIGURATION FIXED INPUT BIDIRECTIONAL I/O1 (COMBINATORIAL) PIN 1 = CLK PIN 11 = OE H 6PIN 1 = INPUT PIN 11 = INPUT S F(O), F (O) F (I) F(D), F (D) CLK Q OE CLK Q OE NC NC SP AR SP AR SP AR SP00015 NOTES: A factory shipped unprogrammed device is configured such that: 1. This is the initial unprogrammed state. All cells are in a conductive state. 2. All AND gates are pulled to a logic “0” (Low). 3. Output polarity is inverting. 4. Pins 1 and 11 are configured as inputs 0 and 9. The clock and OE functions are disabled. 5. All Output Macro Cells (OMCs) are configured as bidirectional I/O, with the outputs disabled via the direction term. 6. This configuration cannot be used if any OMCs are configured as registered (Code = D).
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
1997 Aug 08 8
ABSOLUTE MAXIMUM RATINGS 1 SYMBOL PARAMETER RATINGS UNIT VCC Supply voltage –0.5 to +7 VDC VCC Operating supply voltage 4.5 to 5.5 (Industrial) 4.75 to 5.25 (Commercial) VDC VIN Input voltage –0.5 to VCC + 0.5 VDC VOUT Output voltage –0.5 to VCC + 0.5 VDC Δt/ΔV Input/clock transition rise or fall2 250 ns/V maximum IIN Input currents –10 to +10 mA IOUT Output currents +24 mA Tamb Operating temperature range –40 to +85 (Industrial) 0 to +75 (Commercial) °C Tstg Storage temperature range –65 to +150 °C NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. 2. All digital circuits can oscillate or trigger prematurely when input rise and fall times are very long. When the input signal to a device is at or near the switching threshold, noise on the line will be amplified and can cause oscillation which, if the frequency is low enough, can cause subsequent stages to switch and give erroneous results. For this reason, Schmitt-triggers are recommended if rise/fall times are likely to exceed 250ns at VCC = 4.5V. THERMAL RATINGS TEMPERATURE Maximum junction 150°C Maximum ambient 75°C Allowable thermal rise ambient to junction75°C AC TEST CONDITIONS +5V C L R 1 R 2 GND BZ BY INPUTS BW BX OUTPUTS C 2C 1 DUT NOTE: C 1 and C2 are to bypass VCC to GND. VCC SP00006 VOLTAGE WAVEFORMS 90% 10% 5ns5ns 5ns 5ns 90% 10% +3.0V +3.0V tR tF MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses SP00017
1997 Aug 08 9
Figure 1. ICC vs Frequency5, 6 Figure 2. ΔtPD vs Output Capacitance
- All typical values are at VCC = 5V, Tamb = +25°C.
- All voltage values are with respect to network ground terminal.
- Duration of short-circuit should not exceed one second. Test one at a time.
- Tested with TTL input levels: V
IL = 0.45V, VIH = 2.4V. Measured with all outputs switching.
- ΔICC vs frequency (registered configuration) = 2mA/MHz.
- IIL for Pin 1 (I0/CLK) is ± 10µA with VIN = 0.4V.
- VIN includes CLK and OE if applicable.
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
1997 Aug 08 10
AC ELECTRICAL CHARACTERISTICS 4 Commercial = 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC < 5.25V; Industrial = –40°C ≤ Tamb ≤ +85°C, 4.5V ≤ VCC ≤ 5.5V; R2 = 390Ω TEST CONDITION 1 PLC18V8Z25 (Commercial) PLC18V8ZIA (Industrial) SYMBOL PARAMETER FROM TO R 1 (Ω ) C L (pF) MIN MAX MIN MAX UNIT Pulse width tCKP Clock period (Minimum tIS + tCKO ) CLK + CLK + 200 50 33 33 ns tCKH Clock width High CLK + CLK – 200 50 15 15 ns tCKL Clock width Low CLK – CLK + 200 50 15 15 ns tARW Async reset pulse width I ±, F± I +, F + 25 25 ns Hold time tIH Input or feedback data hold time CLK + Input ± 200 50 0 0 ns Setup time tIS Input or feedback data setup time I ±, F± CLK + 200 50 18 18 ns Propagation delay tPD Delay from input to active output I ±, F± F± 200 50 25 25 ns tCKO Clock High to output valid access Time CLK + F± 200 50 15 15 ns tOE1 3 Product term enable to outputs off I ±, F± F± Active-High R = 1.5k Active-Low R = 550 50 25 25 ns tOD1 2 Product term disable to outputs off I ±, F± F± From VOH R = ∞ From VOL R = 200 5 25 25 ns tOD2 2 Pin 11 output disable High to outputs off OE – F± From VOH R = ∞ From VOL R = 200 5 20 20 ns tOE2 3 Pin 11 output enable to active output OE + F± Active-High R = 1.5k Active-Low R = 550 50 20 20 ns tARD Async reset delay I ±, F± F + 30 30 ns tARR Async reset recovery timeI ±, F± CLK + 20 20 ns tSPR Sync preset recovery timeI ±, F± CLK + 20 20 ns tPPR Power-up reset VCC + F + 25 25 ns Frequency of operation fMAX Maximum frequency I/(tIS + tCKO ) 200 50 30 30 MHz NOTES: 1. Refer also to AC Test Conditions. (Test Load Circuit) 2. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 4. Leave all the cells on unused product terms intact (unprogrammed) for all patterns.
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
1997 Aug 08 11
AC ELECTRICAL CHARACTERISTICS 4 Commercial = 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC < 5.25V; Industrial = –40°C ≤ Tamb ≤ +85°C, 4.5V ≤ VCC ≤ 5.5V; R2 = 390Ω TEST CONDITION 1 PLC18V8Z35 (Commercial) PLC18V8ZI (Industrial) SYMBOL PARAMETER FROM TO R 1 (Ω ) C L (pF) MIN MAX MIN MAX UNIT Pulse width tCKP Clock period (Minimum tIS + tCKO ) CLK + CLK + 200 50 47 57 ns tCKH Clock width High CLK + CLK – 200 50 20 25 ns tCKL Clock width Low CLK – CLK + 200 50 20 25 ns tARW Async reset pulse width I ±, F± I +, F + 35 40 ns Hold time tIH Input or feedback data hold time CLK + Input ± 200 50 0 0 ns Setup time tIS Input or feedback data setup time I ±, F± CLK + 200 50 25 30 ns Propagation delay tPD Delay from input to active output I ±, F± F± 200 50 35 40 ns tCKO Clock High to output valid access Time CLK + F± 200 50 22 27 ns tOE1 3 Product term enable to outputs off I ±, F± F± Active-High R = 1.5k Active-Low R = 550 50 35 40 ns tOD1 2 Product term disable to outputs off I ±, F± F± From VOH R = ∞ From VOL R = 200 5 35 40 ns tOD2 2 Pin 11 output disable High to outputs off OE – F± From VOH R = ∞ From VOL R = 200 5 25 40 ns tOE2 3 Pin 11 output enable to active output OE + F± Active-High R = 1.5k Active-Low R = 550 50 25 30 ns tARD Async reset delay I ±, F± F + 35 40 ns tARR Async reset recovery timeI ±, F± CLK + 25 30 ns tSPR Sync preset recovery timeI ±, F± CLK + 25 30 ns tPPR Power-up reset VCC + F + 35 40 ns Frequency of operation fMAX Maximum frequency I/(tIS + tCKO ) 200 50 21 18 MHz NOTES: 1. Refer also to AC Test Conditions. (Test Load Circuit) 2. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 4. Leave all the cells on unused product terms intact (unprogrammed) for all patterns.
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
1997 Aug 08 12
In order to facilitate state machine design and testing, a power-up reset function has been incorporated in the PLC18V8Z. All internal registers will reset to Active-Low (logical “0”) after a specified period of time (tPPR ). Therefore, any OMC that has been configured as a registered output will always produce an Active-High on the associated output pin because of the inverted output buffer. The internal feedback (Q) of a registered OMC will also be set Low. The programmed polarity of OMC will not affect the Active-High output condition during a system power-up condition. TIMING DIAGRAMS ÉÉÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ Switching Waveforms VALID INPUTVALID INPUT 3–STATE 3-STATE INPUTS I/O, REG. FEEDBACK CLK PIN 11 OE REGISTERED OUTPUTS ANY INPUT PROGRAMMED FOR DIRECTION CONTROL COMBINATORIAL OUTPUTS tIS tIH tCKH tCKL tCKP tCKO tOD1 tOD2 tOE2 tPD tOE1 Power-Up Reset NOTE: Diagram presupposes that the outputs (F) are enabled. The reset occurs regardless of the output condition (enabled or disabled). tCKP tCKH tCKLtIS 1.5V 1.5V 1.5V tCKL tIH tIS 1.5V1.5V tCKO 1.5V1.5V tPPR 4.5V 3.0V +5V VOH VOL +3V +3V V CC F (OUTPUTS) I, B (INPUTS) CLK SP00020
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
1997 Aug 08 13
TIMING DIAGRAMS (Continued) tSPR tARW ASYNCHRONOUS RESET INPUT REGISTERED OUTPUT CLOCK tARD tARR SYNCHRONOUS PRESET INPUT CLOCK REGISTERED OUTPUT Asynchronous Reset Synchronous Preset tIS tIH tCKO SP00021
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
1997 Aug 08 14
(DIAGNOSTIC MODE ONLY) In order to facilitate the testing of state machine/controller designs, a diagnostic mode register preload feature has been incorporated into the PLC18V8Z series device. This feature enables the user to load the registers with predetermined states while a super voltage is applied to Pins 11 and 6 (I9/OE and I5). (See diagram for timing and sequence.) To read the data out, Pins 11 and 6 must be returned to normal TTL levels. The outputs, F0 – F7, must be enabled in order to read data out. The Q outputs of the registers will reflect data in as input via F0 – F7 during preload. Subsequently, the register Q output via the feedback path will reflect the data in as input via F0 – F7. Refer to the voltage waveform for timing and voltage references. t PL = 10µsec. REGISTER PRELOAD (DIAGNOSTIC MODE) ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ I9/OE (PIN 11) (PIN 6) I0/CLK (PIN 1) F0–7 I1–4, 6–8 PRELOAD DATA IN PRELOAD DATA OUT DATA OUT OE (VOL ) I0/CLK F0–7 I1–4, 6–8 tPL tPL tPL tPL tPL tPL tOE tCKL tCKO tIS tIH 5.0V5.0V 12.0V 12.0V 12.0V 5.0V SP00022
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
1997 Aug 08 15
The PLC18V8Z series is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors’ SNAP design software package. ABEL and CUPL design software packages also support the PLC18V8Z architecture. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. PLC18V8Z logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only. With Logic programming, the AND/OR/EX-OR gate input connections necessary to implement the desired logic function are coded directly from logic equations using the Program Table. Similarly, various OMC configurations are implemented by programming the Architecture Control bits AC1 and AC2. Note that the configuration cell is automatically programmed based on the OMC configuration. In this table, the logic state of variables I, P and B associated with each Sum Term S is assigned a symbol which results in the proper fusing pattern of corresponding link pairs, defined as follows: OUTPUT POLARITY – (O, B) O , B S X ACTIVE LEVEL CODE LINVERTING 1 O, B S X ACTIVE LEVEL CODE HNON-INVERTING SP00023 “AND” ARRAY – (I, B) CODE STATE DON’T CARE CODESTATE CODE STATE CODE STATE INACTIVE 1 O I, B H I, B L PP P P I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B SP00024 NOTE: 1. A factory shipped unprogrammed device is configured such that all cells are in a conductive state. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc.
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
1997 Aug 08 16
- THE CONFIGURATION CELL IS AUTOMATICALLY PROGRAMMED BASED ON THE OMC ARCHITECTURE. FOR SP, AR: “–” IS NOT ALLOWED. T E R M 76543210765432107654321089 SP AR PIN D A A A A A A A A D A A A A A A A A D A A A A A A A A D A A A A A A A A D A A A A A A A A D A A A A A A A A D A A A A A A A A D A A A A A A A A 1 1987654321 1 2 13141516171819 12 13141516171819 VARIABLE NAME AND OR (FIXED) CONFIGURATION CELL (CLK/OE CONTROL) I F (I) F (B, O, D) ARCH. CONTROL BITS OUTPUT POLARITY CUSTOMER NAME PURCHASE ORDER # PHILIPS DEVICE # CF(XXXX) CUSTOMER SYMBOLIZED PART # TOTAL NUMBER OF PARTS PROGRAM TABLE # REV. DATE NOTES: In the unprogrammed or virgin state: All AND gate locations are pulled to a logic “0” (Low). Output polarity is inverting. Pins 1 and 11 are configured as inputs 0 and 9, respectively, via the configuration cell. The clock and OE functions are disabled. All output macro cells (OMC) are configured as combinatorial I/O, with the outputs disabled via the direction control term. INACTIVE I, F (I, B) I, F (I, B) DON’T CARE O H L AND ARRAY CONTROL OR ARRAY (FIXED)
- •• • REGISTERED (D-TYPE) FIXED INPUT FIXED OUTPUT BIDIRECTIONAL I/O D I O B OMC ARCH. OUTPUT POLARITY NON-INVERTING INVERTING H L CONFIG. CELL* PIN 1 = CLK; PIN 11 = OE PIN 1, PIN 11 = INPUT L H DATA CANNOT BE ENTERED INTO THE OR ARRAY FIELD DUE TO THE FIXED NATURE OF THE DEVICE ARCHITEC- TURE. DIRECTION CONTROL ACTIVE OUTPUT D A NOT USED PROGRAM TABLE SP00029
Philips Semiconductors Product specification PLC18V8ZZero standby power CMOS versatile PAL devices
1997 Aug 08 17
SNAP RESOURCE SUMMARY DESIGNATIONS CONFIG. CELL CONFIG. CELL I0/CLK PROGRAMMABLE AND ARRAY Q OE D F F MUX VCC OUTPUT POLARITY CONTROL FROM AND ARRAY S X(n) DIRECTION CONTROL TERM TO ALL OMCs TO ALL OMCs AC1 n AC2 n NOTE: Denotes a programmable cell location. FROM AND ARRAYSP AR XORINV XORDIR XORREG NOUTV8DFFV8 OR OE11V8 FDMUX SP00025
CMOS versatile PAL devices Philips Semiconductors Product specification PLC18V8Z
1997 Aug 08 18
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
CMOS versatile PAL devices Philips Semiconductors Product specification PLC18V8Z
1997 Aug 08 19
PLCC20: plastic leaded chip carrier; 20 leads SOT380-1
CMOS versatile PAL devices Philips Semiconductors Product specification PLC18V8Z
1997 Aug 08 20
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
CMOS versatile PAL devices Philips Semiconductors Product specification PLC18V8Z
1997 Aug 08 21
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
CMOS versatile PAL devices Philips Semiconductors Product specification PLC18V8Z
1997 Aug 08 22
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
CMOS versatile PAL devices Philips Semiconductors Product specification PLC18V8Z
1997 Aug 08 23
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. /C0109 /C0110 /C0114