PLB2800 INFINEON | Alldatasheet

Document overview

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Technical content

Features

■ 21 Gbit/s 12 million packets/ second switching engine for solid L2+ wirespeed switching performance ■ Embedded 64-bit MIPS 5Kc CPU ■ On-chip DRAM, SRAM ■ Stackable with up to 16 Purple switches with complete stack management ■ Four Class of Service (CoS) queues per port ■ Strict priority and Weighted-Fair- Queuing (WFQ) packet scheduling ■ Advanced buffer control ■ Broadcast and multicast storm control ■ Multicast support for up to 256 multicast groups ■ Port based flow control ■ Per-flow token bucket policing ■ Per-queue rate shaping ■ Port, tag and flow-based VLANs ■ Stacked VLAN support ■ Port-based security ■ Intrusion detection ■ eCPU switch management with Bus mastering capabilities, flow- based accounting and RMON support ■ Hardware assistance for protocols such as STP, GVRP and IGMP and Snooping Interfaces ■ SMII V1.2/V2.1 for FE ports ■ (R)GMII/TBI/MII for GE ports ■ 32-Bit, 66 MHz PCI or generic host bus with DMA support ■ I C Interface for configuration EEPROM, optional low-cost CPU ■ PC-133 SDRAM interface for external CPU DRAM ■ EJTAG Interface for testing ■ General purpose timer and I/Os Standards Supported ■ Supports a wide variety of IEEE 802.xx protocols ■ IETF RFCs 1155–1157 SNMP ■ IETF RFCs 1213, 1643, 1493 ■ IETF RFC 1757 RMON Physical Characteristics ■ P-BGA-388-2 package ■ Core logic operates at 1.8 V

Published by Infineon Technologies AG P RODUCT B RIEF How to reach us: http://www.infineon.com Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81669 München © Infineon Technologies AG 2003. All Rights Reserved. Template: pb_tmplt.fm/2/2003-05-01 Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office. Warnings Due to technical requirements components may contain dan- gerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life- support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or main- tain and sustain and/or protect human life. If they fail, it is rea- sonable to assume that the health of the user or other persons may be endangered.

Ordering Information

Product Sales Code Description Purple PLB 2800 48FE+2GbE/8GbE L2+ Configurable SoC Package P-BGA-388 Product Sales Code Description Purple2800x Purple 2800 8GbEC LAN Switch Demo Board Package Main board with 8GbE copper modules Purple2800x Purple 2800 48+2GEF LAN Switch Demo Board Main board with 48FE+ 2GbE fiber modules Purple2800x Purple 2800 48+2GbEC LAN Switch Demo Board Main board with 48FE+ 2GbE copper modules VDSL2800 SP-VDSL2800 Ethernet Access Switch Demo Board Main board with 24 EoVDSL ports +2GbE uplinks PLB 2800 Block Diagram Small Form Factor 48 + 2G Layer 2 Ethernet over VDSL Switch Application Example Packet Buffer & Resolution Interface Queue & Packet Buffer Interface Tx MAC Interface Tx/Rx Buffer Rx MAC Interface & Parser Gigabit Ethernet MAC x 2 2 x MII/GMII/TBI x 6 Packet Buffer & Resolution Interface Queue & Packet Buffer Interface Tx MAC Interface Tx/Rx Buffer Rx MAC Interface & Parser 1 x Gigabit Ethernet MAC/8 x FE MAC 48 x SMII or 6 x MII/GMII/TBI Queue & Packet Buffer Interface Packet Buffer & Resolution Interface CPU MAC Tx/Rx Buffer Tx MAC Interface Rx MAC Interface & Parser MBOX 1-4 MBOX Control and Status Packet Resolution Packet Manager Queue Manager Queue Memory (SRAM) 32 bit MIPS64 5Kc Core Instruction Cache Data Cache FPI Interface VCPU FPI Bus LED Control/ MDIO/GPIO/IIC Interface Memory Arbitrator eDRAM Bank2 eDRAM Bank1 256 bit 256 bit SDRAM Controller/ Host Interface Address Table and VLAN Memory (SRAM) GbE PHY GbE PHY EoVDSL PHY Up to 48EoVDSL PHY MII/GMII/TBIMII/GMII/TBI or SMII 2 MB Packet Buffer (eDRAM) 8 k MAC Addresses (eSRAM) High Performance 64-bit MIPS CPU PLB 2800 48+2G 16+6G, 8+7G, 8G) Switch-on-a-Chip I2C LEDs Up to 256 MB SDRAM Other PCI Master/Slaves Ordering No. B115-H8208-X-X-7600 Printed in Germany PS 05031. NB