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SuperSpeed USB 3.0 Host -to-Host Bridge Controller Prolific Technology Inc. 7F, No.48, Sec. 3, Nan Kang Rd., Nan Kang, Taipei 115, Taiwan Tel：+886-2-2654-6363; Fax：886-2-22654-6161 Website：http://www.prolific.com.tw/ © 2013-2019 Prolific Inc. All rights reserved. Proprietary and Confidential Product Data Sheet PL27A1 SuperSpeed USB 3.0 Host-to-Host Bridge Controller USB 3.0 and USB 2.0 specification compliant Transfer data between two Hosts via USB port Supports firmware customization for various transfer protocol modes: Product ID (PID) Protocol (by firmware) 27A1 WINUSB/LIBUSB 27A3 CDC ACM 27A5 RNDIS WINUSB and CDC/ACM drivers are built in Windows, Linux and Mac OS, RNDIS driver is built in Windows and Linux For 27A1 mode, application programs can be stored in external SPI Flash and implemented by read-only Mass Storage Device on Windows and Mac OS. Available disk capacity is about 12MB. Supports external SPI Flash to customize USB vendor/product ID QFN64 Package USB Device Interface: 2 x USB Device PHYs Supports 5GHz SuperSpeed, 480MHz Hi-Speed, and 12MHz Full-Speed mode One General Purpose SPI Master controller USB Endpoint 0 for Control Endpoint with dedicated 512 bytes buffer for each USB Highly configurable endpoint structure Pass Through Channel FIFO architecture can utilize full USB bandwidth for data transferring Provides 2 x LED pins 8-bit High Performance 1T 8032 MCU 3.3V Digital I/O Pad 1.2V Power Supply for Core Built-in 5V to 3V linear low-dropout regulator Embedded Power on Reset (POR) 30MHz crystal oscillator for both USB PHYs System Block Diagram 8-bit MCU P-ROM X-RAM Regulator 5V to 3.3V Clock Switch I-RAM GPIO USB Device Controller USB Device Controller USB3 USB2 PHY USB3 USB2 PHY FIFO Pass Through Channel FIFO EP0 FIFO EP0 FIFO SPI Master P-RAM DMA FIFO
SuperSpeed USB 3.0 Host -to-Host Bridge Controller Prolific Technology Inc. 7F, No.48, Sec. 3, Nan Kang Rd., Nan Kang, Taipei 115, Taiwan Tel：+886-2-2654-6363; Fax：886-2-22654-6161 Website：http://www.prolific.com.tw/ © 2013-2019 Prolific Inc. All rights reserved. Proprietary and Confidential Product Data Sheet PL27A1
Ordering Information
Product Package Type Ordering Number PL27A1 64-pin QFN (9x9mm) PL27A1A3FKG7P1
Release: January 8, 2019 - 3 / 17 - Rev. 1.2 Table of Contents
Release: January 8, 2019 - 5 / 17 - Rev. 1.2 1. Overview The PL27A1 is a single-chip SuperSpeed USB 3.0 Host-to-Host bridge controller specially designed for USB host to host data transfer. SuperSpeed USB has data transfer bandwidth of up to 5Gbps offering 10X performance increase over Hi -Speed USB 2.0 (480Mbps). SuperSpeed USB is b ackward compatib le and interoperates with all USB3.0/USB2.0/USB1.1 hosts, devices, and hubs. Figure 1-1 Target Application (USB 3.0 to USB 3.0 Host Cable) The PL27A1 chip offers external firmware customization for various data transfer mode protocols: Part Number External Firmware Function Mode USB VID/PID (by firmware) Transfer Cable (WINUSB/LIBUSB) UART (CDC/ACM) Remote NDIS Package PL27A1 Easy Transfer Cable 067B/27A1 V QFN64 PL27A1 UART (CDC/ACM) 067B/27A3 V QFN64 PL27A1 RNDIS 067B/27A5 V QFN64 27A1 Mode (USB Easy Transfer Cable): This mode enumerates the cable as a USB Easy Transfer Cable device using built-in WINUSB driver. This cable mode is originally designed for Microsoft Windows Easy Transfer (WET) program built inside Windows Vista, Windows 7, and Windows 8 and also available for installation in Windows XP. Using the Windows Easy Transfer program, the PL27A1 USB 3.0 transfer cable allows users to easily connect an old computer running Microsoft Windows XP /Vista/7/8 to another new computer running Windows Vista/7/8 thru the USB ports. Once the program has established connection for both computers, the user can then easily transfer large data files and program settings from the old computer to the new computer. It’s the fastest and easiest way to transfer files and program settings from an old Windows PC to a new Windows PC. Users can still use the cable in Windows 8.1 and 10 by copying the old WET program in Windows 7 or 8. The PL27A1 also comes with the Prolific PCLinq5 file transfer software for Windows and Mac. PCLinq5 is a versatile user-friendly file manager program that allows the end-user to see and control file directories
Release: January 8, 2019 - 6 / 17 - Rev. 1.2 on both PCs and Macs at the same time. End-users can easily drag-and-drop or cut-and-paste files and folders between remote and local PCs as well as creating new folders and changing file attributes. PCLinq5 supports Windows XP, Vista, 7, 8, and 10 versions as well as Mac OS X latest versions. 27A3 Mode (USB Serial Device): This mode enumerates the cable as a USB Serial Device with virtual COM port on both ends of the host systems using built-in CDC/ACM driver. USB Communication Device Class (ACM) driver is built inside Windows 10, Mac OS X, and Linux OS which provides a virtual COM port software interface when the cable device is plugged to the computer. The CDC/ACM driver is also available for installation in Windows 7 or Windows 8 by simple INF driver update. By using Serial COM port terminal programs (like HyperTerminal, Tera Term or Putty), the 27A3 mode cable allows users to easily transfer data between two computers by simply selecting the assigned COM Port number. Once the serial terminal program has established the virtual COM port connection for both computers, the user can then easily transfer large raw data from one computer to another. 27A5 Mode (Network RNDIS): This mode enumerates the device as a Remote NDIS network device on both ends of the USB host. Fully compliant to Remote NDIS Specification, users can easily communicate between two PCs by using network TCP/IP protocol . Transfer files quickly from one USB host to another and even build a small network and share Inte rnet connection with other PC s. No need to install network drivers or add -on cards. Users can share programs, files, and peripherals easily. The PL27A1 chip solution is especially suitable for those who need easy bulk data transfer between two USB hosts - either notebook PC or desktop PC or other USB host systems or devices like SETUP box es, SmartTVs, smartphones and tablets.
Release: January 8, 2019 - 7 / 17 - Rev. 1.2
Features
SuperSpeed USB 3.0 Host-to-Host Bridge Controller USB 3.0 and USB 2.0 specification compliant SuperSpeed (5Gbps), Hi-Speed (480Mbps), and Full-Speed (12Mbps) Transfer data between two USB Hosts (up to SuperSpeed USB 3.0) Supports firmware customization for various transfer protocol modes: 27A1 mode – WINUSB/LIBUSB (Easy Transfer Cable) 27A3 mode – CDC/ACM (USB Serial Device) 27A5 mode – RNDIS (Network Cable) WINUSB and CDC/ACM drivers are all built inside Windows, Linux, and Mac. RNDIS driver is built in Windows and Linux. Easy Transfer Cable fully supports Microsoft Windows Easy Transfer built-in software in Windows Vista, Windows 7, and Windows 8. Prolific provides royalty-free PCLinq5 software for Windows XP/7/8/10 (Easy Transfer Cable). Compliant with Remote NDIS Specification. Users can link two PCs thru the USB port using network TCP/IP protocol. For 27A1 mode, application programs can be stored in external SPI Flash and implemented by read-only Mass Storage Device on Windows and Mac OS. Available disk capacity is about 12MB. 8-bit high-performance 1T 8032 MCU USB device interface Two USB device PHYs USB endpoint 0 for control endpoint with dedicated 512 bytes buffer for each USB side Highly configurable endpoint structure. Each endpoint can be configured as interrupt, bulk, and isochronous endpoint. Pass Through Channel FIFO architecture utilize full USB bandwidth for data transfer Peripherals One SPI Flash Controller for external SPI Serial Flash Memory Supports DMA feature between external SPI flash and internal FIFO Supports multi-vendor SPI Serial Flash Memory 3.3V Digital I/O Pad 1.2V power supply for core Built-in 5V to 3V linear low-dropout regulator Embedded power-on reset (POR) 30MHz crystal oscillator (shared by both USB PHYs) Supports external SPI Flash to customize USB vendor/product ID Supports LED indicator for connection and transfer status Bus powered from either USB port QFN64 Package
Release: January 8, 2019 - 8 / 17 - Rev. 1.2 2. Functional Block Diagram Figure 2-1 Functional Block Diagram 8-bit MCU P-ROM X-RAM Regulator 5V to 3.3V Clock Switch I-RAM SPI Master GPIO USB Device Controller USB Device Controller USB3 USB2 PHY USB3 USB2 PHY FIFO Pass Through Channel FIFO FIFO EP0 FIFO EP0 FIFO P-RAM DMA
Release: January 8, 2019 - 9 / 17 - Rev. 1.2 3. Pin Diagram Figure 3-1 PL27A1 Pin Diagram (QFN64) V33IO1 49 VSS3IO1 50 P1[7] 51 P1[6] 52 P1[5] 53 P1[4] 54 P0_0 55 VDD 56 P3_0 57 RESETB 58 VD3_LDO 59 VD5_LDO 60 VS3_LDO 61 VD3 62 V1P2 63 VSS 64 32 NC 31 NC 30 NC 29 NC 28 NC
27 P3_1
26 USB_VBUS1
25 USB_VBUS0
24 TEST
23 P1[3]
22 P1[2]
21 VDD
20 P1[1]
19 P1[0]
18 VSS
17 V33IO
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 XI1 XO1 AVDD1 SSTXP1 SSTXM1 AVSS1 SSRXP1 SSRXM1 AVDD1 V33AREG1 REXT1 DP1 DM1 VPGIO TP1 NC NC DM DP REXT V33AREG AVDD SSRXM SSRXP AVSS SSTXM SSTXP AVDD XO XI NC PL27A1 QFN64 VSS3IO
Release: January 8, 2019 - 10 / 17 - Rev. 1.2 4. Pin Assignment & Description Pin Type Abbreviation: I: Input O: Output B: Bidirectional A: Analog P: Power/Ground
4.1 USB0 PHY Related Pins
Table 4-1 USB0 PHY Related Pins Symbol Type Pin No Description DM B 4 High speed D- signal DP B 5 High speed D+ signal REXT A 6 Connect external resistor to analog ground V33AREG P 7 Analog power 3.3V for on-chip USB 2.0 PHY AVDD P 8 Analog power 1.2V for on-chip USB PHY SSRXM I 9 SuperSpeed RXM signal SSRXP I 10 SuperSpeed RXP signal AVSS P 11 Analog power 3.3V for on-chip USB PHY SSTXM O 12 SuperSpeed TXM signal SSTXP O 13 SuperSpeed TXP signal AVDD P 14 Analog power 1.2V for on-chip USB PHY XO B 15 Crystal oscillator 30MHz clock output XI I 16 Crystal oscillator 30MHz clock input AVDD3/V33IO P 17 Analog power 3.3V for on-chip USB PHY
4.2 USB1 PHY Related Pins
Table 4-2 USB1 PHY Related Pins Symbol Type Pin No Description DM1 B 36 High speed D- signal DP1 B 37 High speed D+ signal REXT1 A 38 Connect external resistor to analog ground V33AREG1 P 39 Analog power 3.3V for on-chip USB 2.0 PHY AVDD1 A 40 Analog power 1.2V for on-chip USB PHY SSRXM1 I 41 SuperSpeed RXM signal SSRXP1 I 42 SuperSpeed RXP signal AVSS1 P 43 Analog power 3.3V for on-chip USB PHY SSTXM1 O 44 SuperSpeed TXM signal SSTXP1 O 45 SuperSpeed TXP signal AVDD1 P 46 Analog power 1.2V for on-chip USB PHY XO1 B 47 Crystal oscillator 30MHz clock output XI1 I 48 Crystal oscillator 30MHz clock input AVDD31/V33IO1 P 49 Analog power 3.3V for on-chip USB PHY
Release: January 8, 2019 - 11 / 17 - Rev. 1.2
4.3 System Pins
Symbol Type Pin No Description VSS3IO P 18 3.3V I/O ground P1[0] B 19 LED_TRAN: P1[0] – Control pin for LED behavior during data transfer operation of relative USB side. P1[1] B 20 LED_TRAN: P1[1] – Control pin for LED behavior during data transfer operation of relative USB side. VDD P 21 1.2V core power P1[2] B 22 GPIO P1[2] P1[3] B 23 GPIO P1[3] TEST I 24 Chip Test mode enable. Must be NC or tied to Ground. USB_VBUS0 I 25 USB power signal from side 0 USB VBUS USB_VBUS1 I 26 USB power signal from side 1 USB VBUS P3_1 B 27 LED_indicator: Control pin for single LED mode during any side data transfer operation. TP1 I 33 Must be pulled down(4.7KΩ) to GND. VSS3IO P 34 3.3V I/O ground VPGIO P 35 3.3V Power pin VSS3IO1 P 50 3.3V I/O ground P1[7] B 51 Must be floating if not used. P1[6] B 52 Must be floating if not used. P1[5] B 53 Serial Flash Data Output. Must be floating if not used. P1[4] B 54 Serial Flash Data Input. Must be floating if not used. P0[0] B 55 Serial Flash Clock Input. Must be floating if not used. VDD P 56 1.2V Core Power P3_0 B 57 Serial Flash Chip Select. Must be floating if not used. RESETB I 58 External reset pin, active low VD3_LDO P 59 3.3V LDO regulator output voltage VD5_LDO P 60 5V LDO regulator input voltage VS3_LDO P 61 Ground of LDO VD3 P 62 3.3V regulator input voltage (from LDO output) V1P2 P 63 1.2V Power Input VSS P 64 Ground NC B 1,2,3, 28~32 No Connection. Keep floating.
Release: January 8, 2019 - 12 / 17 - Rev. 1.2 5. Functional Description
5.1 USB3 / USB2 PHY
The USB physical layer IP generate s and responds USB electrical signals. These two USB physical layers IP comply with USB 3.0 and USB 2.0 specification. The USB 3.0 part use s PIPE interface to communicate with USB 3.0 controller while the USB 2.0 part uses UTMI interface to communicate with USB 2.0 controller.
5.2 USB Device Controller
The USB device controller generate s and decodes USB transactions including packet header, CRC ch eck, data payload, etc. This controller acts as USB device that can accept host transaction and respon ds data or status. Each USB device controller has dedicated control endpoint FIFO to handle USB SETUP token and its data transfer.
5.3 Pass-Through Channel FIFO
The Pass-Through Channel FIFO can be used to transfer data packet between two USB controllers side. When the data packet is inputted from one USB side, the other side can output it directly. There are two pairs (IN and OUT) pass-through channels in this chip.
5.4 EP0 FIFO
The EP0 FIFO is used to endpoint 0 transfer data packet only for each side and the size is a maximum packet size of every USB speed mode.
5.5 Regulator
The Regulator IP is included to generate IO 3.3V supply voltage.
5.6 Clock Switch
Clock swit ch is designed to handle clock switch between two sides USB at attach/detach and suspend/resume state. 5.7 8-bit MCU This chip uses high performance 1T 8032 8-bit microcontroller. It provides higher performance than general 8032 MCU.
5.8 P-ROM
There is a Program ROM in this chip. After power on reset, the MCU of this chip runs program from this Program ROM (P-ROM).
Release: January 8, 2019 - 13 / 17 - Rev. 1.2 5.9 256B I-RAM 256 bytes IDATA RAM for 8032 MCU. This memory space can provide high speed scratchpad memory for MCU.
5.10 X-RAM
XDATA RAM for 8032 MCU. This is MCU data memory locate d at XDATA space and MCU uses it to store data in process.
5.11 GPIO and PWM
Two PWM signal generators which can be used to control LED flashing behavior. There are also some GPIO signals that can be controlled directly by MCU. These s ignals are multiplexed with peripherals. If some peripherals are turned on, the GPIO signals which is multiplexed will be disabled and these signals change to peripheral signals.
5.12 DMA
The DMA controller is used to transfer data between FIFO XDATA RAM and peripherals. MCU can control this DMA to get data from FIFO or to put data to FIFO from XDATA RAM. It can also be used to transfer data between P-RAM to SPI flash controller or eMMC flash controller.
5.13 SPI Flash Controller
SPI Flash Controller can be used to access data of SPI serial flash memory. The SPI clock rate can be adjusted by MCU.
Release: January 8, 2019 - 14 / 17 - Rev. 1.2 6. Electrical Characteristics
6.1 Absolute Maximum Ratings
Table 6-1 Absolute Maximum Ratings SYMBOL PARAMETER RATING UNITS VCCK 1.2V Core Power Supply -0.3 to 1.4 V VCC 3.3V Power Supply -0.3 to 4.0 V VD5 5V Power Supply -0.3 to 6.0 V VIN3 Input Voltage of 3.3V I/O -0.3 to VCC3I +0.3 V Input Voltage of 3.3V I/O with 5V Tolerance -0.3 to 5.5 TSTG Storage Temperature -40 to 150 oC
6.2 Recommended Operating Conditions
Table 6-2 Recommended Operating Conditions SYMBOL PARAMETER MIN TYP MAX UNITS VD5 5V Power Supply 4.5 5 5.5 V VCCK 1.2V Core Power Supply 1.14 1.2 1.26 V VCC3I Power Supply of 3.3V I/O 3.0 3.3 3.6 V T Operating Temperature 0 25 70 oC 6.3 Recommended Operating Conditions of 3.3V GPIO Table 6-3 Recommended Operating Conditions of 3.3V GPIO SYMBOL PARAMETER MIN TYP MAX UNITS VDD33 I/O Supply Voltage 3.0 3.3 3.6 V VIH Input High Voltage 2.0 5.5 V VIL Input Low Voltage -0.3 0.8 V RPU Pull-up Resistor 62 77 112 k VOL Output Low Voltage 0.4 V VOH Output High Voltage 2.4 V IOL Low Level Output Current @VOL =0.4V 8 mA IOH High Level Output Current @VOL =2.4V 12 mA
Release: January 8, 2019 - 15 / 17 - Rev. 1.2
6.4 Operating Current
Table 6-4 Operating Current Symbol Parameter Connection Current of 3.3V Current of 1.2V Units IDD Operating Current USB 3.0 57 251 mA USB 2.0 41 85 mA ISUS Suspend Current (Sleep, bus-powered) USB 3.0 0.6 0.8 mA USB 2.0 0.9 0.65 mA
Release: January 8, 2019 - 16 / 17 - Rev. 1.2 7. Outline Diagram PACKAGE TYPE JEDEC OUTLINE MO-220 PKG CODE VQFN (Y964) SYMBOLS MIN. NOM. MAX. A 0.80 0.85 0.90 A1 0.00 0.02 0.05 A3 0.203 REF. B 0.18 0.25 0.30 D 9.00 BSC E 9.00 BSC e 0.50 BSC K 0.20 - - NOTES: 1. All dimensions are in millimeters. 2. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 3. Bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. Figure 7-1 Outline Diagram of QFN64
Release: January 8, 2019 - 17 / 17 - Rev. 1.2 Disclaimer All the information in this document is subject to change without prior notice. Prolific Technology Inc. does not make any representations or any warranties (implied or otherwise) regarding the accuracy and completeness of this document and shall in no event be liable for any loss of profit or any other commercial damage, including but not limited to special, incidental, consequential, or other damages. Trademarks The Prolific logo is a registered trademark of Prolific Technology Inc. All brand names and product names used in this document are trademarks or registered trademarks of their respective holders. Copyrights Copyright © 2013-2019 Prolific Technology Inc. All rights reserved. No part of this document may be reproduced or transmitted in any form by any means without the express written permission of Prolific Technology Inc.