PL2773_V01 PROLIFIC | Alldatasheet
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PL2773 SuperSpeed USB 3.0 & eSATA to SATA Bridge Controller Product Datasheet Document Revision: 1.0.1 Document Release: September 1, 2010 Prolific Technology Inc. 7F, No. 48, Sec. 3, Nan Kang Rd. Nan Kang, Taipei 115, Taiwan, R.O.C. Tel: 886-2-2654-6363 Fax: 886-2-2654-6161 Email: sales@prolific.com.tw URL: http://www.prolific.com.tw
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 2 - Document Version 1.0.1
Revision History
1.0.1 Revised Section 1.3 (Target Applications) Revised Section 5.2 (Core Power Supply) Revised Section 5.5 (Suspend Current) September 1, 2010 1.0.0 Formal Release July 26, 2010 0.9A First Preliminary Release May 18, 2010
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 3 - Document Version 1.0.1 Table of Contents
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 5 - Document Version 1.0.1
1.0 Product Overview
1.1 Overview
The PL2773 is a low-power single-chip SuperSpeed USB 3.0 and eSATA Combo to SATA II compliant bridge IC controller. It is designed to perform seamless protocol transfer between the USB or eSATA host PC and SATA interface storage devices like Hard Disk Drives, Optical Disk Drives, and Solid-State Drives. SuperSpeed USB 3.0 has data transfer bandwidth of up to 5Gbps offering 10X performance increase over Hi -Speed USB 2.0 (480Mbps) while still retaining b ackward compatibility and interoperability with all USB2.0 and USB1.1 devices, hosts, and hubs. The PL2773 eSATA mode connection (SATA Gen1/Gen2) provides transfer rate up to 3Gbps bandwidth. The PL2 773 also integrates a high performance 8 -bit microcontroller which can be used to support versatile system applications such as one button backup, power control, and other USB port feature s. The PL2773 chip is also implemented according to the USB Bulk-Only Mass Storage Class Specification v1.0.
1.2 Features
High Performance USB 3.0 or eSATA to SATA Storage Bridge Controller USB 3.0 Specification and USB 2.0 Specification Compliant o USB-IF SuperSpeed Logo Certified (TID No. 340000010) o SuperSpeed(5Gbps), Hi-Speed(480Mbps), and Full-Speed(12Mbps) o USB Mass Storage Class Bulk-Only Transport Serial ATA Revision 3.0 Specification Compliant o Embedded SATA PHY and Controller o SATA Gen2i/Gen2m (3Gbps) and SATA Gen1i/Gen1m (1.5 Gbps) o Supports SATA Hot Plug o Supports SATA Port Multiplier Supports over 2-Terabytes and 4KB-sector Hard Drives Supports USB3.0/USB2.0/SATA Power Saving Management High Performance Embedded 8-bit Microcontroller Internal data buffer for downstream and upstream optimized data transfer performance Firmware update, Vendor/Product ID, and other related configuration information can be programmed to external Serial EEPROM or SPI serial flash through USB interface. Generic SPI interface and I2C interface for ICP 13 General Purpose IO (GPIO) pins can be defined for specific functions by external configuration ROM or through USB interface. Also provides SDK for further applications. Supports two PWM interfaces Supports single 30-MHz reference clock Ultra-low power 1.2V core operating voltage by 0.13um process Inexpensive LQFP64 package
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 6 - Document Version 1.0.1
1.3 Target Applications
USB 3.0/eSATA Combo External HDD/SSD/ODD USB 3.0/eSATA Combo to SATA Port Multiplier Portable Media Player Figure 1-1 PL2773 Target Applications SATA Port Multiplier SATA SATA SATA SATA SATA SATA USB2.0 USB3.0 SATA eSATA USB2.0 USB3.0 SATA eSATA
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 7 - Document Version 1.0.1
1.4 Block Diagram
(8KB) SRAM (46KB) ICP 8032(1T) XData (2KB) IData (256B) eSATA Device Controller SATA Host Controller SATA PHY GPIOSPI I2C PWM SATA PHY Figure 1-2 Block Diagram of PL2773
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 8 - Document Version 1.0.1
2.0 PIN Assignment Diagram
2.1 LQFP64 Pin Assignment Diagram
XSCO_USB XSCI_USB GND33A DP DM VCC33A RREF SSCAP V128 SSTXM GND33A SSTXP VCC12A SSRXM SSRXP GND12A GNDA_S1 XTAL_S1 VCC12A_P1 GNDA_S1 REXT_S1 TXDP_S1 TXDN_S1 VCC12A_C1 RXDN_S1 GNDA_S1 RXDP_S1 GNDA_S1 GND NC NC P3_3 1GNDA_S2 2RXDP_S2 3GNDA_S2 4RXDN_S2 5VCC12A_C2 6TXDN_S2 7TXDP_S2 8REXT_S2 9GNDA_S2 10VCC12A_P2 12GND 13USB_VBUS 15VCC3IO 16VCCK 14RESETB 11XTAL_S2 P3_447 P3_5 GND45 P3_2 P3_043 P3_1 P1_141 P1_0 P1_339 P1_2 P1_4
36 P1_6
34 VCC3IO
33 VCCK
35 P1_7
P1_5 Figure 2-1 Pin Assignment Diagram of PL2773 LQFP64
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 9 - Document Version 1.0.1
3.0 PIN Assignment Description
3.1 USB PHY Related Pins
Pin Type Abbreviation: I: Input O: Output B: Bidirectional A: Analog P: Power/Ground Table 3-1 USB PHY Related Pins Symbol Type Pin No. LQFP64
Description
RREF A 23 External resistor (12K) for bias current generation DP B 20 High speed D+ signal DM B 21 High speed D- signal XSCI_USB I 18 USB Crystal oscillator input. (30MHz) XSCO_USB O 17 USB Crystal oscillator output. (30MHz) VCC33A P 22 Analog 3.3V supply voltage GND33A P 19,27 Analog ground VCC12A P 29 Analog 1.2V supply voltage. GND12A P 32 Analog ground SSCAP O 24 Connect an external capacitor (X7R 2.2nF ±10%) to GND33A V128 P 25 Analog 1.2V supply voltage. SSTXP A 28 Differential SuperSpeed transmitting data (positive terminal) SSTXM A 26 Differential SuperSpeed transmitting data (negative terminal) SSRXP A 31 Differential SuperSpeed receiving data (positive terminal) SSRXM A 30 Differential SuperSpeed receiving data (negative terminal)
3.2 SATA PHY Related Pins
Table 3-2 SATA PHY Related Pins Symbol Type Pin No. LQFP64 GNDA_S1 P 53,55,61,64 Analog ground RXDP_S1 A 54 Receive Data (Receiver positive input) RXDN_S1 A 56 Receive Data (Receiver negative input) VCC12A_C1 P 57 Analog 1.2V supply voltage VCC12A_P1 P 62 Analog 1.2V supply voltage TXDN_S1 A 58 Transmit Data (Transmitter negative output) TXDP_S1 A 59 Transmit Data (Transmitter positive output)
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 10 - Document Version 1.0.1 REXT_S1 A 60 External resistor (1K) resistor for bias current generation. XTAL_S1 I 63 SATA Crystal oscillator input (30MHz) NOTE: SATA PHY shares the same USB PHY crystal oscillator. GNDA_S2 P 1,3,9 Analog ground RXDP_S2 A 2 Receive Data (Receiver positive input) RXDN_S2 A 4 Receive Data (Receiver negative input) VCC12A_C2 P 5 Analog 1.2V supply voltage VCC12A_P2 P 10 Analog 1.2V supply voltage TXDN_S2 A 6 Transmit Data (Transmitter negative output) TXDP_S2 A 7 Transmit Data (Transmitter positive output) REXT_S2 A 8 External resistor (1K) resistor for bias current generation. XTAL_S2 I 11 SATA Crystal oscillator input (30MHz) NOTE: SATA PHY shares the same USB PHY crystal oscillator.
3.3 System & GPIO Pins
Table 3-3 System & GPIO Pins Symbol Type Pin No. LQFP64 VCC3IO P 15,34 PAD power RESETB I 14 External Reset pin (Active low: Schmitt-trigger) USB_VBUS I 13 USB Power signal from USB VBUS. Default: internal pull-low (Schmitt-trigger) P1[7:0] B 35~42 General Purpose I/O pins: P3_1: Access LED P1_4: Device Power Control P1_5: USB Speed LED Indicator (HS/SS) P1_6: Write Protect Function P1_7: One Button Backup Control Default: internal pull-high (Schmitt-trigger), typical current 8mA in output mode. P3[5:0] B 43,44,46~49 General Purpose I/O pins Default: internal pull-high (Schmitt-trigger), typical current 8mA in output mode. VCCK P 16,33 1.2V core Power pins GND P 12,45,52 Digital ground pins
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 11 - Document Version 1.0.1
4.0 External Configuration ROM
4.1 External Configuration ROM
The PL2773 uses external serial memory (EEPROM or Flash) to store the Vendor ID, Product ID, Device Release Number (in device descriptor ), Attributes and Max Power setting (in configuration descriptor), String Descriptor and some chip operation mode configuration. The external f irmware of PL2773 is also stored in this memory and the maximum size is 46KB by SPI interface or 28KB by I2C interface. After reset, the firmware in the external memory will be loaded into internal program SRAM. Two types of serial interface are supported, the one is SPI (Serial Peripheral Interface) and the other is I2C compatible interface. Both interface s support master mode only. The PL2773 allows the following possible configurations: I2C Serial EEPROM: This option uses I2C serial EEPROM to store chip configuration data and firmware. Firmware is stored in the EEPROM and will be loaded during system startup. SPI Serial Flash: This is the recommended option. It behaves the same as the I2C serial memory with this chip but the transfer speed of SPI interface is faster than I2C interface. The SPI interface is a four -pin interface but this chip uses only three pins to communicate with. So the DI and DO are shorted; or better short by a serial 240-ohm resistor.
4.2 Data Structure of External Serial Memory Content
The Configuration ROM is organized as follows: Table 4-1 EEPROM Address and Content Address Content Note 1:0 Check Word – 0x067B (predefined constant) 3:2 Vendor ID (idVendor field of Device Descriptor) 5:4 Product ID (idProduct field of Device Descriptor) 7:6 Device Release Number (bdcDevice field of Device Descriptor)
8 Attributes (bmAttributes field of Configuration Descriptor)
9 Max Power (MaxPower field of Configuration Descriptor)
10 Chip operation settings
15:14 Reserved 249:16 USB String Descriptor Table 253:250 GPIO Settings 255:254 Miscellaneous
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 12 - Document Version 1.0.1 From byte 16 to byte 230 are used for USB string descriptors. The String Descriptor table is a li nked data structure that holds all string descriptors recognized by this chip in the order of its index. The first entry, String 0, represents the Language ID, as defined by the USB specification. The second entry, String 1, is the Manufacturer Descriptor, as defined by the Device Descriptor. The third and forth entries, String 2 and 3, are the Product Descriptor and Serial Number, respectively, also defined by the Device Descriptor. The user has the option to define String 4, 5, and 6 for their own private use. Each of these String Descriptor Entries is of the following data structure: Table 4-2 String Descriptor Data Structure Offset Field Size Value Note 0 bLength 1 Length of the string plus 2, i.e. (N + 2). 1 bDescriptorType 1 03h – STRING Descriptor type. 2 bString N UNICODE encoded string. The last entry of this table must have a bLength of 0 to indicate the end of this table. A zero-length data will be returned if the host tries to access to the string descriptor beyond the last one. The following table shows one example of valid EEPROM contents: Table 4-3 Example of Valid EEPROM Contents Offset Content Note 0:1 Check Word – 0x067B Constant 2:3 Vendor ID – 0x067B 4:5 Product ID – 0x2773 6:7 Device Release Number – 0x0100 15:10 16 0x04 String Index 0 (4 Bytes) 17 0x03 19:18 0x0409 Language ID for English (United States). 20 0x32 String Index 1 (50 Bytes) 21 0x03 “XXX Technology Inc.” – manufacturer description. 0x00 is padded for UNICODE. 70 0x34 String Index 2 (52 Bytes) 71 0x03
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 13 - Document Version 1.0.1 “Mass Storage Device” – device description. 0x00 is padded for UNICODE. 122 0x0A String Index 3 (10 bytes) 123 0x03 132 0x00 End of String Descriptor Table. The user could also define other strings, 4 to 6, to hold useful information for the drivers and/or applications, such as software authorization codes, symbolic names, just to name a few. However, the total length of this table must not exceed 256 bytes (include reserved space for chip controlling), the supported maximum size of external configuration ROM.
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 14 - Document Version 1.0.1
5.0 Electrical Characteristics
5.1 Absolute Maximum Ratings
Table 5-1 Absolute Maximum Ratings SYMBOL DESCRIPTION RATING UNIT VCCK Core Power Supply -0.5 ~ 1.6 V VCC3IO Power Supply of 3.3 V I/O Cells -0.5 ~ 3.6 V VIN3 Input Voltage of 3.3V I/O Cells -0.5 ~ 3.6 V TSTG Storage Temperature -65 ~ 150 oC IIN DC Input Current 50 mA IOUT Output Short Circuit Current 50 mA Notes: 1. Permanent damage on devices may occur if the absolute maximum ratings are exceeded. These are only stress ratings, and functional operation should be restricted within the conditions detailed in this table. Exposure to the absolute maximum rating conditions for extended periods of time may affect the reliability of the devices. 2. The input and output negative voltage rating may be exceeded if the input and output currents under ratings are observed.
5.2 Recommended Operating Conditions
Table 5-2 Recommended Operating Conditions SYMBOL PARAMETER MIN TYP MAX UNIT VCCK Core Power Supply 1.14 1.2 1.26 V VCC3IO Power Supply of 3.3V 2.97 3.3 3.63 V Tj Junction Operating Temperature -40 25 125 oC 5.3 DC Characteristics of 3.3V Programmable I/O Cells Table 5-3 DC Characteristics of 3.3V Programmable I/O Cells SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT VIL Input Low Voltage
3.3 V LVTTL
- - 0.8 V VIH Input High Voltage 2.0 - - V Vt- Schmitt-trigger negative to threshold voltage 3.3V LVTTL 0.8 1.1 - V Vt+ Schmitt-trigger positive to threshold voltage - 1.6 2.0 V Vol Output low voltage |Iol| = 2mA~16mA - - 0.4 V Voh Output high voltage |Ioh| = 2mA~16mA 2.4 - - V Rpu Input pull-up resistance PU = High PD = Low 40 75 190 k Rpd Input pull-down resistance PU = Low PD = High 40 75 190 k
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 15 - Document Version 1.0.1
5.4 Power On Sequence and Reset Timing
Figure 5-1 Power On Sequence and Reset Timing Diagram Table 5-4 Recommended Timing SYMBOL MIN TYP MAX UNIT T1 - - 1 ms T2 - - 1 ms T3 0 >=0 - ms T4 2 - - ms Trstb 2 4 - ms Note: For Vt+ and Vt-, refer to Table 5-3.
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 16 - Document Version 1.0.1
5.5 Operating Current Parameters
Table 5-5 Operating Current Parameters SYMBOL PARAMETER Connection VCC33 VCC12 UNIT IDD Operating Current USB 3.0 43 242 mA USB 2.0 22 123 mA eSATA 2 212 mA ISUS Suspend Current (S1 Sleep, Self-Powered) USB 3.0 2 119 mA USB 2.0 6 117 mA eSATA 2 208 mA Suspend Current (S4 Hibernate, Self-Powered) USB 3.0 2 103 mA USB 2.0 6 101 mA eSATA 2 182 mA Test Environment Machine: Gigabyte GA-P55A-UD4P Motherboard with on-board Renesas (NEC) USB 3.0 chip.
5.6 Crystal/Oscillator Frequency
The recommended crystal or oscillator frequency is 30MHz 50ppm.
6.0 Ordering Information
Table 6-1 Ordering Information Part Number Package Type PL2773 LQFP64 64-pin LQFP (10x10mm)
Revised Date: September 1, 2010 ds_PL2773_v1.0.1 PL2773 (Chip Rev A) Product Datasheet - 17 - Document Version 1.0.1
7.0 Outline Diagram
7.1 LQFP64 Package (10x10mm) Outline Diagram
Figure 7-1 Outline Diagram of PL2773 LQFP64 (10x10mm)