PIP202-12M-2 NXP | Alldatasheet
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DC-to-DC converter powertrain Rev. 02 — 24 November 2003 Product data M3D797 1. Description The PIP202-12M is designed for use as the power output stage of a synchronous buck DC-to-DC converter. It contains a MOSFET control IC, two power MOSFET transistors and a Schottky diode. By combining the power MOSFETs and the driver circuit into a single component, stray inductances are virtually eliminated, resulting in higher switching frequency, lower switching losses and a compact, efficient design. 2. Features ■ Input voltage conversion range from 3.3 V to 12 V ■ Output voltages from 0.8 V to 5 V ■ Capable of up to 25 A continuous output current ■ Operating frequency up to 1 MHz ■ Peak system efficiency >92% at 500 kHz ■ Low-profile, surface mount package (10× 10 × 0.85 mm) ■ Compatible with any single or multi-phase PWM controller. 3. Applications ■ High-current DC-to-DC point-of-load converters ■ Small form-factor Voltage Regulator Modules ■ Microprocessor and memory voltage regulators. 4. Ordering information Table 1: Ordering information Type number Package Name Description Version PIP202-12M-2 HVQFN68 (MLF68) plastic, thermal enhanced very thin quad flat package; no leads; 68 terminals; body 10× 10 × 0.85 mm SOT687-1
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 2 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 5. Block diagram 6. Pinning information
6.1 Pinning
A bootstrap diode is integrated into the design of the PIP202-12M between VDDC and CB. Fig 1. Block diagram. VDDO VSSO VSSC VO VDDC VI sourceH driveH driveLcontrol cct gnd bootstrap capacitor 03ag51 CB PIP202-12M sourceL PWM input 11, 12 1 to 8, 60, 61 68, PAD1 10, 26, 27, 45 to 59 62 to 67, PAD3 28 to 44 9, 15 22 to 24, PAD2 16, 17 13, 14 control cct supply n.c. 18 to 21, 25 Shaded area denotes terminal 1 index area. Fig 2. Pin configuration (footprint view). VO PAD 3 PIP202-12M VDDO PAD 1 VSSC PAD 2 03ag52 VDDO VDDO VDDO VDDO VDDO VDDO VDDO VSSC VDDO VSSC VO CB CB VDDC VDDC VI VI n.c. n.c. n.c. n.c. VSSC VSSC VSSC n.c. VO VO VSSO VSSO VSSO VSSO VSSO VSSO VSSO VDDO VO VO VO VO VO VO VDDO VDDO VO VO VO VO VO VO VO VO VO VO VO VO VO VO VO VSSO VSSO V SSO VSSO VSSO VSSO VSSO VSSO VSSO VSSO
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 3 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.2 Pin description
[1] All pins connected to PAD1 [2] All pins connected to PAD2 [3] All pins connected to PAD3 [4] PAD1, PAD2 and PAD3 are electrical connections and must be soldered to the printed circuit board [5] All n.c. pins should be connected to V SSC . 7. Functional description
7.1 Basic functionality
In order to understand the functions performed by the PIP202-12M, consider the requirements of a synchronous DC-to-DC converter output stage, driven from a PWM controller (Figure 3). When the input voltage is HIGH, the upper MOSFET must be on and the lower MOSFET must be off. Current flows from the supply (V DDO ), through the upper MOSFET and the inductor (Lout), to the output. Table 2: Pin description Symbol Pin I/O Description VDDO 1 to 8, 60, 61, 68 [1] [4] - output stage supply voltage VSSC 9, 15, 22 to 24[2] [4] - control circuit supply ground VO 10, 26, 27, 45 to 59, 62 to 67 [3] [4] O output CB 11, 12 I/O bootstrap capacitor connection VDDC 13, 14 - control circuit supply voltage VI 16, 17 I pulse width modulated input V SSO 28 to 44 - output stage supply ground n.c. 18 to 21, 25 [5] - no internal connection Fig 3. Simplified functional block diagram of a synchronous DC-to-DC converter output stage. VI VDDC VSSC VO VDDO input voltage from PWM controller control circuit supply (12 V) output stage supply voltage tp tpT Td = VI VSSO CB 03ad36 output 100 nF Lout C out signal ground power ground
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 4 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. When the input voltage is LOW and current is flowing in the inductor, the upper MOSFET must be off and the lower MOSFET must be on. Current flows from the power ground (V SSO ), through the lower MOSFET and the inductor (Lout), to the output. Finally, when switching between states, both MOSFETs must not be on at the same time.
7.2 MOSFET driver function
The input, output and gate drive waveforms are shown inFigure 4. When the input voltage goes HIGH, the gate drive to the lower MOSFET immediately goes LOW. This causes the output current to flow through the Schottky diode, connected between the drain and source of the lower MOSFET. This causes output voltage to fall from zero to approximately−0.5 V. After a delay, if the input voltage is still HIGH, the gate drive to the upper MOSFET goes HIGH. This causes the output voltage to rise to the output stage supply voltage, V DDO. When the input voltage goes LOW, the gate drive to the upper MOSFET immediately goes LOW. The output voltage falls from V DDO , until it is clamped by the Schottky diode at approximately−0.5 V. After a delay, if the input voltage is still LOW, the gate drive to the lower MOSFET goes HIGH. The lower MOSFET turns on, and the output voltage rises from−0.5 V to zero.
7.3 Bootstrap diode
A bootstrap diode is integrated into the design of the PIP202-12M between VDDC and CB. Fig 4. Input, output and gate drive waveforms of a synchronous DC-to-DC converter output stage. input voltage output voltage upper MOSFET gate drive lower MOSFET gate drive 03ag35 delay delay
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 5 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 7.4 3-state function If the input from the PWM controller becomes high impedance (3-state) for longer than td(3-state), then both MOSFETs are turned off and the VI input is driven to 2.5 V by an internal 2 x 10 kΩ resistor voltage divider between an internal 5 V reference and ground. Once the VI input is outside the 3-state window for longer than td(3-state) normal operation will commence. 8. Limiting values [1] Pulse width and repetition rate limited by maximum value of Tj. [2] Assumes a thermal resistance from junction to printed-circuit board of 5 K/W. Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDDC control circuit supply voltage −0.5 15 V VDDO output stage supply voltage −0.5 25 V VI input voltage −0.5 5.25 V VO output voltage −0.5 V DDO + 0.5 V VCB bootstrap voltage −0.5 V O +1 5 V IO(AV) average output current V DDC =1 2V ; Tpcb ≤ 110 °C; Figure 5 -2 5 A IORM repetitive peak output current VDDC =1 2V ; tp ≤ 10 µs [1] - 200 A Ptot total power dissipation T pcb =2 5°C [2] -2 5 W Tpcb =9 0°C [2] -1 2 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C VDDC =1 2V ; VDDO = 12 V; fi= 500 kHz; VO = 1.6 V. Fig 5. Average output current as a function of printed-circuit board temperature. 03ag41 0 50 100 150 Tpcb (°C) IO(AV) (A)
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 6 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9. Thermal characteristics 10. Characteristics [1] If the input voltage remains between VIH and VIL (2.5 V typ) for longer than td(3-state), then both MOSFETs are turned off. Table 4: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit R th(j-pcb) thermal resistance from junction to printed-circuit board - 4 5 K/W R th(j-a) thermal resistance from junction to ambient device mounted on FR4 printed-circuit board; copper area around device 25× 25 mm no thermal vias - 25 - K/W with thermal vias - 20 - K/W with thermal vias and forced air cooling; airflow = 0.8 ms (150 LFM) - 15 - K/W R th(j-c) thermal resistance from junction to case measured on upper surface of package. - 11 - K/W Table 5: Characteristics VDDC =1 2V; Tj=2 5°C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V DDC control circuit supply voltage 25°C ≤ Tj ≤ 150 °C 7 12 14 V VIH HIGH-level input voltage 25 °C ≤ Tj ≤ 150 °C [1] 3.0 3.45 3.9 V VIL LOW-level input voltage 25 °C ≤ Tj≤ 150 °C [1] 1 1.45 1.9 V ILI input leakage current 0 V ≤ VI≤ 5 V - 0.3 1.2 mA IDDC control circuit supply current fi= 0 Hz - 1.5 3 mA fi= 500 kHz;Figure 10 -4 5 6 0 m A Ptot total power dissipation V DDO =1 2V ; IO(AV) =2 0A ; fi= 500 kHz; VO = 1.6 V; Tpcb ≤ 120 °C; Figure 6 - 4.5 - W Dynamic characteristics td(on)(IH-OH)turn-on delay time input HIGH to output HIGH VDDO =1 2V ; IO(AV) =2 5A - 7 7 8 5 n s td(off)(IL-OL)turn-off delay time input LOW to output LOW -3 0 4 5 n s to(r) output rise time - 18 25 ns to(f) output fall time - 12 20 ns td(3-state) 3-state delay time - 140 - ns
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 7 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. VDDC =1 2V ; VDDO = 12 V; VO = 1.6 V; fi= 500 kHz V DDC =1 2V ; VO = 1.6 V; fi= 500 kHz; IO(AV) = 12.5 A Fig 6. Total power dissipation as a function of average output current; typical values. Fig 7. Normalized power dissipation as a function of output stage supply voltage; typical values. 03ag53 0 5 10 15 20 25 IO (A) Ptot (W) 03ag54 0.8 1.2 1.4 1.6 51 0 1 5 2 0 VDDO (V) a a P tot P tot VDDO 12V=() VDDC =1 2V ; VDDO = 12 V; fi= 500 kHz; IO(AV) = 12.5 A V DDC =1 2V ; VDDO = 12 V; VO = 1.6 V; IO(AV) = 12.5 A Fig 8. Normalized power dissipation as a function of output voltage; typical values. Fig 9. Normalized power dissipation as a function of input frequency; typical values. 03ag55 0.9 1.1 1.2 1.3
12345 VO (V)
b 03ag74 0.6 0.8 1.2 1.4 1.6 200 400 600 800 1000 fi (kHz) c b P tot P tot VO 1.6V=() P tot P tot fi 500kHz=()
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 8 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. VDDC =1 2V ; VDDO = 12 V; VO = 1.6 V; IO(AV) = 12.5 A. Fig 10. Control circuit supply current as a function of input frequency; typical values. 03ae75 100 250 500 750 1000 IDDC (mA) fi (kHz)
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 9 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 11. Application information
11.1 Typical application
A typical four-phase buck converter is shown inFigure 11. This system uses four PIP202-12M devices to deliver a continuous output current of 80 A at an operating frequency of 500 kHz. Remark: An external bootstrap diode is not required as one is already integrated into the design of the PIP202-12M between V DDC and CB. Fig 11. Typical application circuit using the PIP202-12M in a four-phase converter. PWM 1 PWM 2 PWM 3 PWM 4 PWM Controller 03ag56 conversion supply (12 V) control circuit supply (12 V) output voltage PIP202-12M 360 nH VDDC VDDOCB VO VSSO VI PIP202-12M 360 nH 100 nF 1 µF VDDC VDDOCB VO VSSOVSSC VSSC VSSC VSSC VI PIP202-12M 360 nH VDDC VDDOCB VO VSSO VI PIP202-12M 360 nH VDDC VDDOCB VO VSSO VI 10 Ω 2.2 nF 2.2 Ω 22 µF (4x) 10 Ω 10 Ω 10 Ω 2.2 Ω 2.2 Ω 2.2 Ω 2.2 nF 2.2 nF 2.2 nF 100 nF 100 nF 100 nF 1 µF 1 µF 1 µF 100 µF (2x) signal ground power ground 100 µF (2x) 100 µF (2x) 100 µF (2x) 22 µF (4x) 22 µF (4x) 22 µF (4x)
9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Table 4. With thermal vias and forced air cooling, the thermal resistance of each The thermal resistance between the junction and the printed-circuit board is 5 K/W.
11.2 Advantages of an integrated driver
discrete components, is stray inductance between the various circuit elements. MOSFETs and causes high-frequency oscillation of the gate voltage. and magnetic fields radiate from PCB tracks and couple into adjacent circuits. stray inductance is virtually eliminated, resulting in a compact, efficient design. cross-conduction whilst allowing the circuit to operate at a higher frequency.
11.3 External connection of power and signal lines
the PCB tracks and the decoupling capacitors. chip ceramic capacitors are recommended.
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 11 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. To protect the control circuit from the transient voltages, the following precautions must be taken. Refer toFigure 12. 1. The output stage ground (VSSO ) must be connected to the decoupling capacitor (Cin) before joining the ground plane. Otherwise, the switching noise on VSSO will couple into the control circuit ground (VSSC ). 2. The control circuit supply must be filtered using a resistor-capacitor (RC) filter. The values shown inFigure 12 are suitable for most applications. 3. It is essential that the VSSC (signal ground) connection at the device is not connected in the current return path between the VSSO (power ground) connection at the device and the VDDO input capacitor. 4. It is also essential that the input to the VDDC (logic power) filter is not connected in the current path between the VDDO (conversion power) connection at the device.
11.4 Switching frequency
A high operating frequency reduces the size and number of capacitors needed to filter the output current, and also reduces the size of the output inductors. The disadvantage, however is higher dissipation due to switching and MOSFET driver losses. For example, doubling the operating frequency of the circuit inFigure 11from 500 kHz to 1 MHz would increase the power dissipation in each PIP202-12M from 4 W to 6 W, at an output current of 20 A in each PIP202-12M. The maximum switching frequency is limited by thermal considerations, the dissipation in the PIP202-12M device(s) and the thermal resistance from junction to ambient.
11.5 Thermal design
The PIP202-12M has three pads on its underside. These are designated PAD1, PAD2 and PAD3 (Figure 2). PAD1 is connected to V DDO , PAD2 is connected to VSSC and PAD3 is connected to VO. In addition to providing low inductance electrical connections, these pads conduct heat away efficiently from the MOSFETs and control IC to the printed-circuit board. The thermal resistance from junction to printed-circuit board is approximately 5 K/W. In order to take full advantage of the low Fig 12. External connection of power and signal lines. VI VDDC VSSC VO VDDO control circuit supply (12 V) output stage supply voltage VSSO CB 03ae27 output 100 nF Lout C out 10 W 1 mF C in signal ground power ground input voltage from PWM controller
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 12 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. thermal resistance of this package, the printed-circuit board must be designed so that heat is conducted away efficiently from the package. This can be achieved by maximizing the area of copper around each pad, and by incorporating thermal vias to conduct the heat to inner and/or bottom layers of the printed-circuit board. An example of a thermal via pattern is shown inFigure 13. In a typical application, with no forced air cooling, the use of thermal vias typically reduces the thermal resistance from 25 K/W to 20 K/W. The additional use of a small fan can reduce this further to approximately 15 K/W. The thermal resistance of a particular design can be measured by passing a known current between V SSO and VDDO . The current flows through the Schottky diode and through the source-drain diode of the upper MOSFET. The direction of current flow is into V SSO and out of VDDO . The volt drop between VSSO and VDDO is then measured and used to calculate the power dissipation in the PIP202-12M. The case temperature of the PIP202-12M can be measured using an infra-red thermometer. The thermal resistance can then be calculated using the following equation: (3) where T case is the measured case temperature (°C), Tamb is the ambient temperature (°C), I is the MOSFET current (A), and VF is the voltage drop between VSSO and VDDO (V). Where more than one phase is used, for example the circuit ofFigure 11, the thermal resistance of each PIP202-12M should be measured with current flowing in all phases. All holes 0.5 mm diameter with 1 mm spacing. Fig 13. Printed-circuit board thermal via pattern. 03ag36 PAD1 PAD2 PAD3 R th j pcb–() T case T amb–
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 13 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 12. Test information Figure 14shows the test circuit used to measure power loss in the PIP202-12M. The output voltage is measured using an averaging circuit. This eliminates losses in the output inductor and the PCB tracks. The calculated power loss, using this method, includes the losses in the Equivalent Series Resistance (ESR) of the input filter capacitors. This must be subtracted from the total loss to give the net loss in the PIP202-12M. 13. Marking Fig 14. Power loss (Ptot) test circuit. VI VDDC VSSC VO VDDO input voltage from pulse generator control circuit supply (12 V) output stage supply VI VSSO CB 03ai73 IO 100 nF V averaging circuit A load A A V VO(AV) IDDO IDDC 500 nH VDDO signal ground power ground P DDO V DDO IDDO×= P DDC V DDC IDDC×= P O V OA V() IO×= P tot P DDO P DDC P O–+= TYPE No: PIP202-12M-N (N is version number) DIFFUSION LOT No: 7 characters MANUFACTURING CODE: see Figure 16 COUNTRY OF ORIGIN: Korea Fig 15. SOT687-1 marking. Fig 16. Interpretation of manufacturing code. terminal 1 index area 03ag38 TYPE No. DIFFUSION LOT No. MANUFACTURING CODE COUNTRY OF ORIGIN Release status code X = Development Sample Y = Customer Qualification Sample blank = Released for Supply Date code YY = last two digits of year WW = week number Design centre k = Hazel Grove, UK Diffusion centre h = Hazel Grove, UK Assembly centre f = Anam Korea 03ai72 hfkYYWWY
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 14 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 14. Package outline Fig 17. SOT687-1. A 4 bUNIT D e REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 10.15 9.85 10.15 9.85 3.8 3.5 3.8 3.5 0.5 v 0.1 w 0.05 y 0.05 0.18 0.30 0.18 c 0.2 9.95 9.55 9.95 9.55 7.85 7.55 0.75 0.50 0.80 0.65 A 1 0.05 0.001 DIMENSIONS (mm are the original dimensions) EE h1EhE1D hD 1 L 0 2.5 5 mm scale SOT687-1 HVQFN68: plastic thermal enhanced very thin quad flat package; no leads; 68 terminals; body 10 x 10 x 0.85 mm A max. A detail X L Eh1 Eh1 D h Eh D h e 18 34 68 52 3517 D D 1 EE1 X 02-10-18 03-06-13 terminal 1 index area terminal 1 index area B A c yy1 C C e b AC C Bv M w M
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 15 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 15. Soldering
15.1 Introduction to soldering MLF packages
The MicroLeadFrame package (MLF) is a near Chip Scale Package (CSP) with a copper leadframe. It is a leadless package, where electrical contact to the printed circuit board is made through metal pads on the underside of the package. In addition to the small pads around the periphery of the package, there are large pads on the underside that provide low thermal resistance, low electrical resistance, low inductance connections between the power components inside the MLF package and the PCB. It is this feature of the MLF package that makes it ideally suited for VRM applications. Electrical connection between the package and the printed circuit board is made by printing solder paste on the printed circuit board, placing the component and reflowing the solder in a convection or infra-red oven. The solder reflow process is shown inFigure 18 and the typical temperature profile is shown inFigure 19. To ensure good solder joints, the peak temperature T p should not exceed 220°C for thin packages such as MLF , and the time above liquidus temperature should be less than 1.25 minutes. The maximum temperature can be increased for lead free solder. The ramp rate during preheat should not exceed 3 K/s. Nitrogen purge is recommended during reflow. Fig 18. Typical reflow soldering process flow. Fig 19. Typical reflow soldering temperature profile. SOLDER PASTE PRINTING POST PRINT INSPECTION COMPONENT PLACEMENT PRE REFLOW INSPECTION REFLOW SOLDERING POST REFLOW INSPECTION (PREFERABL Y X-RAY) REWORK AND TOUCH UP 03aj25 03aj26 100 200 300 0123 time (minutes) Temp Tr Te Tp rate of rise of temperature < 3 K/s 1 min max 1.25 min max (°C)
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 16 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved.
15.2 Rework guidelines
Since the solder joints are largely inaccessible, only the side fillets can be touched up. If there are defects underneath the package, then the whole package has to be removed. The first step in component removal is to reflow the solder joints. It is recommended that the board is heated from the underside using a convective heater whilst hot air or gas is directed at the upper surface of the component. Nozzles should be used to direct the hot air or gas to minimize heating of adjacent components. Excessive airflow should be avoided since this may cause the package to skew. An airflow of 15 to 20 liters per minute is usually adequate. Once the solder joints have reflowed, the component should be lifted off the board using a vacuum pen. The next step is to clean the solder pads using solder braid and a blade shaped soldering tool. Finally, the pads should be cleaned with a solvent. The solvent is usually specific to the type of solder paste used in the original assembly and the paste manufacturers recommendations should be followed. 16. Mounting
16.1 PCB design guidelines
The terminals on the underside of the package are rectangular in shape with a rounded edge on the inside. Electrical connection between the package and the printed-circuit board is made by printing solder paste onto the PCB footprint followed by component placement and reflow soldering. The PCB footprint shown inFigure 20 is designed to form reliable solder joints. The use of solder resist between each solder land is recommended. PCB tracks should not be routed through the corner areas shown inFigure 20. This is because there is a small, exposed remnant of the leadframe in each corner of the package, left over from the cropping process. Good surface flatness of the PCB lands is desirable to ensure accuracy of placement after soldering. Printed-circuit boards that are finished with a roller tin process tend to leave small lumps of tin in the corners of each land. Levelling with a hot air knife improves flatness. Alternatively, an electro-less silver or silver immersion process produces completely flat PCB lands.
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 17 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved.
16.2 Solder paste printing
The process of printing the solder paste requires care because of the fine pitch and small size of the solder lands. A stencil thickness of 0.125 mm is recommended. The stencil apertures can be made the same size as the PCB lands inFigure 20. The type of solder paste recommended for MLF packages is “No clean”, Type 3, due to the difficulty of cleaning flux residues from beneath the MLF package. All dimensions in mm. Fig 20. PCB footprint for SOT687-1 package (reflow soldering).
0.4 SP (2·)
11.15 OA (2·) 7.6 Cu (2·) 10.8 Cu (2·) 0.9 SP (10·) 0.5 SP (4·) 1 SP (10·) 8.9 Cu (2·) 1 SP (8·) 1 SP (8·)
0.28 Cu (68·)
0.4 SP 0.4 SP0.6 Cu 4.1 8.63 OA (4·) 4.1 0.6 Cu e = 0.5 MGW820 solder lands Cu pattern clearance solder paste occupied area 0.1 0.2 0.025
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain Product data Rev. 02 — 24 November 2003 18 of 20 9397 750 11943 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 17. Revision history Table 6: Revision history Rev Date CPCN Description 02 20031124 Product data (9397 750 11943) Modifications:
- Table 5 “Characteristics” on page 6: Min, Typ and Max values changed for VIH, VIL and td(3-state). 01 20020715 - Product data (9397 750 10031)
Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 02 — 24 November 2003 19 of 20 Contact information For additional information, please visithttp://www.semiconductors.philips.com. 18. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 19. Definitions Short-form specification —The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 20. Disclaimers Life support —These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes —Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
© Koninklijke Philips Electronics N.V. 2003. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 24 November 2003 Document order number: 9397 750 11943
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Philips Semiconductors PIP202-12M-2 DC-to-DC converter powertrain