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Technical content
Data Sheet: Technical Data Document Number: IMX8MMIEC Rev. 1, 07/2020
Ordering Information
MIMX8MM6CVTKZAA MIMX8MM5CVTKZAA MIMX8MM4CVTKZAA MIMX8MM3CVTKZAA MIMX8MM2CVTKZAA MIMX8MM1CVTKZAA
Package Information
FCBGA 14 x 14 mm, 0.5 mm pitch NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. 1 i.MX 8M Mini introduction The i.MX 8M Mini applicat ions processor represents NXP’s latest video and a udio experience combining state-of-the-art media- specific features with high-performance processing while optimized for lowest power consumption. The i.MX 8M Mini family of processors features advanced implementation of a quad Arm® Cor- tex®-A53 core, which operates at speeds of up to 1.6 GHz. A general purpose Cortex®-M4 400 MHz core processor is for low-power processing. The DRAM controller supports 32-bit/16-bit LPDDR4, DDR4, and DDR3L memory. A wide range of audio interfaces are available, including I2S, AC97, TDM, and S/PDIF. There are a number of other interfaces for connecting peripherals, such as USB, PCIe, and Ethernet. i.MX 8M Mini Applications Processor Datasheet for Industrial Products 2.1. Recommended connections for unused input/output 12
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Table 1. Features
- 32 KB L1 Instruction Cache 32 KB L1 Data Cache Media Processing Engine (MPE) with NEON technology supporting the Advanced Single Instruction Multiple Data architecture: Floating Point Unit (FPU) with su pport of the VFPv4-D16 architecture Support of 64-bit Armv8-A architecture
512 KB unified L2 cache
1 Tx and 1Rx lane. Support over 20 channels of audio subject to I/O limitations. Table 1. Features (continued)
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The actual feature set depends on the part numbers as described in Table 2. interfaces, may not be enabled for specific part numbers.
1.1 Block diagram
Figure 1 shows the functional modules in the i.MX 8M Mini applications processor system. Figure 1. i.MX 8M Mini system block diagram
1 GB Ethernet
32 KB Secure RAM
32 KB I-cache 32 KB D-cache
512 KB L2 Cache
16 KB I-cache 16 KB D-cache
256 KB TCM
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1.2 Ordering information
have questions about available parts, contact your NXP representative. Contact an NXP representative for additional details. Table 2. Orderable part numbers
53 CPU
Figure 2. Part number nomenclature—i.MX 8M Mini family of processors
1.8 GHz LZ
1.6 GHz KZ
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2 Modules list
describes these modules in alphabetical order. Table 3. i.MX 8M Mini modules list low speed clock. It can be supplied by external 32.768 KHz oscillator. DMA controller used for GPMI2 operation. used as a customer microcontroller. Institute of Standards and Technology (NIST). Mini processors, the secure memory provided is 32 KB. system, and also for the system power management. comprehensive security policy within the i.MX 8M Mini platform. The DAP also provides debugger access to JTAG scan chains. one chip select is supported.
module supports up to 32 bits of I/O. supports separate DMA channels for each NAND device. interrupts at regular intervals with minimal processor intervention. an external clock or on an internal clock. interactive graphics applications on displays. Table 3. i.MX 8M Mini modules list (continued)
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which operates up to a maximum bit rate of 1.5 Gbps. operating up to a maximum bit rate of 1.5 Gbps. 256 KB multimedia RAM through a 64-bit AXI bus. PCIe1 PCI Express 2.0 The PCIe IP prov ides PCI Express Gen 2.0 functionality. PDM Pulse Density Modulation The PDM supports up to 8-channels (4 lanes). such as I2S, AC97, TDM, and codec/DSP interfaces.
path to the DRAM controller.
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2.1 Recommended connections for unused input/output
to reduce overall board power. Table 4 shows the recommended connections for unused power supply rails. All the MMC/SD/SDIO controller IPs are based on the uSDHC IP. SD/SDIO standard, up to version 3.0. MMC standard, up to version 5.1. 1.8 V and 3.3 V operation, but do not support 1.2 V operation. 1-bit/4-bit SD and SDIO mo des, 1-bit/4-bit/8-bit MMC mode. complete list of the VPU’s decoding and encoding capabilities. point evokes an external event on the WDOG line. Table 4. Recommended connections for unused power supply rails
Table 5 shows recommended connections for unused signal contacts/interfaces. Table 5. Recommended connections for unused signal contacts/interfaces Table 4. Recommended connections for unused power supply rails (continued)
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Electrical characteristics
3 Electrical characteristics
This section provides the device and module-level electrical characteristics for the i.MX 8M Mini family of processors.
3.1 Chip-level conditions
This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference to the individual tables and sections.
3.1.1 Absolute maximum ratings
Stresses beyond those listed under Table 7 may affect reliability or cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the operating ranges or parameters tables is not implied. Table 6. i.MX 8M Mini chip-level conditions Table 7. Absolute maximum ratings
i.MX 8M Mini Applications Processor Datasheet for Industrial Products, Rev. 1, 07/2020 NXP Semiconductors 15 GPIO supply voltage NVCC_JTAG, NVCCGPIO1, NVCC_ENET, NVCC_SD1, NVCC_SD2, NVCC_NAND, NVCC_SA1, NVCC_SAI2, NVCC_SAI3, NVCC_SAI5, NVCC_ECSPI, NVCC_I2C, NVCC_UART, NVCC_CLK -0.3 3.8 V — GPIO pre-driver supply voltage PVCC0_1P8, PVCC1_1P8, PVCC2_1P8 -0.3 2.15 V — Isolated core supply voltage VDD_ANA_0P8 -0.3 1.15 V — Analog core supply voltage VDD_ANA0_1P8 -0.3 2.15 V — VDD_ANA1_1P8 -0.3 2.15 V — Arm PLL supply voltage VD D_ARM_PLL_0P8 -0.3 0.95 V — VDD_ARM_PLL_1P8 -0.3 2.15 V — MIPI PHY supply voltage VDD_MIPI_0P9 -0.3 1.05 V — VDD_MIPI_1P2 -0.3 1.45 V — VDD_MIPI_1P8 -0.3 2.15 V — PCIe PHY supply voltage VDD_PCIE_0P8 -0.3 0.95 V — VDD_PCIE_1P8 -0.3 2.15 V — USB PHY supply voltage VDD_USB_0P8 -0.3 0.95 V — VDD_USB_1P8 -0.3 2.15 V — VDD_USB_3P3 -0.3 3.95 V — USB_VBUS input detected USB1_VBUS, USB2_VBUS -0.3 3.95 V — XTAL supply voltage VDD_24M_XTAL_1P8 -0.3 2.15 V — Storage temperature range T STORAGE -40 150 oC— Table 7. Absolute maximum ratings (continued)
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3.1.2 Thermal resistance
3.1.2.1 FCBGA package thermal resistance
Table 9 displays the 14 x 14 mm FCBGA package thermal resistance data. Table 8. Electrostatic discharge and latch up ratings Table 9. Thermal resistance data 2 Per SEMI G38-87 and JESD51-2 with the single layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal. top surface of the board near the package.
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3.1.3 Operating ranges
Table 10 provides the operating ranges of the i.MX 8M Mini applications processor. For details on the chip's power structure, see the “Power Management Unit (PMU)” chapter of the i.MX 8M Mini Table 10. Operating ranges1
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PVCC0_1P8, PVCC1_1P8, PVCC2_1P8 1.650 1.800 1.950 V Power supply for GPIO pre-driver VSS — — — V Ground for all core logic and I/O NVCC_DRAM 1.283 1.35 1.425 V DDR3L 1.14 1.2 1.26 V DDR4 1.06 1.1 1.17 V LPDDR4 DRAM_VREF 0.49 x NVCC_DRAM 0.5 x NVCC_DRAM 0.51 x NVCC_DRAM V Internal output, no connection is needed. should be connected to the separate logic power. VDD_ANA0_1P8 VDD_ANA1_1P8 1.71 1.8 1.89 V Analog 1.8 V core power VDD_ANA_0P8 0.780 0.820 0.900 V Isolated 0.8 V core power VDD_ARM_PLL_0P8 0.780 0.820 0.900 V Arm PLL 0.8 V power VDD_ARM_PLL_1P8 1.71 1.8 1.89 V Arm PLL 1.8 V power VDD_24M_XTAL_1P8 1.71 1.8 1.89 V XTAL 1.8 V power VDD_DRAM_PLL_1P8 1.71 1.8 1.89 V Analog 1.8 V core power VDD_MIPI_0P9 0.855 0.9 1.000 V 0.9 V power for PLL and internal logic VDD_MIPI_1P2 1.14 1.2 1.26 V 1.2 V power for analog VDD_MIPI_1P8 1.71 1.8 1.89 V 1.8 V power for PLL and analog VDD_PCI_0P8 5,6 0.805 0.850 0.900 V Digital supply for PCIe PHY VDD_PCI_1P85 1.71 1.8 1.89 V 1.8 V supply for PCIe PHY VDD_USB_0P8 0.780 0.820 0.900 V Digital power supply from PHY’s I/O power pads VDD_USB_1P8 1.71 1.80 1.89 V 1.8 V analog power supply VDD_USB_3P3 3.069 3.30 3.6 V 3.3 V analog power supply USB1_VBUS USB2_VBUS 0.800 1.40 3.60 V USB_VBUS input detect signal Temperature Sensor Accuracy — ±3 ±5 °C Sensing temperature range 10°C to 105°C T J -40 — +105 oCS e e Table 2 for complete list of junction temperature capabilities. 1 The BD71847MWV PMIC does not support 0.950 V for VDD_GPU, VDD_VPU, and VDD_DRAM. For this PMIC, 0.975 V typical is acceptable and supported. 2 Applying the maximum voltage results in maximum power consumption and heat generation. A voltage set point = (Vmin + the supply tolerance) is recommended. This results in an optimized power/speed ratio. Table 10. Operating ranges1 (continued)
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3.1.4 External clock sources
Each i.MX 8M Mini processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency (XTALI). The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real time clock operation, and slow system and watch-dog counters. The clock input can only be connected to an external oscillator. RTC_XTALO should be directly connected to VDD_SNVS_0P8. The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input can be connected to either an external oscillator or a crystal using internal oscillator amplifier. Table 11 shows the interface frequency requirements. Table 12 shows the external input clock for OSC32K. 3 Overdrive maximum voltage includes all the nominal frequencies. 4 Booting VDD_SOC at 0.800 V ±5% is acceptable (Vmin = 0.760 V). Software is expected to program the VDD_SOC voltage to the typical value in this table prior to first DRAM memory access. 5 Ensure the VDD_PCI_1P8 does not have more than 40 mVpp AC power supply noise superimposed on the high power supply voltage for the PHY core (1.8 V nominal DC value). Simultaneously, the VDD_PCI_0P8 should have no more than 20 mVpp AC power supply noise superimposed on the low power supply voltage for th PHY core (0.9 V nominal DC value for the overdrive). 6 It can be min 0.78 V when supplied but not operating PCIe. 7 “EN” of TMU Enable Register (TMU_TER) is required to be always enabled for the part to operate correctly. Table 11. External input clock frequency 1 The required frequency stability of this clock source is application dependent. 2 Recommended nominal frequency 32.768 kHz. 3 External oscillator or a fundamental frequency crystal appropriately coupled to the internal oscillator amplifier. should be directly connected to VDD_SNVS_0P8 when using an external 32.768 kHz oscillator. There is no internal RC oscillator. Table 12. External input clock for OSC32K
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3.1.5 Maximum supply currents
Power consumption is highly dependent on the application. Estimating the maximum supply currents required for power supply design is difficult because the use cases that requires maximum supply current is not a realistic use cases. To help illustrate the effect of the application on power consumption, data was collected while running consumer standard benchmarks that are designed to be compute and graphic intensive. The results provided are intended to be used as guidelines for power supply design.
3.1.6 Power modes
The i.MX 8M Mini processors support the following power modes:
- RUN Mode: All external power ra ils are on, CPU is active and running; other internal modules can be on/off based on application.
- IDLE Mode: When there is no th read running and all high-speed devices are not active, the CPU can automatically enter this mode. The CPU can be in the power-gated state but with L2 data retained, DRAM and the bus clock are reduced. Most of the internal logic is clock gated but still
Table 13. Maximum supply currents
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- SUSPEND Mode: The most efficient power saving mode where all the cloc ks are off and all the unnecessary power supplies are off.
- SNVS Mode: This mode is also called RTC mode . Only the power for the SNVS domain remains on to keep RTC and SNVS logic alive.
- OFF Mode: All power rails are off. Table 15 summarizes the external power supply states in all the power modes.
Table 14. Chip power in different LP mode measurement application note for more details. 2 Sum of the listed supply rails. Table 15. The power supply states
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3.2 Power supplies requir ements and restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations:
- Excessive current during power-up phase
- Prevention of the device from booting
- Irreversible damage to the pr ocessor (worst-case scenario) Misc_1P81 OFF OFF ON ON ON Misc_0P81 OFF OFF ON ON ON VDD_MIPI_1P2 OFF OFF OFF ON ON VDD_MIPI_0P9 OFF OFF OFF ON ON VDD_DRAM_PLL_0P8 OFF OFF ON ON ON VDD_SNVS_0P8 OFF ON ON ON ON NVCC_SNVS_1P8 OFF ON ON ON ON NVCC_<XXX> OFF OFF ON ON ON PVCCx_1P8 OFF OFF ON ON ON NVCC_DRAM OFF OFF ON ON ON
1 See Table 16
Table 16. Group name Table 15. The power supply states (continued)
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3.2.1 Power-up sequence
Figure 5 illustrates the power-up sequence of i.MX 8M Mini processor. Figure 3. The power-up sequence
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Table 17 represents the timing parameters of the power-up sequence.
3.2.2 Power-down sequence
Figure 5 illustrates the power-down sequence of i.MX 8M Mini processor. Table 17. Power-up sequence 1 The values of T13 depend on T2. RTC_RESET_B must be de-assert before POR_B de-asserts. t1 Uncertain period before PMIC_ON_RE Q assert during VDD_SNVS_0P8 ramp up. During power-up, make sure NVCC_xxx - PVCCx_1P8 < 2 V.
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Table 18 represents the timing parameters of the power-down sequence.
3.3 PLL electrical characteristics
Table 19 shows PLL electrical characteristics. Table 18. Power-down sequence During power-down, make sure NVCC_xxx - PVCCx_1P8 < 2 V. Table 19. PLL electrical parameters
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3.4 On-chip oscillators
3.4.1 OSC24M
A 24 MHz oscillator is used as the primary clock source for the PLLs to generate the clock for the CPU, BUS, and high-speed interfaces. For fractional PLLs, the 24 MHz clock from the oscillator can be used as the PLL reference clock directly. SYS_PLL2 Clock output range 1 GHz Reference clock 24 MHz Lock time 25 s SYS_PLL3 Clock output range 600 MHz ~ 1 GHz Reference clock 24 MHz Lock time 25 s ARM_PLL Clock output range 800 MHz ~1.6 GHz Reference clock 24 MHz Lock time 25 s DRAM_PLL Clock output range Maximum 750 MHz Reference clock 24 MHz Lock time 375 s GPU_PLL Clock output range Maximum 1 GHz Reference clock 24 MHz Lock time 25 s VPU_PLL Clock output range 400 MHz ~ 800 MHz Reference clock 24 MHz Lock time 25 s Table 20. Crystal specifications1 Table 19. PLL electrical parameters (continued)
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3.4.2 OSC32K
An external 32.768 kHz oscillator is necessary.
3.5 General purpose I/O (GPIO) DC parameters
Table 21 shows DC parameters for GPIO pads. The parameters in Table 21 are guaranteed per the operating ranges in Table 10, unless otherwise noted. 1 Actual working drive level is depend on real design. Please contact crystal vendor for selecting drive level of crystal. Table 21. GPIO DC parameters 1 Does not support internal pull-up or pull-down for 3.3 V IOs. Table 22. Additional leakage parameters
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3.5.1 DDR I/O DC elec trical characteristics
The DDR I/O pads support LPDDR 4, DDR4, and DDR3L operational modes. The DDR Memory Controller (DDRMC) is designed to be compatible with JEDEC-compliant SDRAMs. DDRMC operation is contingent upon the board’s DDR design adherence to the DDR design and layout requirements stated in the hardware development guide for the i.MX 8M Mini applications processor.
3.6 I/O AC parameters
This section includes the AC parameters of the following I/O types:
- General Purpose I/O (GPIO) The GPIO load circuit and output transition time waveforms are shown in Figure 5 and Figure 6.
Figure 5. Load circuit for output Figure 6. Output transition time waveform
3.6.1 General purpose I/O AC parameters
This section presents the I/O AC parameters for GPIO in different modes. Table 22. Additional leakage parameters (continued)
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3.7 Output buffer impedance parameters
This section defines the I/O impedance parameters of the i.MX 8M Mini family of processors for the following I/O types: NOTE DDR I/O output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see Figure 7). Table 23. Maximum frequency of operation for input Table 24. Maximum frequency of operation for output
i.MX 8M Mini Applications Processor Datasheet for Industrial Products, Rev. 1, 07/2020 NXP Semiconductors 31 Figure 7. Impedance matching load for measurement
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3.7.1 DDR I/O output buffer impedance
Table 25 shows DDR I/O output buffer impedance of i.MX 8M Mini family of processors. Note: 1. Output driver impedance is controlled across PVTs using ZQ calibration procedure. 2. Calibration is done against 240 external reference resistor. 3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.
3.8 System modules timing
This section contains the timing and electrical parameters for the modules in each i.MX 8M Mini processor.
3.8.1 Reset timings parameters
Figure 8 shows the reset timing and Table 26 lists the timing parameters. Figure 8. Reset timing diagram Table 25. DDR I/O output buffer impedance Table 26. Reset timing parameters
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3.8.2 WDOG Reset timing parameters
Figure 9 shows the WDOG reset timing and Table 27 lists the timing parameters. Figure 9. WDOGx_B timing diagram Manual (IMX8MMRM) for detailed information.
3.9 External peripheral interface parameters
The following subsections provide information on external peripheral interfaces.
3.9.1 ECSPI timing parameters
parameters for master and slave modes. Table 27. WDOGx_B timing parameters
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3.9.1.1 ECSPI Master mode timing
Figure 10 depicts the timing of ECSPI in master mode. Table 28 lists the ECSPI master mode timing characteristics. Figure 10. ECSPI Master mode timing diagram Table 28. ECSPI Master mode timing parameters 2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
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3.9.1.2 ECSPI Slave mode timing
Figure 11 depicts the timing of ECSPI in Slave mode. Table 29 lists the ECSPI Slave mode timing characteristics. Figure 11. ECSPI Slave mode timing diagram Table 29. ECSPI Slave mode timing parameters
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3.9.2 Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC
This section describes the electrical information of the uSDHC, which includes SD/eMMC 5.1 (single data rate) timing, eMMC 5.1/SD3.0 (dual data rate) AC timing, and SDR50/SDR104 AC timing. Figure 12 depicts the timing of SD3.0/eMMC5.1 (SDR), and Table 30 lists the SD3.0/eMMC5.1 (SDR) timing characteristics. Figure 12. SD3.0/eMMC5.1 (SDR) timing Table 30. SD3.0/eMMC5.1 (SDR) interface timing specification
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3.9.2.3 HS400 DDR AC timing
Figure 14 depicts the timing of HS400 mode, and Table 32 lists the HS400 timing characteristics. Be aware that only data is sampled on both edges of the clock (not applicable to CMD). The CMD input/output timing for HS400 mode is the same as CMD input/output timing for SDR104 mode. Check SD5, SD6, and SD7 parameters in Table 34 SDR50/SDR104 Interface Timing Specification for CMD input/output timing for HS400 mode. Figure 14. HS400 timing Table 32. HS400 interface timing specification Table 31. eMMC5.1/SD3.0 (DDR) interface timing specification (continued)
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3.9.2.4 HS200 Mode AC timing
Figure 15 depicts the timing of HS200 mode, and Table 33 lists the HS200 timing characteristics. Figure 15. HS200 timing Table 33. HS200 interface timing specification 1 HS200 is for 8 bits while SDR104 is for 4 bits. Table 32. HS400 interface timing specification (continued)
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3.9.2.5 SDR50/SDR104 AC timing
Figure 16 depicts the timing of SDR50/SDR104, and Table 34 lists the SDR50/SDR104 timing characteristics. Figure 16. SDR50/SDR104 timing Table 21, "GPIO DC parameters," on page 28. Table 34. SDR50/SDR104 interface timing specification 1 Data window in SDR100 mode is variable.
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3.9.3 Ethernet controller (ENET) AC electrical specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. Table 35. ENET signal mapping are two RGMII clock schemes. for PHY, and MAC also use this 50M clock. MAC use external 50M clock.
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3.9.3.1 RMII mode timing
Figure 17 shows RMII mode timings. Table 36 describes the timing parameters (M16–M21) shown in the figure. I2C1_SDA enet1.MDIO RMII/RGMII ALT1 I/O — I2C2_SCL enet1.1588_EV ENT1_IN RMII/RGMII ALT1 O — I2C2_SDA enet1.1588_EV ENT1_OUT RMII/RGMII ALT1 I/O — GPIO1_IO00 ENET_PHY_RE F_CLK_ROOT RGMII ALT1 O Reference clock for PHY. GPIO1_IO08 enet1.1588_EV ENT0_IN RMII/RGMII ALT1 I Capture/compar e block input/output event bus signal. When configured for capture and a rising edge is detected, the current timer value is latched and transferred into the corresponding ENET_TCCRn register for inspection by software. When configured for compare, the corresponding signal 1588_EVENT is asserted for one cycle when the timer reaches the compare value programmed in register ENET_TCCRn. An interrupt or DMA request can be triggered if the corresponding bit in ENET_TCSRn[TIE] or ENET_TSCRn[TDRE] is set. GPIO1_IO09 enet1.1588_EV ENT0_OUT RMII/RGMII ALT1 O — Table 35. ENET signal mapping (continued)
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3.9.3.2 RGMII signal switching specifications
Table 36. RMII signal timing Table 37. RGMII signal switching specifications1
3 Data to clock output skew at transmitter -500 500 ps
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Figure 18. RGMII transmit signal timing diagram original Figure 19. RGMII receive signal timing diagram original
1 The timings assume the following configuration:
2 For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.
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3.9.4 General-purpose media interface (GPMI) timing
up to 200 MB/s I/O speed and individual chip select. separately, as described in the following subsections. Asynchronous mode. Table 38 describes the timing parameters (NF1–NF17) that are shown in the figures. Figure 21. Command Latch cycle timing diagram
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Figure 22. Address Latch cycle timing diagram Figure 23. Write Data Latch cycle timing diagram Figure 24. Read Data Latch cycle timing diagram (Non-EDO Mode) Figure 25. Read Data Latch cycle timing diagram (EDO mode)
i.MX 8M Mini Applications Processor Datasheet for Industrial Products, Rev. 1, 07/2020 NXP Semiconductors 47 In EDO mode (Figure 24), NF16/NF17 are different from the definition in non-EDO mode (Figure 23). They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical values for them are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI samples NAND_DATAxx at the rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 8M Mini 0x8 at 50 MT/s EDO mode. But if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. Table 38. Asynchronous mode timing parameters1
1 GPMI’s Asynchronous mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD. This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings. 2 AS minimum value can be 0, while DS/DH minimum value is 1. 3 T = GPMI clock period -0.075 ns (half of maximum p-p jitter). 4 NF12 is guaranteed by the design.
6 EDO mode, GPMI clock 100 MHz
(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).
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3.9.4.2 Source synchronous mode AC timing (ONFI 2.x compatible) Figure 26 to Figure 28 show the write and read timing of Source Synchronous mode. Figure 26. Source Synchronous mode command and address timing diagram
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Figure 29. NAND_DQS/NAND_DQ read valid window Table 39. Source Synchronous mode timing parameters1
1 GPMI’s Source Synchronous mode output timing can be controlled by the module’s internal registers
on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings. 2 T = tCK(GPMI clock period) –0.075 ns (half of maximum p-p jitter).
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3.9.4.3.1 Command and address timing
ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing.
3.9.4.3.2 Read and write timing
mode AC Timing,” for details.
3.9.4.4 Toggle mode AC Timing
3.9.4.4.1 Command and address timing
Toggle mode command and address timing is the same as ONFI 1.0 compatible Asynchronous mode AC timing. See Section 3.9.4.1, Asynchronous mode AC timing (ONFI 1.0 compatible),” for details.
3.9.4.4.2 Read and write timing
Figure 30. Toggle mode data write timing
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Figure 31. Toggle mode data read timing Table 40. Toggle mode timing parameters
i.MX 8M Mini Applications Processor Datasheet for Industrial Products, Rev. 1, 07/2020 NXP Semiconductors 53 For DDR Toggle mode, Figure 29 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI samples NAND_DATA[7:0] at both the rising and falling edges of a delayed NAND_DQS signal, which is provided by an internal DPLL. The delay value of this register can be controlled by the GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 8M Mini 0x7, which means a 1/4 clock cycle delay is expected. But if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay.
3.9.5 I 2C bus characteristics
The Inter-Integrated Circuit (I2C) provides functionality of a standard I2C master and slave. The I2C is designed to be compatible with the I2C Bus Specification, version 2.1, by Philips Semiconductor (now NXP Semiconductors).
3.9.6 MIPI D-PHY timing parameters
MIPI D-PHY electrical specifications are compliance. NF24 postamble delay tPOST POST_DELAY T + 0.43 [see note2] —n s NF28 Data write setup tDS 5 0.25 tCK - 0.32 — ns NF29 Data write hold tDH 5 0.25 tCK - 0.79 — ns NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ 6 —3 . 1 8 n s NF31 NAND_DQS/NAND_DQ read hold skew tQHS 6 —3 . 2 7 n s 1 AS minimum value can be 0, while DS/DH minimum value is 1. 2 T = tCK (GPMI clock period) -0.075 ns (half of maximum p-p jitter). 3 CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started with enough time of ALE/CLE assertion to low level.
4 PRE_DELAY+1 (AS+DS)
5 Shown in Figure 30. 6 Shown in Figure 31. Table 40. Toggle mode timing parameters (continued)
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3.9.7 PCIe PHY parameters
The PCIe interface is designed to be compatible with PCIe specification Gen2 x1 lane and supports the PCI Express 1.1/2.0 standard.
3.9.7.1 PCIE_RESREF reference resistor connection
The impedance calibration process requires connection of reference resistor 8.2 k1% precision resistor on PCIE_RESREF pads to ground. It is used for termination impedance calibration.
3.9.8 PDM timing parameters
Figure 32 illustrates the input timing of the PDM. Table 41. MIPI PHY worst power dissipation1 (at least 1 clock lane enable).
2.1 Gbps
Table 42. PCIe DC electrical characteristics
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3.9.9 Pulse width modulator (PWM) timing parameters
Figure 33 depicts the timing of the PWM, and Table 43 lists the PWM timing parameters. Figure 33. PWM timing Table 43. PWM output timing parameters
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3.9.10 FlexSPI timing parameters
Measurements are with a load of 15 pF and an input slew rate of 1 V/ns.
3.9.10.1 FlexSPI input/read timing
There are three sources for the internal sample clock for FlexSPI read data:
- Dummy read strobe genera ted by FlexSPI controller and looped back internally (FlexSPIn_MCR0[RXCLKSRC] = 0x0)
- Dummy read strobe generate d by FlexSPI controller and looped back through the DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1)
- Read strobe provided by memory device and input from DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x3) The following sections describe input signal timing for each of these four internal sample clock sources.
3.9.10.1.1 SDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x0, 0x1
Figure 34. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1 Table 44. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0 Table 45. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1
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3.9.10.1.2 SDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x3
There are two cases when the memory provides both read data and the read strobe in SDR mode:
- A 1 — Memory generates both read data and read strobe on SCK rising edge (or falling edge)
- A 2 — Memory generates read data on SCK falling edge and generates read strobe on SCK rising edge
Figure 35. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1) Table 46. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1) Table 47. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)
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Figure 36. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2) samples read data on a half-cycle delayed DQS falling edge.
3.9.10.1.3 DDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x0, 0x1
Figure 37. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1 Table 48. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0 Table 49. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1
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3.9.10.1.4 DDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x3
Figure 38. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3
3.9.10.2 FlexSPI output/write timing
3.9.10.2.1 SDR mode
Table 50. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case 1) Table 51. FlexSPI output timing in SDR mode
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Figure 39. FlexSPI output timing in SDR mode
3.9.10.2.2 DDR mode
FlexSPI SDR input timing specifications. Processor Reference Manual (IMX8MMRM) for more details. Table 52. FlexSPI output timing in DDR mode FlexSPI SDR input timing specifications. Processor Reference Manual (IMX8MMRM) for more details.
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3.9.11 SAI/I2S switching specifications
This section provides the AC timings for the SAI in Master (clocks driven) and Slave (clocks input) modes. (SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below. Table 53. Master mode SAI timing (50 MHz)1 1 To achieve 50 MHz for BCLK operation, clock must be set in feedback mode. Table 54. Master mode SAI timing (25 MHz)
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Figure 41. SAI timing—Master modes Table 55. Slave mode SAI timing (50 MHz)1 1 TX does not support 50 MHz operation in Slave mode. Table 56. Slave mode SAI timing (25 MHz) Table 54. Master mode SAI timing (25 MHz) (continued)
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3.9.12 SPDIF timing parameters
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode. Table 57. SPDIF timing parameters Table 56. Slave mode SAI timing (25 MHz) (continued)
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Figure 43. SPDIF_SR_CLK timing diagram Figure 44. SPDIF_ST_CLK timing diagram Table 57. SPDIF timing parameters (continued)
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3.9.13 UART I/O configuration and timing parameters
3.9.13.1 UART RS-232 I/O configu ration in different modes
The i.MX 8M Mini UART interfaces can serve both as DTE or DCE device. This can be configured by the DCEDTE control bit (default 0—DCE mode). Table 58 shows the UART I/O configuration based on the enabled mode.
3.9.13.2 UART RS-232 Serial mode timing
This section describes the electrical information of the UART module in the RS-232 mode.
3.9.13.2.1 UART transmitter
Figure 45 depicts the transmit timing of UART in the RS-232 Serial mode, with 8 data bit/1 stop bit format. Table 59 lists the UART RS-232 Serial mode transmit timing characteristics. Figure 45. UART RS-232 Serial mode transmit timing diagram Table 58. UART I/O configuration vs. mode Table 59. RS-232 Serial mode transmit timing parameters 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
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3.9.13.2.2 UART receiver
Figure 46 depicts the RS-232 Serial mode receive timing with 8 data bit/1 stop bit format. Table 60 lists Serial mode receive timing characteristics. Figure 46. UART RS-232 Serial mode receive timing diagram
3.9.14 USB PHY parameters
This section describes the USB-OTG PHY parameters.
3.9.14.1 Pad/Package/Board connections
The USBx_VBUS pin cannot directly connect to the 5 V VBUS voltage on the USB2.0 link. Each USBx_VBUS pin must be isolated by an external 30 K1% precision resistor.
3.9.14.2 USB PHY worst power consumption
Table 61 shows the USB 2.0 PHY worst power dissipation. Table 60. RS-232 Serial mode receive timing parameters 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
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4 Boot mode configuration
4.1 Boot mode configuration pins
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse. Table 62. Fuses and associated pins used for boot
4.2 Boot device interface allocation
which are configured during boot when appropriate. Table 63. Interface allocation during boot on the fuse “CS select (SPI only)“. on the fuse “CS select (SPI only)“. on the fuse “CS select (SPI only)“. 8-bit, only CS0 is supported.
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Package information and contact assignments
5 Package information and contact assignments
This section includes the contact assignment information and mechanical package drawing. 5.1 14 x 14 mm package information 5.1.1 14 x 14 mm, 0.5 mm pitch, ball matrix Figure 47 shows the top, bottom, and side views of the 14 × 14 mm FCBGA package.
Figure 47. 14 X 14 MM BGA, case x package top, bottom, and side views
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Table 64 shows supplies contact assignments for the 14 x 14 mm package. Table 64. i.MX 8M Mini 14 x 14 mm supplies contact assignments
Table 65 shows an alpha-sorted list of functional contact assignments for the 14 x 14 mm package. Table 65. i.MX 8M Mini 14 x 14 mm functional contact assignments Table 64. i.MX 8M Mini 14 x 14 mm supplies contact assignments (continued)
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Table 65. i.MX 8M Mini 14 x 14 mm functional contact assignments (continued)
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Table 66 shows the i.MX 8M Mini 14 x 14 mm 0.5 mm pitch ball map. deasserted, it becomes input with PD.
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Table 66. 14 x 14 mm, 0.5 mm pitch ball map
Table 66. 14 x 14 mm, 0.5 mm pitch ball map (continued)
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5.2 DDR pin function list
Table 67 shows the DDR pin function list. Table 67. DDR pin function list
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Table 67. DDR pin function list (continued)
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Revision history
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6 Revision history
Table 68 provides a revision history for this data sheet. Table 68. Revision history
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