PIMX8MM3CVTKZDA

IMX8MMIEC_V01 NXP | Alldatasheet

Document overview

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Technical content

Data Sheet: Technical Data Document Number: IMX8MMIEC Rev. 2, 11/2022

Ordering Information

MIMX8MM6CVTKZAA MIMX8MM5CVTKZAA MIMX8MM4CVTKZAA MIMX8MM3CVTKZAA MIMX8MM2CVTKZAA MIMX8MM1CVTKZAA

Package Information

FCBGA 14 x 14 mm, 0.5 mm pitch NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. 1 i.MX 8M Mini introduction The i.MX 8M Mini applications processor represents NXP’s latest video and audio experience combining state-of-the-art media-specific features with high-performance processing while optimized for lowest power consumption. The i.MX 8M Mini family of processors features advanced implementation of a quad Arm® Cor- tex®-A53 core, which operates at speeds of up to 1.6 GHz. A general purpose Cortex®-M4 400 MHz core processor is for low-power processing. The DRAM controller supports 32-bit/16-bit LPDDR4, DDR4, and DDR3L memory. A wide range of audio interfaces are available, including I2S, AC97, TDM, and S/PDIF. There are a number of other interfaces for connecting peripherals, such as USB, PCIe, and Ethernet. i.MX 8M Mini Applications Processor Datasheet for Industrial Products 2.1. Recommended connections for unused input/output 12

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Table 1. Features

• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• Media Processing Engine (MPE) with NEON technology supporting the Advanced Single Instruction Multiple Data architecture:
• Floating Point Unit (FPU) with support of the VFPv4-D16 architecture Support of 64-bit Armv8-A architecture

512 KB unified L2 cache

• low power standby mode
• IoT features including Weave
• Manage IR or Wireless Remote Cortex M4 CPU:
• 16 KB L1 Instruction Cache
• 16 KB L1 Data Cache
• 256 KB tightly coupled memory (TCM) Connectivity One PCI Express (PCIe)
• Single lane supporting PCIe Gen2
• Dual mode operation to function as root complex or endpoint
• Integrated PHY interface
• Support L1 low power sub-state Two USB 2.0 OTG controllers with integrated PHY interfaces:
• Spread spectrum clock support Three Ultra Secure Digital Host Controller (uSDHC) interfaces:
• MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec
• SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec
• Support for SDXC (extended capacity) One Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE), Ethernet AVB, and IEEE 1588 Four Universal Asynchronous Receiver/Transmitter (UART) modules Four I2C modules Three ECSPI modules On-chip memory Boot ROM (256 KB) On-chip RAM (256 KB + 32 KB) GPIO and pin multiplexing General-purpose input/output (GPIO) modules with interrupt capability Input/output multiplexing controller (IOMUXC) to provide centralized pad control Power management Temperature sensor with programmable trip points Flexible power domain partitioning with internal power switches to support efficient power management

• LPDDR4 (up to 1.5 GHz)
• DDR4-2400
• DDR3L-1600 8-bit NAND-Flash, including support for Raw MLC/SLC devices, BCH ECC up to 62-bit, and ONFi3.2 compliance (clock rates up to 100 MHz and data rates up to 200 MB/sec) eMMC 5.1 Flash (2 interfaces, uSDHC1 and uSDHC3) SPI NOR Flash (3 interfaces) FlexSPI with support for XIP (for ME in low-power mode) and parallel read mode of two identical FLASH devices Multimedia Video Processing Unit:
• 1080p60 VP9 Profile 0, 2 (10-bit)
• 1080p60 HEVC/H.265 Decoder
• 1080p60 AVC/H.264 Baseline, Main, High decoder
• 1080p60 VP8
• 1080p60 AVC/H.264 Encoder
• 1080p60 VP8
• TrustZone support Graphic Processing Unit:
• GCNanoUltra for 3D acceleration
• GC320 for 2D acceleration LCDIF Display Controller:
• Support up to 2 layers of overlay
• Support up to 1080p60 display through MIPI DSI MIPI Interface:
• 4-lane MIPI CSI interface
• 4-lane MIPI DSI interface Audio:
• S/PDIF input and output, including a new Raw Capture input mode
• Five synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, codec/DSP , and DSD interfaces, including one SAI with 8 Tx and 8 Rx lanes, one SAI with 4 Tx and 4 Rx lanes, two SAI with 2 Tx and 2 Rx lanes, and one SAI with 1 Tx and 1Rx lane. Support over 20 channels of audio subject to I/O limitations.
• 8-Channel Pulse Density Modulation (PDM) input System debug Arm CoreSight debug and trace architecture Trace Port Interface Unit (TPIU) to support off-chip real-time trace Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering Unified trace capability for Quad Cortex-A53 and Cortex-M4 CPUs Cross Triggering Interface (CTI) Support for 5-pin (JTAG) debug interface

Table 1. Features (continued)

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The actual feature set depends on the part numbers as described in Table 2. interfaces, may not be enabled for specific part numbers.

• Support Arm Cortex-A53 MPCore TrustZone On-chip RAM (OCRAM) secure region protection using OCRAM controller High Assurance Boot (HAB) Cryptographic acceleration and assurance (CAAM) module and Assurance Module:
• Support Widevine and PlayReady content protection
• Public Key Cryptography (PKHA) with RSA and Elliptic Curve (ECC) algorithms
• Real-time integrity checker (RTIC)
• DRM support for RSA, AES, 3DES, DES
• Side channel attack resistance
• True random number generation (RNG)
• Manufacturing protection support Secure non-volatile storage (SNVS):
• Secure real-time clock (RTC) Secure JTAG controller (SJC)

1.1 Block diagram

Figure 1 shows the functional modules in the i.MX 8M Mini applications processor system. Figure 1. i.MX 8M Mini system block diagram

1 GB Ethernet

32 KB Secure RAM

32 KB I-cache 32 KB D-cache

512 KB L2 Cache

16 KB I-cache 16 KB D-cache

256 KB TCM

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1.2 Ordering information

have questions about available parts, contact your NXP representative. Contact an NXP representative for additional details. Table 2. Orderable part numbers

53 CPU

Figure 2. Part number nomenclature—i.MX 8M Mini family of processors

1.8 GHz LZ

1.6 GHz KZ

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2 Modules list

describes these modules in alphabetical order. Table 3. i.MX 8M Mini modules list low speed clock. It can be supplied by external 32.768 KHz oscillator. DMA controller used for GPMI2 operation. used as a customer microcontroller. Institute of Standards and Technology (NIST). Mini processors, the secure memory provided is 32 KB. system, and also for the system power management. comprehensive security policy within the i.MX 8M Mini platform.

• System memory and peripheral registers
• All debug configuration registers The DAP also provides debugger access to JTAG scan chains. DDRC Double Data Rate Controller The DDR Controller has the following features:
• Supports 32/16-bit LPDDR4 (up to 1.5 GHz), DDR4-2400, and DDR3L-1600
• Supports up to 8 Gbyte DDR memory space eCSPI1 eCSPI2 eCSPI3 Configurable SPI Full-duplex enhanced Synchronous Serial Interface, with data rate up to 52 Mbit/s. Configurable to support Master/Slave modes, only one chip select is supported.

• Flexible sequence engine to support various flash vendor devices
• Single pad/Dual pad/Quad pad mode of operation
• Single Data Rate/Double Data Rate mode of operation
• Parallel Flash mode
• DMA support
• Memory mapped read access to connected flash devices
• Multi master access with priority and flexible and configurable buffer for each master GIC Generic Interrupt Controller The GIC handles all interrupts from the various subsystems and is ready for virtualization. GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 General Purpose I/O Modules Used for general purpose input/output to external ICs. Each GPIO module supports up to 32 bits of I/O. GPMI General Purpose Memory Interface The GPMI module supports up to 8x NAND devices and 62-bit ECC encryption/decryption for NAND Flash Controller (GPMI2). GPMI supports separate DMA channels for each NAND device. GPT1 GPT2 GPT3 GPT4 GPT5 GPT6 General Purpose Timer Each GPT is a 32-bit “free-running” or “set-and-forget” mode timer with programmable prescaler and compare and capture register. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in “set-and-forget” mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock. GPU3D Graphics Processing Unit-3D The GPU3D provides hardware acceleration for 3D graphics algorithms with sufficient processor power to run desktop quality interactive graphics applications on displays. I2C1 I2C2 I2C3 I2C4 I2C Interface I 2C provides serial interface for external devices. Data rates of up to 320 kbps are supported. IOMUXC IOMUX Control This module enables flexible I/O multiplexing. Each IO pad has a default as well as several alternate functions. The alternate functions are software configurable.

Table 3. i.MX 8M Mini modules list (continued)

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which operates up to a maximum bit rate of 1.5 Gbps. operating up to a maximum bit rate of 1.5 Gbps. user-visible mechanism for interfacing with on-chip fuse elements. 256 KB multimedia RAM through a 64-bit AXI bus. PCIe1 PCI Express 2.0 The PCIe IP provides PCI Express Gen 2.0 functionality. PDM Pulse Density Modulation The PDM supports up to 8-channels (4 lanes). such as I2S, AC97, TDM, and codec/DSP interfaces.

• Powered by a 16-bit Instruction-Set micro-RISC engine
• Multi channel DMA supporting up to 32 time-division multiplexed DMA channels
• 48 events with total flexibility to trigger any combination of channels
• Memory accesses including linear, FIFO, and 2D addressing
• Shared peripherals between Arm and SDMA
• Very fast Context-Switching with 2-level priority based preemptive multi tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers (increment, decrement, and no address changes on source and destination address)
• DMA ports can handle unidirectional and bidirectional flows (Copy mode)
• Up to 8-word buffer for configurable burst transfers for EMIv2.5
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available SJC Secure JTAG Controller The SJC provides JTAG interface (designed to be compatible with JTAG TAP standards) to internal logic. The i.MX 8M Mini family of processors uses JTAG port for production, testing, and system debugging. Additionally, the SJC provides BSR (Boundary Scan Register) standard support, designed to be compatible with IEEE 1149.1. The JTAG port must be accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. The i.MX 8M Mini SJC incorporates three security modes for protecting against unauthorized accesses. Modes are selected through eFUSE configuration. SNVS Secure Non-Volatile Storage Secure Non-Volatile Storage, including Secure Real Time Clock, Security State Machine, Master Key Control, and Violation/Tamper Detection and reporting. SPDIF1 Sony Philips Digital Interconnect Format A standard audio file transfer format, developed jointly by the Sony and Phillips corporations. It supports Transmitter and Receiver functionality. TEMPSENSOR Temperature Sensor Temperature sensor TZASC Trust-Zone Address Space Controller The TZASC (TZC-380 by Arm) provides security address region control functions required for intended application. It is used on the path to the DRAM controller.

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2.1 Recommended connections for unused input/output

to reduce overall board power. Table 4 shows the recommended connections for unused power supply rails.

• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none)
• Programmable baud rates up to 4 Mbps. This is a higher max baud rate relative to the 1.875 MHz, which is stated by the TIA/EIA-232-F standard.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud uSDHC1 uSDHC2 uSDHC3 SD/MMC and SDXC Enhanced Multi-Media Card / Secure Digital Host Controller i.MX 8M Mini SoC characteristics: All the MMC/SD/SDIO controller IPs are based on the uSDHC IP . They are designed to support:
• SD/SDIO standard, up to version 3.0.
• MMC standard, up to version 5.1.
• 1.8 V and 3.3 V operation, but do not support 1.2 V operation.
• 1-bit/4-bit SD and SDIO modes, 1-bit/4-bit/8-bit MMC mode. Two uSDHC controllers (uSDHC1 and uSDHC3) can support up to an 8-bit interface, the other controller (uSDHC2) can only support up to a 4-bit interface. USB1 USB2 2x USB 2.0 controllers and PHYs Two USB controllers and PHYs that support USB 2.0. Each USB instance contains:
• USB 2.0 core, which can operate in 2.0 mode VPU Video Processing Unit A high performing video processing unit (VPU), which covers many SD-level and HD-level video decoders. See the i.MX 8M Mini complete list of the VPU’s decoding and encoding capabilities. WDOG1 WDOG2 WDOG3 Watchdog The watchdog (WDOG) timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the Arm core, and a second point evokes an external event on the WDOG line. XTALOSC Crystal Oscillator interface The XTALOSC module enables connectivity to an external crystal oscillator device. In a typical application use case, it is used for a 24 MHz oscillator.

Table 4. Recommended connections for unused power supply rails

Table 5 shows recommended connections for unused signal contacts/interfaces. Table 5. Recommended connections for unused signal contacts/interfaces Table 4. Recommended connections for unused power supply rails (continued)

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Electrical characteristics

3 Electrical characteristics

This section provides the device and module-level electrical characteristics for the i.MX 8M Mini family of processors.

3.1 Chip-level conditions

This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference to the individual tables and sections.

3.1.1 Absolute maximum ratings

Stresses beyond those listed under Table 7 may affect reliability or cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the operating ranges or parameters tables is not implied. Table 6. i.MX 8M Mini chip-level conditions Table 7. Absolute maximum ratings

i.MX 8M Mini Applications Processor Datasheet for Industrial Products, Rev. 2, 11/2022 NXP Semiconductors 15 GPIO supply voltage NVCC_JTAG, NVCCGPIO1, NVCC_ENET, NVCC_SD1, NVCC_SD2, NVCC_NAND, NVCC_SA1, NVCC_SAI2, NVCC_SAI3, NVCC_SAI5, NVCC_ECSPI, NVCC_I2C, NVCC_UART, NVCC_CLK -0.3 3.8 V — GPIO pre-driver supply voltage PVCC0_1P8, PVCC1_1P8, PVCC2_1P8 -0.3 2.15 V — Isolated core supply voltage VDD_ANA_0P8 -0.3 1.15 V — Analog core supply voltage VDD_ANA0_1P8 -0.3 2.15 V — VDD_ANA1_1P8 -0.3 2.15 V — Arm PLL supply voltage VDD_ARM_PLL_0P8 -0.3 0.95 V — VDD_ARM_PLL_1P8 -0.3 2.15 V — MIPI PHY supply voltage VDD_MIPI_0P9 -0.3 1.05 V — VDD_MIPI_1P2 -0.3 1.45 V — VDD_MIPI_1P8 -0.3 2.15 V — PCIe PHY supply voltage VDD_PCIE_0P8 -0.3 0.95 V — VDD_PCIE_1P8 -0.3 2.15 V — USB PHY supply voltage VDD_USB_0P8 -0.3 0.95 V — VDD_USB_1P8 -0.3 2.15 V — VDD_USB_3P3 -0.3 3.95 V — USB_VBUS input detected USB1_VBUS, USB2_VBUS -0.3 3.95 V — XTAL supply voltage VDD_24M_XTAL_1P8 -0.3 2.15 V — Storage temperature range TSTORAGE -40 150 oC — Table 7. Absolute maximum ratings (continued)

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3.1.2 Thermal resistance

3.1.2.1 FCBGA package thermal resistance

Table 9 displays the 14 x 14 mm FCBGA package thermal resistance data. Table 8. Electrostatic discharge and latch up ratings

• Class I@ 25 oC ambient temperature
• Class II @ 105 oC ambient temperature A A JESD78E

Table 9. Thermal resistance data 2 Per SEMI G38-87 and JESD51-2 with the single layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal. top surface of the board near the package.

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3.1.3 Operating ranges

Table 10 provides the operating ranges of the i.MX 8M Mini applications processor. For details on the chip's power structure, see the “Power Management Unit (PMU)” chapter of the i.MX 8M Mini Table 10. Operating ranges1

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PVCC0_1P8, PVCC1_1P8, PVCC2_1P8 1.650 1.800 1.950 V Power supply for GPIO pre-driver VSS — — — V Ground for all core logic and I/O NVCC_DRAM 1.283 1.35 1.425 V DDR3L 1.14 1.2 1.26 V DDR4 1.06 1.1 1.17 V LPDDR4 DRAM_VREF 0.49 x NVCC_DRAM 0.5 x NVCC_DRAM 0.51 x NVCC_DRAM V Internal output, no connection is needed. should be connected to the separate logic power. VDD_ANA0_1P8 VDD_ANA1_1P8 1.71 1.8 1.89 V Analog 1.8 V core power VDD_ANA_0P8 0.780 0.820 0.900 V Isolated 0.8 V core power VDD_ARM_PLL_0P8 0.780 0.820 0.900 V Arm PLL 0.8 V power VDD_ARM_PLL_1P8 1.71 1.8 1.89 V Arm PLL 1.8 V power VDD_24M_XTAL_1P8 1.71 1.8 1.89 V XTAL 1.8 V power VDD_DRAM_PLL_1P8 1.71 1.8 1.89 V Analog 1.8 V core power VDD_MIPI_0P9 0.855 0.9 1.000 V 0.9 V power for PLL and internal logic VDD_MIPI_1P2 1.14 1.2 1.26 V 1.2 V power for analog VDD_MIPI_1P8 1.71 1.8 1.89 V 1.8 V power for PLL and analog VDD_PCI_0P85,6 0.805 0.850 0.900 V Digital supply for PCIe PHY VDD_PCI_1P85 1.71 1.8 1.89 V 1.8 V supply for PCIe PHY VDD_USB_0P8 0.780 0.820 0.900 V Digital power supply from PHY’s I/O power pads VDD_USB_1P8 1.71 1.80 1.89 V 1.8 V analog power supply VDD_USB_3P3 3.069 3.30 3.6 V 3.3 V analog power supply USB1_VBUS USB2_VBUS 1.34 — 3.60 V USB_VBUS input detect signal Temperature Sensor Accuracy7 — ±3 ±5 °C Sensing temperature range 10°C to 85°C — ±4 ±6 °C Sensing temperature range 10°C to 95°C — ±5 ±7 °C Sensing temperature range 10°C to 105°C Table 10. Operating ranges1 (continued)

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3.1.4 External clock sources

Each i.MX 8M Mini processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency (XTALI). The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real time clock operation, and slow system and watch-dog counters. The clock input can only be connected to an external oscillator. RTC_XTALO should be directly connected to VDD_SNVS_0P8. The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input can be connected to either an external oscillator or a crystal using internal oscillator amplifier. Table 11 shows the interface frequency requirements. TMU Sensing Temperature Range 10 — 125 oC — T J -40 — +105 oC See Table 2 for complete list of junction temperature capabilities. 1 The BD71847MWV PMIC does not support 0.950 V for VDD_GPU, VDD_VPU, and VDD_DRAM. For this PMIC, 0.975 V typical is acceptable and supported. 2 Applying the maximum voltage results in maximum power consumption and heat generation. A voltage set point = (Vmin + the supply tolerance) is recommended. This results in an optimized power/speed ratio. 3 Overdrive maximum voltage includes all the nominal frequencies. 4 Booting VDD_SOC at 0.800 V ±5% is acceptable (Vmin = 0.760 V). Software is expected to program the VDD_SOC voltage to the typical value in this table prior to first DRAM memory access. 5 Ensure the VDD_PCI_1P8 does not have more than 40 mVpp AC power supply noise superimposed on the high power supply voltage for the PHY core (1.8 V nominal DC value). Simultaneously, the VDD_PCI_0P8 should have no more than 20 mVpp AC power supply noise superimposed on the low power supply voltage for th PHY core (0.9 V nominal DC value for the overdrive). 6 It can be min 0.78 V when supplied but not operating PCIe. 7 “EN” of TMU Enable Register (TMU_TER) is required to be always enabled for the part to operate correctly. Table 11. External input clock frequency 1 The required frequency stability of this clock source is application dependent. 2 Recommended nominal frequency 32.768 kHz.

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Table 12 shows the external input clock for OSC32K.

3.1.5 Maximum supply currents

Power consumption is highly dependent on the application. Estimating the maximum supply currents required for power supply design is difficult because the use cases that requires maximum supply current is not a realistic use cases. To help illustrate the effect of the application on power consumption, data was collected while running consumer standard benchmarks that are designed to be compute and graphic intensive. The results provided are intended to be used as guidelines for power supply design. 3 External oscillator or a fundamental frequency crystal appropriately coupled to the internal oscillator amplifier. The typical values shown in Table 11 are required for use with NXP software to ensure precise time keeping and USB operation. For RTC_XTALI operation, an external oscillator is necessary. RTC_XTALO should be directly connected to VDD_SNVS_0P8 when using an external 32.768 kHz oscillator. NOTE There is no internal RC oscillator. Table 12. External input clock for OSC32K Table 13. Maximum supply currents

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3.1.6 Power modes

The i.MX 8M Mini processors support the following power modes:

• RUN Mode: All external power rails are on, CPU is active and running; other internal modules can be on/off based on application.
• IDLE Mode: When there is no thread running and all high-speed devices are not active, the CPU can automatically enter this mode. The CPU can be in the power-gated state but with L2 data retained, DRAM and the bus clock are reduced. Most of the internal logic is clock gated but still remains powered. The M4 core can remain running. Compared with RUN mode, all the external power rails from the PMIC remain the same, and most of the modules still remain in their state.
• SUSPEND Mode: The most efficient power saving mode where all the clocks are off and all the unnecessary power supplies are off.
• SNVS Mode: This mode is also called RTC mode. Only the power for the SNVS domain remains on to keep RTC and SNVS logic alive.
• OFF Mode: All power rails are off. NVCC_<XXX> Imax = N x C x V x (0.5 x F) Where: N—Number of IO pins supplied by the power line C—Equivalent external capacitive load V—IO voltage (0.5 x F)—Data change rate. Up to 0.5 of the clock rate (F). In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz. NVCC_DRAM DRAM_VFEF 10 mA

Table 14. Chip power in different LP mode Table 13. Maximum supply currents (continued)

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Table 15 summarizes the external power supply states in all the power modes. SUSPEND NVCC (1.8 V) 1.20 mW NVCC_DRAM (1.1 V) 0.50 NVCC_ENET (1.8 V) 0.10 NVCC_SNVS_1P8 (1.8 V) 0.10 PVCC (1.8 V) 0.60 VDD_MIPI_0P9 (0.9 V) 2.20 VDD_SNVS_0P8 (0.8 V) 0.10 VDD_SOC (0.82 V) 4.00 VDD_ARM_0P8 (0.82 V) 0.10 VDDA_PCIE_USB_0P8 (0.82 V) 3.00 Total2 11.90 1 All the power numbers defined in the table are for information only. These numbers are based on typical silicon at 25oC, under non-OS environment and use case dependent. For power numbers with OS and real use cases, see Power consumption measurement application note for more details. 2 Sum of the listed supply rails. Table 15. The power supply states Table 14. Chip power in different LP mode (continued)

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3.2 Power supplies requirements and restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations:

• Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the processor (worst-case scenario) PVCCx_1P8 OFF OFF ON ON ON NVCC_DRAM OFF OFF ON ON ON

1 See Table 16

Table 16. Group name Table 15. The power supply states (continued)

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3.2.1 Power-up sequence

Figure 6 illustrates the power-up sequence of i.MX 8M Mini processor. Figure 3. The power-up sequence

i.MX 8M Mini Applications Processor Datasheet for Industrial Products, Rev. 2, 11/2022 NXP Semiconductors 25 Table 17 represents the timing parameters of the power-up sequence.

3.2.2 Power-down sequence

Figure 6 illustrates the power-down sequence of i.MX 8M Mini processor. Table 17. Power-up sequence 1 The values of T13 depend on T2. RTC_RESET_B must be de-assert before POR_B de-asserts. t1 Uncertain period before PMIC_ON_REQ assert during VDD_SNVS_0P8 ramp up. During power-up, make sure NVCC_xxx - PVCCx_1P8 < 2 V.

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Figure 4. The power-down sequence

i.MX 8M Mini Applications Processor Datasheet for Industrial Products, Rev. 2, 11/2022 NXP Semiconductors 27 Table 18 represents the timing parameters of the power-down sequence.

3.3 PLL electrical characteristics

Table 19 shows PLL electrical characteristics. Table 18. Power-down sequence During power-down, make sure NVCC_xxx - PVCCx_1P8 < 2 V. Table 19. PLL electrical parameters

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3.4 On-chip oscillators

3.4.1 OSC24M

A 24 MHz oscillator is used as the primary clock source for the PLLs to generate the clock for the CPU, BUS, and high-speed interfaces. For fractional PLLs, the 24 MHz clock from the oscillator can be used as the PLL reference clock directly. SYS_PLL2 Clock output range 1 GHz Reference clock 24 MHz Lock time 25 s SYS_PLL3 Clock output range 600 MHz ~ 1 GHz Reference clock 24 MHz Lock time 25 s ARM_PLL Clock output range 800 MHz ~1.6 GHz Reference clock 24 MHz Lock time 25 s DRAM_PLL Clock output range Maximum 750 MHz Reference clock 24 MHz Lock time 375 s GPU_PLL Clock output range Maximum 1 GHz Reference clock 24 MHz Lock time 25 s VPU_PLL Clock output range 400 MHz ~ 800 MHz Reference clock 24 MHz Lock time 25 s Table 20. Crystal specifications1 Table 19. PLL electrical parameters (continued)

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3.4.2 OSC32K

This block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implements a low power oscillator. Figure 5. Crystal model and external components

3.5 General purpose I/O (GPIO) DC parameters

operating ranges in Table 10, unless otherwise noted. 1 Actual working drive level is depend on real design. Please contact crystal vendor for selecting drive level of crystal. Table 21. 32K crystal specifications1 given by the following formula: CL={CL1 X CL2 / (CL1 + CL2)} + PCB strays. 2 Actual working drive level is depend on real design. Please contact crystal vendor for selecting drive level of crystal. 3 ESR is the equivalent series resistance of the crystal. 4 Rf is the feedback resistor to bias the amplifier. A larger value of Rf is preferred at lower frequencies. 5 Rs is the series resistor to limit amplifier gain and reduce power dissipation in the crystal.

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3.5.1 DDR I/O DC electrical characteristics

The DDR I/O pads support LPDDR 4, DDR4, and DDR3L operational modes. The DDR Memory Controller (DDRMC) is designed to be compatible with JEDEC-compliant SDRAMs. DDRMC operation is contingent upon the board’s DDR design adherence to the DDR design and layout requirements stated in the hardware development guide for the i.MX 8M Mini applications processor. Table 22. GPIO DC parameters 1 Does not support internal pull-up or pull-down for 3.3 V IOs. Table 23. Additional leakage parameters

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3.6 I/O AC parameters

This section includes the AC parameters of the following I/O types:

• General Purpose I/O (GPIO) The GPIO load circuit and output transition time waveforms are shown in Figure 6 and Figure 7.

Figure 6. Load circuit for output Figure 7. Output transition time waveform

3.6.1 General purpose I/O AC parameters

This section presents the I/O AC parameters for GPIO in different modes. Table 24. Maximum frequency of operation for input Table 25. Maximum frequency of operation for output

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3.7 Output buffer impedance parameters

This section defines the I/O impedance parameters of the i.MX 8M Mini family of processors for the following I/O types: NOTE DDR I/O output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see Figure 8). 01X 1X 4x Fast Slew 200 100 180 90 11X 0X 6x Slow Slew 250 130 200 100 11X 1X 6x Fast Slew 250 130 200 100 Table 25. Maximum frequency of operation for output (continued)

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3.7.1 DDR I/O output buffer impedance

Table 26 shows DDR I/O output buffer impedance of i.MX 8M Mini family of processors. Note: 1. Output driver impedance is controlled across PVTs using ZQ calibration procedure. 2. Calibration is done against 240  external reference resistor. 3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.

3.8 System modules timing

This section contains the timing and electrical parameters for the modules in each i.MX 8M Mini processor.

3.8.1 Reset timings parameters

Figure 9 shows the reset timing and Table 27 lists the timing parameters. Figure 9. Reset timing diagram Table 26. DDR I/O output buffer impedance Table 27. Reset timing parameters

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3.8.2 WDOG Reset timing parameters

Figure 10 shows the WDOG reset timing and Table 28 lists the timing parameters. Figure 10. WDOGx_B timing diagram Manual (IMX8MMRM) for detailed information.

3.8.3 DDR SDRAM–specific parameters (LPDDR4 and DDR4)

bulk/decoupling capacitors and DDR trace routing between the processor and the selected DDR memory. ns-processors/i.mx-8-processors:IMX8-SERIES . Table 28. WDOGx_B timing parameters

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Processors that demonstrate full DDR performance on NXP validated designs, but do not function on customer designs, are not considered marginal parts. A report detailing how the returned part behaved on an NXP validated system will be provided to the customer as closure to a customer’s reported DDR issue. Customers bear the responsibility of properly designing the Printed Circuit Board, correctly simulating and modeling the designed DDR system, and validating the system under all expected operating conditions (temperatures, voltages) prior to releasing their product to market.

3.8.3.1 Clock/data/command/address pin allocations

These processors uses generic names for clock, data, and command address bus (DCF—DRAM controller functions); see Table 69 for details about mapping of clock, data, and command address signals of LPDDR4 and DDR4 modes.

3.9 External peripheral interface parameters

The following subsections provide information on external peripheral interfaces.

3.9.1 ECSPI timing parameters

This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing parameters for master and slave modes. Table 29. i.MX 8M Mini DRAM controller supported SDRAM configurations

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3.9.1.1 ECSPI Master mode timing

Figure 11 depicts the timing of ECSPI in master mode. Table 30 lists the ECSPI master mode timing characteristics. Figure 11. ECSPI Master mode timing diagram Table 30. ECSPI Master mode timing parameters 2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

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3.9.1.2 ECSPI Slave mode timing

Figure 12 depicts the timing of ECSPI in Slave mode. Table 31 lists the ECSPI Slave mode timing characteristics. Figure 12. ECSPI Slave mode timing diagram Table 31. ECSPI Slave mode timing parameters

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3.9.2 Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC

This section describes the electrical information of the uSDHC, which includes SD/eMMC 5.1 (single data rate) timing, eMMC 5.1/SD3.0 (dual data rate) AC timing, and SDR50/SDR104 AC timing. Figure 13 depicts the timing of SD3.0/eMMC5.1 (SDR), and Table 32 lists the SD3.0/eMMC5.1 (SDR) timing characteristics. Figure 13. SD3.0/eMMC5.1 (SDR) timing Table 32. SD3.0/eMMC5.1 (SDR) interface timing specification

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timing characteristics. Be aware that only DA TA is sampled on both edges of the clock (not applicable to CMD). Figure 14. eMMC5.1/SD3.0 (DDR) timing 1 In Low-Speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. clock frequency can be any value between 0–50 MHz. clock frequency can be any value between 0–52 MHz. 4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. Table 33. eMMC5.1/SD3.0 (DDR) interface timing specification Table 32. SD3.0/eMMC5.1 (SDR) interface timing specification (continued)

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3.9.2.3 HS400 DDR AC timing

Figure 15 depicts the timing of HS400 mode, and Table 34 lists the HS400 timing characteristics. Be aware that only data is sampled on both edges of the clock (not applicable to CMD). The CMD input/output timing for HS400 mode is the same as CMD input/output timing for SDR104 mode. Check SD5, SD6, and SD7 parameters in Table 36 SDR50/SDR104 Interface Timing Specification for CMD input/output timing for HS400 mode. Figure 15. HS400 timing Table 34. HS400 interface timing specification Table 33. eMMC5.1/SD3.0 (DDR) interface timing specification (continued)

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3.9.2.4 HS200 Mode AC timing

Figure 16 depicts the timing of HS200 mode, and Table 35 lists the HS200 timing characteristics. Figure 16. HS200 timing Table 35. HS200 interface timing specification 1 HS200 is for 8 bits while SDR104 is for 4 bits. Table 34. HS400 interface timing specification (continued)

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3.9.2.5 SDR50/SDR104 AC timing

Figure 17 depicts the timing of SDR50/SDR104, and Table 36 lists the SDR50/SDR104 timing characteristics. Figure 17. SDR50/SDR104 timing Table 22, "GPIO DC parameters," on page 30. Table 36. SDR50/SDR104 interface timing specification 1 Data window in SDR100 mode is variable.

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3.9.3 Ethernet controller (ENET) AC electrical specifications

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. Table 37. ENET signal mapping

• MAC generate output 50M reference clock for PHY, and MAC also use this 50M clock.
• MAC use external 50M clock. ENET_TD1 RMII and RGMII.TD1 RMII/RGMII ALT0 O — ENET_TD0 RMII and RGMII.TD0 RMII/RGMII ALT0 O — ENET_TX_CTL RMII.TX_EN; RGMII.TX_CTL RMII/RGMII ALT0 O — ENET_TXC RMII.TX_ERR; RGMII. TX_CLK RGMII ALT0/ALT1 O For RMII—ENET_TXC works as RMII.TX_ERR need to work in the ALT1 mode. For RGMII—ENET_TXC works as RGMII.TX_CLK need to work in the ALT0 mode. ENET_RX_CTL RMII.RX_EN (CRS_DV); RGMII.RC_CTL RMII/RGMII ALT0 I — ENET_RXC RMII.RX_ERR; RGMII.RX_CLK RGMII ALT0/ALT1 I For RMII—ENET_RXC works as RMII.RX_ERR need to work in the ALT1 mode. For RGMII—ENET_RXC works as RGMII.RX_CLK need to work in the ALT0 mode. ENET_RD0 RMII and RGMII.RD0 RMII/RGMII ALT0 I — ENET_RD1 RMII and RGMII.RD1 RMII/RGMII ALT0 I — ENET_RD2 RGMII.RD2 RGMII ALT0 I — ENET_RD3 RGMII.RD3 RGMII ALT0 I — GPIO1_IO06 enet1.MDC RMII/RGMII ALT1 O — GPIO1_IO07 enet1.MDIO RMII/RGMII ALT1 I/O — I2C1_SCL enet1.MDC RMII/RGMII ALT1 O —

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3.9.3.1 RMII mode timing

Figure 18 shows RMII mode timings. Table 38 describes the timing parameters (M16–M21) shown in the figure. I2C1_SDA enet1.MDIO RMII/RGMII ALT1 I/O — I2C2_SCL enet1.1588_EV ENT1_IN RMII/RGMII ALT1 O — I2C2_SDA enet1.1588_EV ENT1_OUT RMII/RGMII ALT1 I/O — GPIO1_IO00 ENET_PHY_RE F_CLK_ROOT RGMII ALT1 O Reference clock for PHY . GPIO1_IO08 enet1.1588_EV ENT0_IN RMII/RGMII ALT1 I Capture/compare block input/output event bus signal. When configured for capture and a rising edge is detected, the current timer value is latched and transferred into the corresponding ENET_TCCRn register for inspection by software. When configured for compare, the corresponding signal 1588_EVENT is asserted for one cycle when the timer reaches the compare value programmed in register ENET_TCCRn. An interrupt or DMA request can be triggered if the corresponding bit in ENET_TCSRn[TIE] or ENET_TSCRn[TDRE] is set. GPIO1_IO09 enet1.1588_EV ENT0_OUT RMII/RGMII ALT1 O — Table 37. ENET signal mapping (continued)

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Figure 18. RMII mode signal timing diagram

3.9.3.2 RGMII signal switching specifications

Table 38. RMII signal timing Table 39. RGMII signal switching specifications1

3 Data to clock output skew at transmitter -500 500 ps

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1 The timings assume the following configuration:

2 For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively. Table 39. RGMII signal switching specifications1 (continued)

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Figure 21. RGMII receive signal timing diagram with internal delay

3.9.4 General-purpose media interface (GPMI) timing

up to 200 MB/s I/O speed and individual chip select. separately, as described in the following subsections. Asynchronous mode. Table 40 describes the timing parameters (NF1–NF17) that are shown in the figures. Figure 22. Command Latch cycle timing diagram

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In EDO mode (Figure 25), NF16/NF17 are different from the definition in non-EDO mode (Figure 24). They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical values for them are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI samples NAND_DATAxx at the rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 8M Mini 0x8 at 50 MT/s EDO mode. But if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. Table 40. Asynchronous mode timing parameters1

1 GPMI’s Asynchronous mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP , HW_GPMI_TIMING0_DATA_SETUP , and HW_GPMI_TIMING0_DATA_HOLD. This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings. 2 AS minimum value can be 0, while DS/DH minimum value is 1. 3 T = GPMI clock period -0.075 ns (half of maximum p-p jitter). 4 NF12 is guaranteed by the design.

6 EDO mode, GPMI clock  100 MHz

(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).

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Figure 28. Source Synchronous mode data write timing diagram Figure 29. Source Synchronous mode data read timing diagram

i.MX 8M Mini Applications Processor Datasheet for Industrial Products, Rev. 2, 11/2022 NXP Semiconductors 53 Figure 30. NAND_DQS/NAND_DQ read valid window Table 41. Source Synchronous mode timing parameters1

1 GPMI’s Source Synchronous mode output timing can be controlled by the module’s internal registers

depends on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings. 2 T = tCK(GPMI clock period) –0.075 ns (half of maximum p-p jitter).

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3.9.4.3 ONFI NV-DDR2 mode (ONFI 3.2 compatible)

3.9.4.3.1 Command and address timing

ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing.

3.9.4.3.2 Read and write timing

mode AC Timing,” for details.

3.9.4.4 Toggle mode AC Timing

3.9.4.4.1 Command and address timing

Toggle mode command and address timing is the same as ONFI 1.0 compatible Asynchronous mode AC timing. See Section 3.9.4.1, Asynchronous mode AC timing (ONFI 1.0 compatible),” for details.

3.9.4.4.2 Read and write timing

Figure 31. Toggle mode data write timing

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For DDR Toggle mode, Figure 30 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI samples NAND_DATA[7:0] at both the rising and falling edges of a delayed NAND_DQS signal, which is provided by an internal DPLL. The delay value of this register can be controlled by the GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 8M Mini 0x7, which means a 1/4 clock cycle delay is expected. But if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay.

3.9.5 I 2C bus characteristics

The Inter-Integrated Circuit (I2C) provides functionality of a standard I2C master and slave. The I2C is designed to be compatible with the I2C Bus Specification, version 2.1, by Philips Semiconductor (now NXP Semiconductors).

3.9.6 MIPI D-PHY timing parameters

MIPI D-PHY electrical specifications are compliance. NF24 postamble delay tPOST POST_DELAY T + 0.43 [see note2] — ns NF28 Data write setup tDS5 0.25 tCK - 0.32 — ns NF29 Data write hold tDH5 0.25 tCK - 0.79 — ns NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ 6 — 3.18 ns NF31 NAND_DQS/NAND_DQ read hold skew tQHS 6 — 3.27 ns 1 AS minimum value can be 0, while DS/DH minimum value is 1. 2 T = tCK (GPMI clock period) -0.075 ns (half of maximum p-p jitter). 3 CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started with enough time of ALE/CLE assertion to low level.

4 PRE_DELAY+1  (AS+DS)

5 Shown in Figure 31. 6 Shown in Figure 32. Table 42. Toggle mode timing parameters (continued)

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3.9.7 PCIe PHY parameters

The PCIe interface is designed to be compatible with PCIe specification Gen2 x1 lane and supports the PCI Express 1.1/2.0 standard.

3.9.7.1 PCIE_RESREF reference resistor connection

The impedance calibration process requires connection of reference resistor 8.2 k1% precision resistor on PCIE_RESREF pads to ground. It is used for termination impedance calibration.

3.9.8 PDM timing parameters

Figure 33 illustrates the input timing of the PDM. Table 43. MIPI PHY worst power dissipation1 (at least 1 clock lane enable).

2.1 Gbps

Table 44. PCIe DC electrical characteristics

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Figure 33. PDM input timing rate and CLKDIV without I/O timing concerns.

3.9.9 Pulse width modulator (PWM) timing parameters

Figure 34 depicts the timing of the PWM, and Table 45 lists the PWM timing parameters. Figure 34. PWM timing Table 45. PWM output timing parameters

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3.9.10 FlexSPI timing parameters

Measurements are with a load of 15 pF and an input slew rate of 1 V/ns.

3.9.10.1 FlexSPI input/read timing

There are three sources for the internal sample clock for FlexSPI read data:

• Dummy read strobe generated by FlexSPI controller and looped back internally (FlexSPIn_MCR0[RXCLKSRC] = 0x0)
• Dummy read strobe generated by FlexSPI controller and looped back through the DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1)
• Read strobe provided by memory device and input from DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x3) The following sections describe input signal timing for each of these four internal sample clock sources.

3.9.10.1.1 SDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x0, 0x1

Figure 35. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1 Table 46. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0 Table 47. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1

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Timing shown is based on the memory generating read data on the SCK falling edge, and FlexSPI controller sampling read data on the falling edge.

3.9.10.1.2 SDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x3

There are two cases when the memory provides both read data and the read strobe in SDR mode:

• A1 —Memory generates both read data and read strobe on SCK rising edge (or falling edge)
• A2 —Memory generates read data on SCK falling edge and generates read strobe on SCK rising edge

Figure 36. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1) Table 48. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1) Table 49. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)

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3.9.10.1.3 DDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x0, 0x1

Figure 38. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1 Table 50. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0 Table 51. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1

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3.9.10.1.4 DDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x3

Figure 39. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3

3.9.10.2 FlexSPI output/write timing

3.9.10.2.1 SDR mode

Table 52. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case 1) Table 53. FlexSPI output timing in SDR mode

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3.9.10.2.2 DDR mode

FlexSPI SDR input timing specifications. Processor Reference Manual (IMX8MMRM) for more details. Table 54. FlexSPI output timing in DDR mode FlexSPI SDR input timing specifications. Processor Reference Manual (IMX8MMRM) for more details.

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Figure 41. FlexSPI output timing in DDR mode

3.9.11 SAI/I2S switching specifications

This section provides the AC timings for the SAI in Master (clocks driven) and Slave (clocks input) modes. (SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below. Table 55. Master mode SAI timing (50 MHz)1

1 To achieve 50 MHz for BCLK operation, below configuration must be used:

• In TX, configure BCI=0 in SAI TCR2 register and FSD=1 in SAI TCR4 register.
• In RX, configure BCI=1 in SAI TCR2 register and FSD=0 in SAI TCR4 register. Num Characteristic Min Max Unit S1 SAI_MCLK cycle time 20 — ns S2 SAI_MCLK pulse width high/low 40% 60% MCLK period S3 SAI_BCLK cycle time 20 — ns S4 SAI_BCLK pulse width high/low 40% 60% BCLK period S5 SAI_BCLK to SAI_FS output valid — 2 ns S6 SAI_BCLK to SAI_FS output invalid 0 — ns S7 SAI_BCLK to SAI_TXD valid — 2 ns S8 SAI_BCLK to SAI_TXD invalid 0 — ns S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 2 — ns S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 — ns

Table 56. Master mode SAI timing (25 MHz)

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• To achieve 50 MHz BCLK in RX, configure BCI=1 in SAI TCR2 register and FSD=0 in SAI TCR4 register. Num Characteristic Min Max Unit S11 SAI_BCLK cycle time (input) 20 — ns S12 SAI_BCLK pulse width high/low (input) 40% 60% BCLK period S13 SAI_FS input setup before SAI_BCLK 2 — ns S14 SAI_FA input hold after SAI_BCLK 2 — ns S17 SAI_RXD setup before SAI_BCLK 2 — ns S18 SAI_RXD hold after SAI_BCLK 2 — ns

Table 56. Master mode SAI timing (25 MHz) (continued)

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Figure 43. SAI Timing — Slave Modes

3.9.12 SPDIF timing parameters

encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode. Table 58. Slave mode SAI timing (25 MHz)

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3.9.13 UART I/O configuration and timing parameters

3.9.13.1 UART RS-232 I/O configuration in different modes

The i.MX 8M Mini UART interfaces can serve both as DTE or DCE device. This can be configured by the DCEDTE control bit (default 0—DCE mode). Table 60 shows the UART I/O configuration based on the enabled mode.

3.9.13.2 UART RS-232 Serial mode timing

This section describes the electrical information of the UART module in the RS-232 mode.

3.9.13.2.1 UART transmitter

Figure 46 depicts the transmit timing of UART in the RS-232 Serial mode, with 8 data bit/1 stop bit format. Table 61 lists the UART RS-232 Serial mode transmit timing characteristics. Figure 46. UART RS-232 Serial mode transmit timing diagram Table 60. UART I/O configuration vs. mode Table 61. RS-232 Serial mode transmit timing parameters 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

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3.9.13.2.2 UART receiver

Figure 47 depicts the RS-232 Serial mode receive timing with 8 data bit/1 stop bit format. Table 62 lists Serial mode receive timing characteristics. Figure 47. UART RS-232 Serial mode receive timing diagram

3.9.14 USB PHY parameters

This section describes the USB-OTG PHY parameters.

3.9.14.1 Pad/Package/Board connections

The USBx_VBUS pin cannot directly connect to the 5 V VBUS voltage on the USB2.0 link. Each USBx_VBUS pin must be isolated by an external 30 K1% precision resistor.

3.9.14.2 USB PHY worst power consumption

Table 63 shows the USB 2.0 PHY worst power dissipation. Table 62. RS-232 Serial mode receive timing parameters 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

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Table 63. USB 2.0 PHY worst power dissipation

4 Boot mode configuration

4.1 Boot mode configuration pins

sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse. Table 64. Fuses and associated pins used for boot

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4.2 Boot device interface allocation

which are configured during boot when appropriate. Table 65. Interface allocation during boot on the fuse “CS select (SPI only)“. on the fuse “CS select (SPI only)“. on the fuse “CS select (SPI only)“. 8-bit, only CS0 is supported.

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5 Package information and contact assignments

This section includes the contact assignment information and mechanical package drawing. 5.1 14 x 14 mm package information 5.1.1 14 x 14 mm, 0.5 mm pitch, ball matrix Figure 48 shows the top, bottom, and side views of the 14 × 14 mm FCBGA package.

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Figure 48. 14 X 14 MM BGA, case x package top, bottom, and side views

Table 66 shows supplies contact assignments for the 14 x 14 mm package. Table 66. i.MX 8M Mini 14 x 14 mm supplies contact assignments

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Table 67 shows an alpha-sorted list of functional contact assignments for the 14 x 14 mm package. Table 67. i.MX 8M Mini 14 x 14 mm functional contact assignments Table 66. i.MX 8M Mini 14 x 14 mm supplies contact assignments (continued)

Table 67. i.MX 8M Mini 14 x 14 mm functional contact assignments (continued)

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Table 68 shows the i.MX 8M Mini 14 x 14 mm 0.5 mm pitch ball map. deasserted, it becomes input with PD.

Table 68. 14 x 14 mm, 0.5 mm pitch ball map

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Table 68. 14 x 14 mm, 0.5 mm pitch ball map (continued)

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5.2 DDR pin function list

Table 69 shows the DDR pin function list. Table 69. DDR pin function list

Table 69. DDR pin function list (continued)

92 NXP Semiconductors

i.MX 8M Mini Applications Processor Datasheet for Industrial Products, Rev. 2, 11/2022

94 NXP Semiconductors

Revision history

6 Revision history

Table 70 provides a revision history for this data sheet. Table 70. Revision history Table 10, "Operating ranges".

• Added Note for the Figure 3, "The power-up sequence".
• Added Note for the Figure 4, "The power-down sequence".
• Updated the driver level and ESR values in the Table 20, "Crystal specifications".
• Updated Section 3.4.2, OSC32K.
• Updated Note1 for Table 55, "Master mode SAI timing (50 MHz)".
• Updated Note1 for Table 57, "Slave mode SAI timing (50 MHz)".
• Added Section 3.8.3, DDR SDRAM–specific parameters (LPDDR4 and DDR4) information.
• Replaced RGMII to RMII in ENET_TD2 Table 37, "ENET signal mapping"comments.
• Replaced ESCPI to ECSPI in NVCC_ECSPI Table 66, "i.MX 8M Mini 14 x 14 mm supplies contact assignments" remarks.
• Updated uSDHC Output Delay minimum value from 6.6 to -6.6 in Table 32, "SD3.0/eMMC5.1 (SDR) interface timing specification"
• Updated USB1_VBUS, USB2_VBUS minimum and typical value in Table 10, "Operating ranges" Rev. 1 07/2020 • Updated the eMMC descriptions in the Table 1, "Features"
• Updated numbers of SD 3.0 in the Figure 1, "i.MX 8M Mini system block diagram"
• Updated the part differentiator in the Table 2, "Orderable part numbers"
• Updated the part differentiator and Fusing in the Figure 2, "Part number nomenclature—i.MX 8M Mini family of processors"
• Updated eCSPI, SJC, and uSDHC descriptions in the Table 3, "i.MX 8M Mini modules list"
• Updated a typo for NVCC_ENET in the Table 4, "Recommended connections for unused power supply rails"
• Updated the min values and a typo in theTable 7, "Absolute maximum ratings"; removed ESD parameters from the Table 7, "Absolute maximum ratings"
• Added the Table 8, "Electrostatic discharge and latch up ratings"
• Added a footnote in the Table 10, "Operating ranges"
• Added VDD_24M_XTAL_1P8, VDD_ARM_PLL_1P8, and PVCCx_1P8 in the Table 13, "Maximum supply currents"
• Updated the Table 14, "Chip power in different LP mode"
• Updated the suspend mode state of VDD_MIPI_0P9 and VDD_MIPI_1P2 in the Table 15, "The power supply states"
• Updated the maximum values of T1, T2, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13 and minimum value of T3 in the Table 17, "Power-up sequence"
• Updated the maximum values in the Table 18, "Power-down sequence"
• Removed the USBx_ID, ONOFF, and POR_B from the Table 23, "Additional leakage parameters"
• Added GPIO1_09, I2C2_SCL, and I2C2_SDA in the Table 37, "ENET signal mapping"
• Removed 0x2 from the Section 3.9.10.1.1, SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1 and Section 3.9.10.1.3, DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
• Updated the parameters of GPIO1_IO00, GPIO1_IO01, GPIO1_IO05, GPIO1_IO09, and SAI5_MCLK in the Table 67, "i.MX 8M Mini 14 x 14 mm functional contact assignments"
• Fixed typos in the Table 68, "14 x 14 mm, 0.5 mm pitch ball map"

i.MX 8M Mini Applications Processor Datasheet for Industrial Products, Rev. 2, 11/2022 NXP Semiconductors 95 Rev. 0.2 04/2019 • Updated numbers of eMMC and FlexSPI in the Figure 1, "i.MX 8M Mini system block diagram"

• Updated the descriptions about USB and uSDHC in the Table 3, "i.MX 8M Mini modules list"
• Updated the comment of VDD_VPU and the LPDDR4 maximum value of NVCC_DRAM in the Table 10, "Operating ranges" Rev. 0.1 02/2019 • Updated the SNVS states in the Table 15, "The power supply states" Rev. 0 02/2019 • Initial version

Table 70. Revision history (continued)

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