PI90LVB16 PERICOM | Alldatasheet
Document overview
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Technical content
Features
Master/Slave clock selection in a backplane application 160 MHz operation (typical) 100ps duty cycle distortion (typical) 50ps channel to channel skew (typical) 3.3V power supply design Glitch-free power on at CLKI/O pins Low Power design (16mA @ 3.3V static) Accepts small swing (300mV typical) differential signal levels Industrial temperature operating range (40°C to +85°C) Available in 24-pin TSSOP Packaging (L) General Description PI90LVB16 is a six-channel LVTTL clock distribution driver with 50 picosecond channel-to-channel skew. It translates one BLVDS (Bus Low-Voltage Differential Signaling) input signal into six LVTTL- compatible output signals for distribution to adjacent chips on the same board. The PI90LVB16 accepts BLVDS (300mV typical) differ- ential input levels, and translates them to 3V CMOS output levels. The 160MHz PI90LVB16 can be the master clock, driving inputs of other clock I/O pins in a multipoint environment. It can also drive the BLVDS backplane with a separate channel acting as a return/ source LVTTL clock source. The master/slave clock selection of the driving source is controlled by the CrdCLK IN and the DE pins. An output enable pin OE, when high, forces all CLKOUT pins high. A backplane clock distribution network must be able to drive many transmission line stubs. The Bus LVDS feature of the PI90LVB16 is ideal for driving data transfers in large, high-performance backplane system applications. The device can be used as a source synchro- nous driver to distribute clock signals within data and telecommu- nications systems. Function Diagram 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver Delay MUX CLK OUT0 CLK OUT1 CLK OUT5 CrdCLK IN D R DE OE CLKI/0– CLKI/0+ Receive Mode Truth Table tupnI tuptuO EOE DK LCdrC NI )O/IKLC()+O/IKLC(K LC TUO HH X X H LH X D IV ≥ V70.0H LH X D IV ≤ V70.0L L = Low Logic State; H = High Logic State; X = Irrelevant Z = High Impedance tupnIt uptuO EOE DK LCdrC NI +O/IKLC O/IKLCK LC TUO LL L L H L LL H H L H HL L L H H HL H H L H HH X Z Z H Driver Mode Truth Table
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Clock Buffer/Bus Transceiver GND OE NC VCCA GNDA CLKI/0+ CLKI/0– GNDA CrdCLK IN NC DE GND VCC CLK OUT0 GND CLK OUT1 VCC CLK OUT2 GND CLK OUT3 VCC CLK OUT4 GND CLK OUT5 Connection Diagram 24-Pin L emaNniP# niPe pyTn oitpircseD +O/IKLC6 O /I. tupnikcolclaitnereffidehtfoedis)evitisoP(eurT O/IKLC7 O /I. tupnikcolclaitnereffidehtfoedis)evitageN(yratnemelpmoC EO2 I K LCllasecrofnipsiht,hgiHnehW.woLevitcasinipsiht;EO TUO ,woLnehW.hgiHnip KLC TUO O/IKLCehttaDIVroNIKLCdrCehtrehtieybdenimretedsietatscigolsnip otecivedpullupkaewasahnipsihT.nipEDehttalevelcigolehtottcepserhtiwsnip V CC KLCllaneht,gnitaolfsiEOfI. TUO .hgiHeblliwsnip ED1 1I K LCdraCehtselbanenipsiht,woLnehW.woLevitcasinipsiht;ED NI ehtotlangis KLCdnasnipO/IKLC TUO erasnipO/IKLCeht,etatS-3sirevirDehthgiHnehW. KLCehtfoetatsehtenimreteddnastupni TUO otecivedpullupkaewasahnipsihT.snip V CC .etatS-3erasnipO/IKLCllaneht,gnitaolfsiEDfI. KLC TUO 32,12,91,71,51,31O . stuptuo)SOMC(kcolcdereffuBxiS KLCdrC NI 9I .)levelLTTrolevelSOMC(draCmorfkcolctupnI V CC 42,02,61r ewoPV CC VgolanA; ACC VmorfetarapesyllanretnI( CC etarapesesuroyllanretxetcennoc, VrehtiE.deriuqergnicneuqesrewoplaicepsoN.)seilppusrewop ACC Vro CC ebnac .seilppusrewophtobylppaylsuoenatlumisro,tsrifdeilppa DNG2 2,81,41,21,1d nuorGD NG V ACC 4r ewoPV golanA ACC VmorfetarapesyllanretnI( CC rewopetarapesesuroyllanretxetcennoc, VrehtiE.deriuqergnicneuqesrewoplaicepsoN.)seilppus ACC Vro CC deilppaebnac .seilppusrewophtobylppaylsuoenatlumisro,tsrif ADNG8 ,5d nuorG .yllanretxedetcennocebtsumdnuorGmorfetarapesyllanretnI(dnuorGgolanA CN0 1,3 .stcennoCoN
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Clock Buffer/Bus Transceiver Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed (3,4) lobmySr etemaraPs noitidnoCn iP. niM. pyT. xaMs tinU V HT hgiHdlohserhTtupnI ,+O/IKLC O/IKLC 525 7 Vm V LT woLdlohserhTtupnI 075 3 RMCV egatloVedoMnommoC egnaR )5( kaep-ot-kaepVm052=DIV V DI 2/ 8.2 V DI 2/ V I NI tnerruCtupnI V NI VotVO= CC V=ED, CC V=EO, CC , Vm05–V2.1=tupnIrehtO 015 –0 1+A µ V R1HO egatloVhgiHtuptuOI ,Vm052=DIV HO Am0.1= KLC TUO V CC 2.09 .2 V V R2HO egatloVhgiHtuptuOI ,Vm052=DIV HO Am6=V CC 6.05 .2 V R1LO egatloVwoLtuptuO I LO Vm052=DIV,Am0.1= 40.01 .0 V R2LO egatloVwoLtuptuO I LO Vm052=DIV,Am6= 02 2.04 .0 I RHDO KLC TUO cimanyD tnerruCtuptuO )6( V,Vm052+=DIV TUO V= CC V1 614 24 3 Am I RLDO V,Vm052=DIV TUO V1= 415 25 .73 V HI egatloVhgiHtupnI ,EO,ED KLCdrC NI 0.2V CC V V LI egatloVwoLtupnI DNG8 .0 I HI tnerruChgiHtupnI V NI V= CC V4.2ro ED,EO 64 6 AµI LI tnerruCwoLtupnI V NI V4.0roDNG= 021 10 2+ I DRCNI tnerruCtupnI V NI VotV0= CC V=EO, CC KLCdrC NI 55 V LC pmalCegatloVtupnI I TUO Am5.1=, ED,EO KLCdrC NI 8.0V I CC ylppuSdaoLoN tnerruC ,delbanEstuptuO deilppADIVoN ,V0=ED=EO KLCdrC NI V= CC ,DNGro nepO=)–(O/IKLC KLC TUO tiucriCnepO=)5:0( V CC AmI 1CC ylppuSdaoLoN tnerruC ,delbanEstuptuO nommoCrevoDIV egnaRegatloV V=ED,DNG=EO CC , KLCdrC NI V= CC ,DNGro )V572.2MCVV521.0(Vm052=DIV KLC TUO tiucriCnepO=)5:0( I DCC ylppuSdedaoLrevirD tnerruC ,V0=EO=ED KLCdrC NI V= CC ,DNGro RL 5.73= Ω +O/IKLCneewteb KLC,O/IKLCdna TUO tiucriCnepO=)5:0( 611 2
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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver lobmySr etemaraPs noitidnoCn iP. niM. pyT. xaMs tinU V DO laitnereffiDtuptuOrevirD egatloV RL 5.73= Ω 5erugiF, V0=ED ,+O/IKLC O/IKLC 0520 530 54 Vm Δ V DO VrevirD DO edutingaM egnahC 20 2 V SO egatloVtesffOrevirD 1.1 52.15 .1V Δ V SO egatloVtesffOrevirD egnahCedutitluM 10 2V m V DHO hgiHtuptuOrevirD 4.18 .1 V V DLO woLtuptuOrevirD 8.05 0.1 I D1SO trohSlaitnereffiDrevirD tnerruCtiucriC )6( KLCdrC NI V= CC ,DNGro V0=ED,)rehtegotdetrohsstuptuo(,V0=DOV 31–7 1– Am I D2SO trohSlaitnereffiDrevirD VottnerruCtiucriC CC )6( KLCdrC NI V=+O/IKLC,V0=ED,DNG= CC 117 1 I D3SO KLCdrC NI V= CC V=O/IKLC,V0=ED, CC 017 1 I D4SO trohSlaitnereffiDrevirD DNGottnerruCtiucriC )6( KLCdrC NI V= CC +O/IKLC,V0=ED, = V0 517 1 I D5SO KLCdrC NI O/IKLC,V0=ED,DNG= = V0 517 1 I FFO egakaeLffOrewoP tnerruC V CC V,nepOroV0= DEILPPA V6.3=0 2–A µ Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed(3,4) Switching Characteristics Differential Receiver Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed (7,8) lobmySr etemaraPs noitidnoC. niM. pyT )1( .xaMs tinU t RDLHP KLC.woLothgiHyaleDnoitagaporPlaitnereffiD O/I KLCot TUO CL Fp51= Vm052=DIV 2&1serugiF 3.16 .28 .3 sn t RDHLP KLC.hgiHotwoLyaleDnoitagaporPlaitnereffiD O/I KLCot TUO 3.16 .28 .3 t R1KS noitrotsiDelcyCytuD )01( ,wekseslup LHPtHLPt 50 04 sp t R2KS egdEemaS;wekSlennahC-ot-lennahC )11( 50 8 t R3KS wekStraP-ot-traP )21( DBT sn t RHLT hgiH-ot-woLemiTnoitisnarT )9( )%08ot%02(,0 .14 .14 .2 t RLHT woL-ot-hgiHemiTnoitisnarT )9( )%02ot%08(,0 .13 .14 .2 t REOHLP KLCotEO(hgiH-ot-woLyaleDnoitagaporP TUO ) CL Fp51= 4&3serugiF 0.11 .22 .3 t REOLHP KLCotEO(woL-ot-hgiHyaleDnoitagaporP TUO )0 .11 .22 .3 f XAM ycneuqerFgnitarepOmumixaM )51( 0010 61z HM
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Clock Buffer/Bus Transceiver Switching Characteristics Differential Driver Timing Requuirements (Over supply voltage and operating temperature ranges, unless otherwise specificed (7,8) Notes: 1. Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. These ratings are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics specifies conditions of device operation. 2. ESD Rating: ESD qualification is performed per the following: HBM (1.5k Ω , 100pF), Machine Model (250V, 0Ω ), IEC 1000-4-2. All VCC pins connected together, all ground pins connected together. 3. Current into device pins are defined as positive. Current out of device pins defined as negative. All voltages are referenced to ground except VID, VOD, VTH, and VTL 4. All typicals are given for: V CC = +3.3V and TA = +25°C. 5. The VCMR range is reduced for larger VID. Example: If VID=400 mV, then VCMR is 02V to 2.2VAVID up to VCC-0V may be applied between the CLKI/O+ and CLKI/O inputs, with the Common Mode set to V CC/2. 6. Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating. 7. C L includes probe and fixture capacitance. 8. Generator waveform for all tests unless otherwise specified: f = 25 MHz, Zo = 50 Ω , tr = 1ns, tf = 1ns (10%90%). To ensure fastest propagation delay and minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns /V. In general, the faster the input edge rate, the better the AC performance, 9. All device output transition times are based on characterization measurements and are guaranteed by design. 10. tSKIR is the difference in receiver propagation delay tPLH-tPHL of one device, and is the duty cycle distortion of the output at any given temperature and VCC. The propagation delay specification is a device-to-device worst case over process, voltage and temperature. 11. tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direc tion. This parameter is guaranteed by design and characterization. 12. tSK3R part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direct ion. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distributio n. tSK3R is defined as Max-Min differential propagation delay. This parameter is guaranteed by design and characterization. 13. tSK1D is the difference in driver propagation delay tPLH-tPHLand is the duty cycle distortion of the CLKI/O outputs. 14. tSK2D part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same directio n. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t SK2D is defined as Max-Min differential propagation delay. 15. Generator input conditions: t rtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V pk-pk). Output Criteria: 60%/40% duty cycle, VOL(max) 0.4V, VOH(min) 2.7V, Load - 7pF (stray plus probes). lobmySr etemaraPs noitidnoC. niM. pyT )1( .xaMs tinU t DDLHP KLCdrC.woLothgiHyaleDnoitagaporPlaitnereffiD NI otO /IKLC CL Fp51= RL 5.73= Ω 7&6serugiF 0.15 .12 .2 sn t DDHLP KLCdrC.hgiHotwoLyaleDnoitagaporPlaitnereffiD NI otO /IKLC0 .13 .12 .2 t drCLHP KLCdrC NI KLCot TUO woLothgiHyaleDnoitagaporP CL Fp51= 9&8serugiF 0.28 .25 .4 t drCHLP KLCdrC NI KLCot TUO hgiHotwoLyaleDnoitagaporP0 .28 .25 .4 t D1KS wekSlaitnereffiD t HLP t LHP )31( CL Fp51= 7&6serugiF 006s p t D2KS wekStraP-ot-traPlaitnereffiD )41( DBT sn t DHLT emiTnoitisnarTlaitnereffiD )9( )%08ot%02(,2 .05 3.05 6.0 t DLHT emiTnoitisnarTlaitnereffiD )9( )%02ot%08(,2 .05 3.05 6.0 t DZHP O/IKLCotED.etatS-3otwoLemiTnoitisnarT V NI VotV0= CC CL Fp51= RL 5.73= Ω 11&01serugiF 6.2 t DZLP O/IKLCotED.etatS-3otwoLemiTnoitisnarT 6.2 t DHZP O/IKLCotED.hgiH-ot-etatS-3emiTnoitisnarT 3.4 t DLZP O/IKLCotED.woL-ot-etatS-3emiTnoitisnarT 6.3 f XAM ycneuqerFgnitarepOmumixaM )51( 0010 61z HM
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Figure 1. Receiver Propagation Delay and Transition Time Test Circuit Figure 2. Receiver Propagation Delay and Transition Time Waveforms
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Figure 3. Output Enable (OE) Test Circuit Figure 4. Output Enable (OE) Delay Waveforms
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Figure 6. Driver Propagation Delay Test Circuit Figure 5. Differential Driver DC Test Figure 7. Driver Propagation Delay and Transition Time Waveforms
0 Differential
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Figure 8. CrdCLK IN Propagation Delay Time Test Circuit Figure 9. CrdCLK IN Propagation Delay Time Waveforms
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Figure 10. Driver 3-State Test Circuit Figure 11. Driver 3-State Waveforms
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Clock Buffer/Bus Transceiver Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 24-Pin TSSOP (L) Package
Ordering Information
edoCgniredrOe maNegakcaPe pyTegakcaPe gnaRgnitarepO L61BVL09IP4 2LP OSSTnip-42C °58otC°04 .303 .311 .047 1.20 .002 .006 SEATING PLANE .0256 BSC .018 .030 .004 .008 .252 BSC .169 .177 X.XX X.XX DENOTES CONTROLLING DIMENSIONS IN MILLIMETERS 0.05 0.15 6.4 0.45 0.75 0.09 0.20 4.3 4.57.7 7.9 0.65 0.19 0.30 .007 .012 Max