PI90LV3486 PERICOM | Alldatasheet

Document overview

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  • PDF pages: 9

Technical content

Features

  • Signaling Rates >400Mbps (200 MHz)
  • Single 3.3V Power Supply Design
  • Accepts ±350mV (typical) Differential Swing
  • Maximum Differential Skew of 0.35ns
  • Integrated 110-Ohm termination on PI90LVTxxxx
  • Maximum Propagation Delay of 4.7ns
  • Low Voltage TTL (LVTTL) Outputs
  • Industrial Temperature Operating Range: -40°C to 85°C
  • Open, Short, and Terminated Fail Safe
  • Meets or Exceeds ANSI/TIA/EIA-644 LVDS Standard
  • Packaging (Pb-free & Green available): -16-Pin TSSOP (L ) -16-Pin SOIC (W) -8-Pin SOIC (W) -8-Pin MSOP (U) PI90LV/LVT3486 PI90LV/LVT9637 PI90LV3486/PI90LVT3486 PI90LV9637/PI90LVT9637

Description

The PI90LV/LVT3486 and PI90LV/LVT9637 are differential line receivers that use low-voltage differential signaling (LVDS) to support data rates in excess of 400 Mbps. These products are designed for applications requiring high-speed, low-power con- sumption and low noise generation. A differential input signal (350mV) is translated by the device to 3V CMOS output level.

Applications

Applications include point-to-point and multidrop baseband data transmission over controlled impedance media of approximately 100-ohms. The transmission media can be printed circuit board traces, backplanes, or cables. The PI90LV/LVT3486 and PI90LV/LVT9637, as well as companion line drivers PI90LV/LVB3487 and PI90LV/LVB9638 provide new alternatives to RS-232, PECL, and ECL devices for high-speed, point-to-point interface applications. 16-Pin W, L 8-Pin W,U

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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI90LV3486/PI90LVT3486 PI90LV9637/PI90LVT9637 LVDS High-Speed Differential Line Receivers Function Tables Pin Descriptions elbanEs tupnIlaitnereffiDt uptuO NER +NI R, –NI R TUO HV DI ≥ Vm001H HV <Vm001– DI Vm001<? HV DI ≤ Vm001–L LX Z Hn epOH PI90LV/LVT3486 PI90LV/LVT9637 stupnIlaitnereffiDt uptuO R +NI R, –NI R TUO V DI ≥ Vm001H V<Vm001– DI Vm001<? V DI ≤ Vm001–L nepOH emaNn oitpircseD R TUO sniptuptuoreviecerSOMC/LTT R +NI sniptupnireviecergnitrevni-noN R –NI sniptupnireviecergnitrevnI DNGn ipdnuorG V CC %01±V3.3+,nipylppusrewopevitisoP Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Absolute Maximum Ratings (see Note 1, Page 4) Recommended Operating Conditions .niM. pyT. xaMs tinU V(egatloVylppuS CC )0 .3+3 .3+6 .3+ V egatloVtupnIrevieceRD NG0 .3+ riAeerFgnitarepO T(erutarepmeT A) 04–5 2+5 8+C °

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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI90LV3486/PI90LVT3486 PI90LV9637/PI90LVT9637 LVDS High-Speed Differential Line Receivers lobmySr etemaraPs noitidnoCn iP. niM. pyT. xaMs tinU V HT hgiHtupnIlaitnereffiD dlohserhT V2.1+=mcV )21( R +NI , R -NI 02+0 01+ Vm V LT woLtupnIlaitnereffiD dlohserhT 001–0 2– RMCVe gatloVedoM-nommoC egnaR V DI kaep-ot-kaepVm002= )5( 1.06 .2V I NI tnerruCtupnI V NI V8.2+= V CC V0ro6.3+= 01–1 ±0 1+ AµV NI V0=0 1–1 ±0 1+ V NI V6.3+=V CC V0=0 2–0 2+ V HO egatloVhgiHtuptuOI HO V,Am4.0–= DI Vm002+= R TUO 7.20 .3 V I HO detanimrettupnI,Am4.0–= 7.20 .3 I HO detrohstupnI,Am4.0–= 7.20 .3 V LO egatloVwoLtuptuOI LO V,Am2= DI Vm002–=1 .05 2.0 I SO tnerruCtiucriCtrohStuptuOV 0=tuoV,delbanE )01( 51–8 4–0 21–A m I ZO tnerruCetatS-eerhTtuptuOV ,delbasiD TUO VroV0= CC 01–1 ±0 1+A µ V HI egatloVhgiHtupnI NE 0.2V CC V V LI egatloVwoLtupnI DNG8 .0 II tnerruCtupnIV NI VroV0= CC V=tupnIrehtO, CC DNGro0 2–1 ±0 2+A µ V LC egatloVpmalCtupnII LC Am81–=5 .1–8 .0–V I CC tnerruCylppuSdaoLoN delbanEsrevieceR V=NE CC nepOstupnI,DNGro V CC 015 1 AmnepOstupnI,V5.0roV4.2=NE0 15 1 I ZCC tnerruCylppuSdaoLoN delbasiDsrevieceR nepOstupnI,DNG=NE7 0 1 CW ecnaticapaCtupnI 50 1F p R MRET ecnadepmInoitanimreTx xxxTVL09IP0 90 113 41 Ω

Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 2)

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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI90LV3486/PI90LVT3486 PI90LV9637/PI90LVT9637 LVDS High-Speed Differential Line Receivers Switching Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 3,4,7,8) lobmySr etemaraPs noitidnoC. niM. pyT. xaMs tinU t DLHP V(woLothgiHyaleDnoitagaporPlaitnereffiD MC )V32.1= CL Fp01= V DI Vm002= )2&1serugiF( 8.17 .4 sn t DHLP V(hgiHotwoLyaleDnoitagaporPlaitnereffiD MC )V32.1=8 .17 .4 t 1DKS t|wekSesluPlaitnereffiD DLHP t- DHLP | )6( 01 .05 .0 t 2DKS ecivedemas-wekSlennahC-ot-lennahClaitnereffiD )7( 01 .05 .0 t 3DKS wekStraP-ot-traPlaitnereffiD )8( 0.1 t 4DKS wekStraP-ot-traPlaitnereffiD )9( 5.1 t HLT emiTesiR 53.02 .1 t LHT emiTllaF 53.02 .1 t ZHP ZothgiHemiTelbasiDR L k2= Ω 82 1 t ZLP ZotwoLemiTelbasiD CL Fp01= )4&3serugiF( 62 1 t HZP hgiHotZemiTelbanE 117 1 t LZP woLotZemiTelbanE 117 1 f XAM ycneuqerFgnitarepOmumixaM )31( gnihctiwsslennahcllA0 52z HM Notes: 1. “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device o peration. 2. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenc ed to ground unless otherwise specified. 3. All typicals are given for: V CC = +3.3V, TA = +25°C. 4. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z O = 50Ω, tR and tF (0% to 100%) ≤ 3ns for RIN. shorted is valid over a common-mode range of 0V to 2.3V. A V ID up tp VCC - 0V may be applied to the R IN+ / RIN- inputs with the Common-Mode voltage set to V CC/2. Propagation delay and Differential Pulse skew decrease when VID is increased from 200mV to 400mV. Skew specifications apply for 200mV ≤ VID ≤ 800mV over the common mode range. 6. tskd1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative goi ng edge of the same channel. 7. t SKD2, Channel-to-Channel Skew, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs. 8. t SKD3, Part-to-Part Skew, is the differential Channel-to-Channel skew of any event between devices. This specification applies to de vices at the same VCC,and within 5ºC of each other within the operating temperature range. 9. t SKD4, Part-to-Part Skew, is the differential Channel-to-Channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tskd4 is defined as IMax - Mini differential propagation delay. 10. Output short circuit current (I OS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. 11. C L includes probe and jig capacitance. 12. V CC is always higher than RIN+ and RIN- voltage. RIN- and RIN+ are allowed to have a voltage range -0.2V to VCC- VID/2. However, to be compliant with AC specifications, the common voltage range 0.1V to 2.3V. 13. fmax generator input conditions: t R = tF < 1ns, (0% to 100%), 50% duty cycle, differential (1.05V to1.35V peak to peak). Output Criteria: duty cycle = 60%/40%, V OL (max 0.4V), V OH (min 2.7V), Load = 10pF (stray plus probes).

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Figure 1. Receiver Propagation Delay and Transition Time Test Circuit Figure 2. Receiver Propagation Delay and Transition Time Waveforms Figure 3. Receiver Three-State Delay Test Circuit CL includes load and test jig capacitance.

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Figure 4. Receiver Three-State Delay Waveforms Figure 5. Point-to-Point Application

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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI90LV3486/PI90LVT3486 PI90LV9637/PI90LVT9637 LVDS High-Speed Differential Line Receivers Packaging Mechanical: 16-Pin TSSOP (L) .193 .201 .047 max. .002 .006 SEATING PLANE .0256 BSC .018 .030 .004 .008 .252 BSC .169 .177 X.XX X.XX DENOTES CONTROLLING DIMENSIONS IN MILLIMETERS 0.05 0.15 6.4 0.45 0.75 0.09 0.20 4.3 4.5 1.20 4.9 5.1 0.65 0.19 0.30 .007 .012 SEATING PLANE .050 BSC 0-8˚ .149 .157 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS 3.78 3.99.386 .393 9.80 10.00 1.27 .053 .068 1.35 1.75 .2284 .2440 5.80 6.20 .0040 .0098 0.10 0.25 .013 .020 .0155 .0260 0.330 0.508 0.393 0.660 .0075 .0098 0.25 0.50 .0099 .0196 x 45˚ 0.19 0.25 .016 .050 0.41 1.27REF Packaging Mechanical: 16-Pin SOIC (W)

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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI90LV3486/PI90LVT3486 PI90LV9637/PI90LVT9637 LVDS High-Speed Differential Line Receivers Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/

Ordering Information

Ordering Code Package Code Package Type PI90LV3486L L 16-pin TSSOP PI90LV3486LE L Pb-free & Green, 16-pin TSSOP PI90LV3486W W 16-pin SOIC PI90LV3486WE W Pb-free & Green, 16-pin SOIC PI90LVT3486L L 16-pin TSSOP PI90LVT3486LE L Pb-free & Green, 16-pin TSSOP PI90LVT3486W W 16-pin SOIC PI90LVT3486WE W Pb-free & Green, 16-pin SOIC PI90LV9637U U 8-pin MSOP PI90LV9637UE U Pb-free & Gr een, 8-pin MSOP PI90LV9637W W 8-pin SOIC PI90LV9637WE W Pb-free & Green, 8-pin SOIC PI90LVT9637U U 8-pin MSOP PI90LVT9637UE U Pb-free & Gr een, 8-pin MSOP PI90LVT9637W W 8-pin SOIC PI90LVT9637WE W Pb-free & Green, 8-pin SOIC