PI90LV14 PERICOM | Alldatasheet

Document overview

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Technical content

Features

  • Meets and Exceeds the Requirements of ANSI TIA/EIA-644-1995  Designed for clocking rates up to 320MHz  Operates from a single 3.3V Supply  Low Voltage Differential Signaling (LVDS) with Output Voltages of ±350mV into a 100Ω load  Choice between LVDS or TTL clock input  Synchronous Enable/Disable  Clock outputs default LOW when inputs open  Multiplexed clock input - Internal 300kΩ pullup resistor on input pins - CLK and CLK have 110Ω internal termination (PI90LVT14)  50ps Output-to-Output Skew  475ps typical propagation delay  Bus Pins are high impedance when disabled or with VCC less than 1.5V  TTL inputs are 5V Tolerant  Power Dissipation at 400Mbits/s of 150mW  Function compatible to Motorola (PECL) MC100EL14 and Micrel/Synergy (PECL) SY100EL14V  >9kV ESD Protection  20-pin TSSOP (L) and QSOP (Q) packages

Description

The PI90LV14 implements low voltage differential signaling (LVDS) to achieve clocking rates as high as 320MHz with low skew. The PI90LV14 is a low-skew 1:5 clock distribution chip which incorporates multiplexed clock inputs to allow for distribution of a lower-speed, single-ended clock or a high-speed system clock. When LOWthe SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. Because the internal flip-flop is clocked on the falling edge of the input clock, all associated specification limits are referenced to the negative edge of the clock input. The intended application of these devices and signaling technique is for high-speed clock distribution between boards. 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI90LV14/PI90LVT14 1:5 Clock Distribution niPn oitnuF KLC,KLCs tuptuOkcolClaitnereffiD KLCSt upnIkcolCLTTVL NEe lbanEsuonorhcnyS LESt upnItceleSkcolC 5-1KLC ±TUO stupnIkcolClaitnereffiD Pin Descriptions KLCK LCSL ES* NE+ TUOKLC LXL L L HXLL H XL H L L XHH L H ↓↓ XH * Z Function Table * On next negative transition of CLK, or SCLK EN CLK GND SEL GND CLK SCLK GND VCC VCC CLK5OUT– CLK5OUT+ CLK4OUT– CLK4OUT+ CLK3OUT– CLK3OUT+ CLK2OUT– CLK2OUT+ CLK1OUT– CLK1OUT+ D Q V /K31/K31/K30 Ω /K50/K49/K39/K30/K4C/K56/K54/K31/K34 /K4F/K6E/K6C/K79

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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI90LV14/PI90LVT14 1:5 Clock Distribution Notes: 1. Within-Device skew is defined for identical transitions on similar paths through a device. 2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK. 3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated with only 50mV input swings. 4. The range in which the high level of the input swing must fall while meeting the V PP spec. 5. t SKIR is the difference in receiver propagation delay (t PLH-tPHL) of one device, and is the duty cycle distortion of the output at any given temperature and V CC. The propagation delay specification is a device-to-device worst case over process, voltage, and temperature. 6. t SK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. This parameter is guaranteed by design and characterization. 7. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V peak-peak). Output Criteria: 60%/40% duty cycle, VOL (max) 0-4V, VOH (min) 2.7V, Load - 7pF (stray plus probes). 8. C L includes probe and fixture capacitance. 9. Generator waveform for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr = 1ns, tf = 1ns (35%-65%). To ensure fastest propagation delay and minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V. Switching Characteristics over Recommended Operating Conditions (unless otherwise noted)(8,9). citsiretcarahCl obmyS. niM. pyT. xaMs tinUn oitidnoC tuptuOotyaleDnoitagaporP ±TUOKLCotKLC ±TUOKLCotKLCS ±TUOKLCotLES t HLP t LHP 0.3 5.2 6.2 0.4 5.3 6.3 sn emiTelbasiD ±TUOKLCotKLCSroKLCt ZHP t ZLP t HZP t LZP 7.2 7.2 7.4 7.3 5.3 5.3 0.6 0.6 sn 2 wekStraP-ot-traP Qot)ffiD(KLC QotKLCS,)ES(KLC wekSeciveDhtiW t weks t weks t weks DBT DBT DBT sp emiTputeS xNEK LCot KLCotNEC ts ts 001 001 001– 001– emiTdloH otNEC,xNEK LCS xKLCotNEC,xNE th th 055 005 027 027 )KLC(gniwStupnImuminiM V PP 02.00 08.0 V )KLC(egnaRedoM.moC V RMC 521.05 .1V CC 02.0- 4 (semiTllaF/esiR )%08–02 S± TUOKLCotKLC ±TUOKLCotKLCS tr tf 051 051 0021 0021 sp wekSesluPnoitrotsiDelcyCytuD t( HLP t- LHP )t R1KS 0020 035 egdeemas,wekSlennahC-ot-lennahC t R2KS 070 916 ycneuqerFgnitarepOmumixaM 052z HM7

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Figure 1. Voltage and Current Definitions Figure 2. V OD Test Circuit

  1. All input pulses are supplied by a generator having the following characteristics: t r or tf ≤ 1ns, Pulse Repetition Rate

The measurement of VOC(PP) is made on test equipment with a –3dB bandwidth of at least 300MHz. Figure 3. Test Circuit & Definitions for the Driver Common-Mode Output Voltage

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Figure 4. Test Circuit, Timing, & Voltage Definitions for the Differential Output Signal

  1. All input pulses are supplied by a generator having the following characteristics: t r or tf ≤ 1ns, Pulse Repetition Rate
  2. All input pulses are supplied by a generator having the following characteristics: t

Figure 5. Enable & Disable Time Circuit & Definitions

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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI90LV14/PI90LVT14 1:5 Clock Distribution .252 .260 .047 1.20 .002 .006 SEATING PLANE.0256 BSC .018 .030 .004 .008.238 .269 .169 .177 X.XX X.XX DENOTES CONTROLLING DIMENSIONS IN MILLIMETERS 0.05 0.15 6.1 6.7 0.45 0.75 0.09 0.20 4.3 4.5 6.4 6.6 0.65 0.19 0.30 .007 .012 Max .337 .344 .053 .069 .004 .010 SEATING PLANE .025 BSC .007 .010.228 .244 .150 .1571 .016 .050 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS 0.635 8.56 8.74 1.35 1.75 5.79 6.19 0.41 1.27 0.101 0.254 .008 .012 0.203 0.305 3.81 3.99 0.178 0.254 .058 1.47 .015 x 45˚ 0.38REF Detail A Detail A .008 0.20 MIN. Guage Plane .010 0.254 .041 1.04 REF .016 .035 0.41 0.89 0˚-6˚ .008 .013 0.20 0.33 edoCgniredrOe pyTegakcaPe gnaRgniredrO L41VL09IP POSSTlim-371niP-02 C°58otC°04– L41TVL09IP Q41VL09IP POSQlim-051niP-02 Q41TVL09IP

Ordering Information

20-Pin QSOP (Q) Package 20-Pin TSSOP (L) Package Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131  1-800-435-2336  Fax (408) 435-1100  http://www.pericom.com