PI74FCT162511 PERICOM | Alldatasheet

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1 PS2080A 01/15/95

LATCHED TRANSCEIVER WITH PARITY 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 Simplified Logic Block Diagram 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI74FCT16511T PI74FCT162511T Fast CMOS 16-Bit Registered/Latched Transceiver With Parity Product Features: Common Features:

  • PI74FCT16511 and PI74FCT162511 are high-speed, low power devices with high current drive.
  • Vcc = 5V ±10%
  • Typical tsk(o) (Output Skew) < 250 ps, clocked mode
  • Extended range of –40°C to +85°C
  • Hysteresis on all inputs
  • Packages available: – 56-pin 240 mil wide TSSOP (A) – 56-pin 300 mil wide SSOP (V) PI74FCT16511T Features:
  • High output drive: I OH = –32 mA; IOL = 64 mA
  • Power off disable outputs permit “live insertion”
  • Typical V OLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C PI74FCT162511T Features:
  • High output drive: I OL /IOH = 24 mA
  • Open drain parity error allows wire-OR
  • Typical V OLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C
  • Balanced output drivers: ±24 mA
  • Series current limiting resistors Product Description: Pericom Semiconductor’s PI74FCT series of logic circuits are pro- duced in the Company’s advanced 0.8 micron CMOS technology, achieving industry leading speed grades. The PI74FCT16511T and PI74FCT162511T are high-speed, low- power 16-bit registered/latched transceiver with parity which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched or clocked modes. It has a parity generator/ checker in the A-to-B direction and a parity checker in the B-to-A direction. Error checking is done at the byte level with separate parity bits for each byte. One error flag for each direction (A-to-B or B-to-A) exists to indicate an error for either byte in either direction. The parity error flags which are open drain outputs, can be tied together and/or tied with flags from other devices to form a single error flag or interrupt. To disable the error flag during combinational transitions, a designer can disable the parity error flag by the OExx control pins. The operation in A-to-B direction is controlled by LEAB, CLKAB and OEAB control pins, and the operation in B-to-A direction is controlled by LEBA, CLKBA and OEBA control pins. GEN/CHK is used to select the operation of A-to-B direction, while B-to-A direction is always in checking mode. The ODD/EVEN select is common between the two directions. Independent operation can be achieved between the two directions by using the corresponding control lines except for the ODD/EVEN control. Latch/ RegisterByte Parity Generator/ Checker Latch/ Register Byte Parity Checking Parity Data Parity, data Parity, data Parity, data OEAB B0-15 PB1,2 PERB (Open Drain) LEBA CLKBA LEAB CLKAB GEN/CHK A0-15 PA1,2 ODD/EVEN OEBA PERA (Open Drain)

2 PS2080A 01/15/95

LATCHED TRANSCEIVER WITH PARITY 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 Logic Block Diagram B8-B15 PB1 PERB PB2 ODD/EVEN OEAB LEBA CLKBA CLKAB LEAB A0-A7 OEBA A8-A15 (Open Drain) B0-B7 PA1 PA2 GEN/CHK PERA (Open Drain) P O I C D C D C D C D C D C D C D C D C D C D C D C D C D C D C D C D C D C D C D C D P O I P P

3 PS2080A 01/15/95

LATCHED TRANSCEIVER WITH PARITY 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 Product Pin Description Pin Name Description OEAB A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) CLKAB A-to-B Clock Input CLKBA B-to-A Clock Input LEAB A-to-B Latch Enable Input LEBA B-to-A Latch Enable Input PERA Parity Error (Open Drain) on A Outputs PERB Parity Error (Open Drain) on B Outputs Ax A-to-B Data Inputs or B-to-A 3-State Outputs Bx B-to-A Data Inputs or B-to-A 3-State Outputs ODD/EVEN (1) Parity Mode Selection Input GEN/CHK (1) A-to-B Port Generate or Check Mode Input PAx (2) A-to-B Parity Input, B-to-A Parity Output PBx B-to-A Parity Input, A-to-B Parity Output GND Ground V CC Power NOTES: 1. ODD/EVEN and GEN/CHK should be tied to VCC or GND with no resistor for optimum results. 2. The PAx pin input is internally disabled during parity generation. This means that when generating parity in the A-to-B direction, there is no need to add a pull-up resistor to guarantee state. The pin will still function properly as the parity output for the B-to-A direction. Product Pin Configuration Capacitance (TA = 25°C, f = 1 MHz) Parameters(1) Description Test Conditions Typ Max. Units C IN Input Capacitance V IN = 0V 4.5 6.0 pF C I/O I/O Capacitance V OUT = 0V 5.5 8.0 pF C O Open Drain Capacitance V OUT = 0V 4.5 6.0 pF Note: 1. This parameter is determined by device characterization but is not production tested. OEAB LEAB PA 1 GND VCC GND PERA A10 A11 A12 A13 VCC A14 A15 GND PA 2 OEBA LEBA GENCHK CLKAB PB GND B VCC B PERB GND B B10 B11 B12 B13 VCC B14 B15 GND PB CLKBA ODD/EVEN 56-PIN V56 A56

4 PS2080A 01/15/95

LATCHED TRANSCEIVER WITH PARITY 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 Truth Table(1,2) Output Inputs Buffers OEAB LEAB CLKAB A X BX HX X X Z LH X L L LH X H H LL › LL LL › HH LLL X B (3) LL H X B (4) NOTES: 1. H = High Voltage Level L = Low Voltage Level X = Don't Care or Irrelevant Z = High Impedance › = LOW-to-HIGH Transition 2. A-to-B data flow is shown. B-to-A flow control is the same, except using OEBA, LEBA, and CLKBA. 3. Output level before the indicated steady-state input conditions were established. 4. Output level before the indicated steady-state input conditions were established, assuming CLKAB was HIGH before LEAB went LOW. Truth Table (Parity Generation) (1, 2, 3, 4, 5) A 0 - A7, Total Number of Inputs that are high ODD/EVEN PB 1 1, 3, 5 or 7 L H 1, 3, 5 or 7 H L 0, 2, 4, 6 or 8 L L 0, 2, 4, 6 or 8 H H NOTES: 1. Conditions shown are for GEN/CHK = L, OEAB = L, OEBA = H. 2. A-to-B parity generation is shown. B-to-A can check parity while A-to-B is performing generation. B-to-A will not generate parity. 3. The response shown is for LEAB = H. If LEAB = L, then CLKAB will control as an edge triggered clock. 4. Conditions shown are for the byte A0-A7. The byte A8-A15 is similar but will output the parity on PB 5. The error flag PERB will remain in a high state during parity generation. Truth Table (Parity Checking) (1, 2, 3, 4) A 0 - A7 and PA1(5), Total Number of Inputs that are high ODD/EVEN PERB 1, 3, 5, 7 or 9 L L 1, 3, 5, 7 or 9 H H (6) 0, 2, 4, 6 or 8 L H (6) 0, 2, 4, 6 or 8 H L NOTES: 1. Conditions shown are for GEN/CHK = H, OEAB = L, OEBA = H. 2. A-to-B parity checking is shown. B-to-A parity checking is same but uses OEBA = L, OEAB = H and errors will be indicated on PERA. 3. In parity checking mode the parity bits will be transmitted unchanged along with the corresponding data regardless of parity errors. (PB 1 = PA1) 4. The response shown is for LEAB = H. If LEAB = L, then CLKAB will control as an edge triggered clock. 5. Conditions shown are for the byte A0-A7 and PA 1. The byte A8-A15 and PA2 is same. 6. The parity error flag PERB is a combined flag for both bytes A0-A7 and A8-A15. If a parity error occurs on either byte PERB will go low.

5 PS2080A 01/15/95

LATCHED TRANSCEIVER WITH PARITY 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameters Description Test Conditions (1) Min. Typ (2) Max. Units V IH Input HIGH Voltage Guaranteed Logic HIGH Level 2.0 V V IL Input LOW Voltage Guaranteed Logic LOW Level 0.8 V IIH Input HIGH Current (Input pins) VCC = Max. V IN = VCC 1µ A (I/O pins) –1 IIL Input LOW Current (Input pins) VCC = Max. V IN = GND 1 µA (I/O pins) –1 IOZH High Impedance V CC = Max. V OUT = 2.7V 1 µA IOZL Output Current V OUT = 0.5V –1 µA V IK Clamp Diode Voltage V CC = Min., IIN = –18 mA –0.7 –1.2 V IOS Short Circuit Current (I/O pins) VCC = Max.(3), VOUT = GND –80 –140 –225 mA IO Output Drive Current (I/O pins) VCC = Max.(3), VOUT = 2.5V –50 –180 mA IOFF Output Leakage Current V CC = Max., VOUT = 4.5V ±100 µA (Open Drain) V H Input Hysteresis 100 mV PI74FCT16511T Output Drive Characteristics (Over the Operating Range) Parameters Description Test Conditions (1) Min. Typ (2) Max. Units V OH Output HIGH Voltage V CC = Min., VIN = VIH or VIL IOH = –3.0 mA 2.5 3.5 V IOH = –15.0 mA 2.4 3.5 IOH = –32.0 mA 2.0 3.0 V OL Output LOW Voltage V CC = Min., VIN = VIH or VIL IOL = 64 mA 0.2 0.55 V IOFF Power Down Disable V CC = 0V, VIN or VOUT £4.5V — — ±100 µA PI74FCT162511T Output Drive Characteristics (Over the Operating Range) Parameters Description Test Conditions (1) Min. Typ (2) Max. Units V OH Output HIGH Voltage VCC = Min., VIN = VIH or VIL IOH = –24.0 mA 2.4 3.3 V V OL Output LOW Voltage V CC = Min., VIN = VIH or VIL IOL = 24 mA 0.3 0.55 V IODL Output LOW Current V CC = 5V, VIN = VIH OR VIL, VOUT = 1.5V(3) 60 115 150 mA IODH Output HIGH Current VCC = 5V, VIN = VIH OR VIL, VOUT = 1.5V(3) –60 –115 –150 mA Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

6 PS2080A 01/15/95

LATCHED TRANSCEIVER WITH PARITY 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 Power Supply Characteristics Parameters Description Test Conditions (1) Min. Typ (2) Max. Units ICCL , ICCH , Quiescent Power V CC = Max. V IN = GND or VCC 0.1 500 µA ICCZ Supply Current DICC Supply Current per V CC = Max. V IN = 3.4V(3) 0.5 1.5 mA Input @ TTL HIGH ICCD Supply Current per V CC = Max., Outputs Open VIN = VCC 75 120 µA/ Input per MHz(4) OEAB = GND V IN = GND MHz OEBA = V CC One Bit Toggling 50% Duty Cycle IC Total Power Supply V CC = Max., V IN = VCC 0.8 1.7 (5) mA Current(6) Outputs Open V IN = GND fCP = 10 MHZ (CLKAB) 50% Duty Cycle LEAB = OEAB = GND V OEBA = V CC V IN = GND fI = 5 MHZ One Bit Toggling V CC = Max., V IN = VCC 3.8 6.5 (5) Outputs Open V IN = GND fCP = 10 MHZ (CLKAB) 50% Duty Cycle LEAB = OEAB = GND V IN = 3.4V 9.0 21.8 (5) OEBA = V CC V IN = GND fI = 2.5 MHZ

18 Bits Toggling

Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested. 6. IC =IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + DICC DH N T + ICCD (fCP /2 + FIN I) ICC = Quiescent Current DICC = Power Supply Current for a TTL High Input (VIN = 3.4V) D H = Duty Cycle for TTL Inputs High N T = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fI = Input Frequency N I = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz.

7 PS2080A 01/15/95

LATCHED TRANSCEIVER WITH PARITY 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 16511T/162511T Switching Characteristics over Operating Range (Propagation Delays) 16511/162511T 162511AT Com. Com. Parameters Description Conditions (1) Min Max Min Max Unit tPLH Propagation Delay C L = 50 pF 1.5 6.5 1.5 5.7 ns tPHL PAx to PBx R L = 500W tPLH Propagation Delay 1.5 6.5 1.5 5.0 ns tPHL Ax to Bx or Bx to Ax, PBx to PAx tPLH Propagation Delay 1.5 9.0 1.5 7.5 ns tPHL Ax to PBx tPLH (3) Propagation Delay 1.5 10.5 1.5 9.0 ns tPHL Ax to PERB, PAx to PERB 1.5 9.5 1.5 8.0 tPLH (3) Propagation Delay 1.5 10.5 1.5 9.0 ns tPHL Bx to PERA, PBx to PERA 1.5 9.5 1.5 8.0 tPLH Propagation Delay 1.5 6.0 1.5 5.6 ns tPHL LEBA to Ax and PAx LEAB to Bx and PBx t PLH (3) Propagation Delay 1.5 7.5 1.5 7.0 ns tPHL LEBA to PERA, LEAB to PERB 1.5 6.5 1.5 6.0 tPLH Propagation Delay 1.5 6.0 1.5 5.6 ns tPHL CLKBA to Ax and PAx CLKAB to Bx and PBx t PLH (3) Propagation Delay 1.5 7.5 1.5 7.0 ns tPHL CLKBA to PERA 1.5 6.5 1.5 6.0 CLKAB to PERB t PZH Output Enable Time 1.5 7.0 1.5 6.0 ns tPZL OEBA to Ax and PAx OEAB to Bx and PBx t PHZ Output Disable Time(4) 1.5 7.0 1.5 5.6 ns tPLZ OEBA to Ax and PAx OEAB to Bx and PBx t PLZ (3) Parity ERROR Enable 1.5 6.0 1.5 6.0 ns tPZL OEBA to PERA, OEAB to PERB 1.5 6.0 1.5 6.0 tPLH ODD/EVEN to PERB 1.5 10.0 1.5 10.0 ns tPHL 1.5 10.0 1.5 10.0 tPLH ODD/EVEN to PBx 1.5 10.0 1.5 10.0 ns tPHL Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. On Open Drain Outputs tPLH is measured up to VOUT = VOL + 0.3V. 4. This parameter is guaranteed but not production tested.

8 PS2080A 01/15/95

LATCHED TRANSCEIVER WITH PARITY 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI74FCT16511T/162511T Switching Characteristics over Operating Range (Setup Times) 16511/162511T 162511AT Com. Com. Parameters Description Conditions(1,3) Min. Max. Min. Max. Unit tSU Setup Time GEN/CHK LOW PBx valid 6.5 — 4 — ns HIGH or LOW PBx not valid 3 — 3 — ns Ax to CLKAB GEN/CHK HIGH PERB valid 6.5 — 4 — ns PERB not valid 3 — 3 — ns tSU Setup Time GEN/CHK HIGH PERB valid 6.5 — 4 — ns PAx to CLKAB PERB not valid 3 — 3 — ns tSU Setup Time PERA valid 6.5 — 4 — ns Bx to CLKBA PERA not valid 3 — 3 — ns PBx to CLKBA tSU Setup Time CLKAB LOW PBx valid 6.5 — 3.5 — ns Ax to LEAB GEN/CHK LOW PBx not valid 3 — 3 — ns CLKAB LOW PERB valid 6.5 — 3.5 — ns GEN/CHK HIGH PERB not valid 3 — 3 — ns CLKAB HIGH PBx valid 6.5 — 3.5 — ns GEN/CHK LOW PBx not valid 3 — 3 — ns CLKAB HIGH PERB valid 6.5 — 3.5 — ns GEN/CHK HIGH PERB not valid 3 — 3 — ns tSU Setup Time CLKAB LOW PERB valid 6.5 — 3.5 — ns PAx to LEAB GEN/CHK HIGH PERB not valid 3 — 3 — ns CLKAB HIGH PERB valid 6.5 — 3.5 — ns GEN/CHK HIGH PERB not valid 3 — 3 — ns tSU Setup Time CLKBA LOW PERA valid 6.5 — 3.5 — ns Bx to LEBA PERA not valid 3 — 3 — ns PBx to LEBA CLKAB HIGH PERA valid 6.5 — 3.5 — ns PERA not valid 3 — 3 — ns PI74FCT16511T/162511T Switching Characteristics over Operating Range (Hold Times) 16511/162511T16511/162511AT Com. Com. Parameters Description Conditions (1) Min. Max. Min. Max. Unit tH Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA 1 — 1 — ns tH Hold Time HIGH or LOW PAx to LEAB 1 — 1 — ns tH Hold Time HIGH or LOW PBx to LEBA 1 — 1 — ns tH Hold Time Ax to CLKAB, PAx to CLKAB 1 — 1 — ns tH Hold Time Bx to CLKBA, PBx to CLKBA 1 — 1 — ns tW LEAB or LEBA Pulse Width HIGH (2) 3—3— n s tW CLKAB or CLKBA Pulse Width HIGH or LOW (2) 3—3— n s Notes: 1. See test circuit and wave forms. 2. This parameter is guaranteed but not production tested. 3. “Not valid” means the setup time indicated is not sufficient to assure proper functioning of this output; however, the set-up time indicated will assure proper functioning of the A-to-B or B-to-A port respective to the indicated direction. Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com C L = 50 pF R L = 500W C L = 50 pF R L = 500W