PI74ALVCH16501 PERICOM | Alldatasheet

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Technical content

1 PS8133A 01/31/00

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI74ALVCH16501 18-Bit Universal Bus Transceiver With 3-State Outputs Logic Block Diagram Product Description Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed. The 18-bit PI74ALVCH16501 univeral bus transceiver is designed for 2.3V to 3.6V V CC operation. Data flow in each direction is controlled by Output Enable (OEAB and OEBA), Latched Enable (LEAB and LEBA), and CLOCK (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is LOW, the A-bus is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high- impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The Output Enables are complementary (OEAB is active HIGH and OEBA is active LOW). To ensure the high-impedance state during power up or power down, OEBA should be tied to V CC through a pull-up resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Product Features

  • PI74ALVCH16501 is designed for low voltage operation
  • V CC = 2.3V to 3.6V
  • Hysteresis on all inputs
  • Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V , TA = 25°C
  • Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V , TA = 25°C
  • Bus Hold retains last active bus state during 3-STATE eliminating the need for external pullup resistors
  • Industrial operation at –40°C to +85°C
  • Packages available: – 48-pin 240 mil wide plastic TSSOP (A) – 48-pin 300 mil wide plastic SSOP (V)

18-BIT UNIVERSAL BUS TRANSCEIVER

2 PS8133A 01/31/00

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 Pin Name Description O E Output Enable Input (Active HIGH) L E Latch Enable (Active HIGH) CLK Clock Input (Active HIGH) Ax Data I/O B x Data I/O GND Ground V CC Power Product Pin Description Truth Table(1)† Notes: 1. H = High Signal Level L = Low Signal Level Z = High Impedance ↑ = LOW-to-HIGH Transition † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA. ‡ Output level before the indicated steady-state input conditions were established, provided that CLKAB is HIGH before LEAB goes LOW. § Output level before the indicated steady-state input conditions were established. Product Pin Configuration 56-PIN V-56 A-56 OEAB LEAB GND VCC GND A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA GND CLKAB GND VCC GND B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND stupnI BtuptuO BAEOB AELB AKLCA LX X X Z HH X L L HH X H H HL ↑ LL HL ↑ HH HL H X B 0 ‡ HL L X §0B

18-BIT UNIVERSAL BUS TRANSCEIVER

3 PS8133A 01/31/00

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. sretemaraPn oitpircseDs noitidnoCtseT. niM. pyT. xaMs tinU V CC egatloVylppuS3 .26 .3 V V HI egatloVHGIHtupnI V CC V7.2otV3.2=7 .1 V CC V6.3otV7.2=0 .2 V LI egatloVWOLtupnI V CC V7.2otV3.2=7 .0 V CC V6.3otV7.2=8 .0 V NI egatloVtupnI0 V CC V TUO egatloVtuptuO0 V CC I HO tnerruCtuptuOlevel-hgiH V CC V3.2=2 1- Am V CC V7.2=2 1- V CC V0.3=4 2- I LO tnerruCtuptuOlevel-woL V CC V3.2=2 1 V CC V7.2=2 1 V CC V0.3=4 2 TA erutarepmeTriA-eerFgnitarepO0 4-5 8C ° Recommended Operating Conditions(1) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.)

18-BIT UNIVERSAL BUS TRANSCEIVER

4 PS8133A 01/31/00

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 sretemaraPs noitidnoCtseTV CC )1( .niM. pyT )2( .xaMs tinU V HO I HO 001-= µA. xaMot.niMV CC -2.0 V I HO AM6-=V HI =V 7.1V 3.20 .2 I HO 21-=m A V HI =V 7.1V 3.27 .1 V HI =V 0.27 .2V 2 .2 V HI =V 0.2V 0.34 .2 I HO 42-=m A V HI V0.2=V 0.30 .2 V LO I LO 001= µA. xaMot.niM2 .0 I LO =A m6V LI =V 7.0V 3.24 .0 I LO 21=m A V LI =V 7.0V 3.27 .0 V LI =V 8.0V 7.24 .0 I LO =A m42V LI =V 8.0V 0.35 5.0 II V I =V CC DNGroV 6.35 ± µA II )dloH( )3( V I =V 7.0 V3.2 V I =V 7.15 4- V I =V 8.0 V0.3 V I =V 0.25 7- V I =V 6.3ot0V 6.30 05± I ZO )4( V O =V CC DNGroV 6.30 1± I CC V I =V CC DNGroI O 0=V 6.30 4 ∆I CC VtatupnienO CC VtastupnirehtO,V6.0- CC DNGroV 6.3otV30 57 C I stupnIlortnoCV I =V CC DNGroV 3.34 F p C OI stropBroAV O =V CC DNGroV 3.38 F p Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading. 3. Bus Hold maximum dynamic current required to switch the input from one state to another. 4. For I/O ports, the I OZ includes the input leakage current.

18-BIT UNIVERSAL BUS TRANSCEIVER

5 PS8133A 01/31/00

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 Timing Requirements over Operating Range Switching Characteristics Over Operating Range(1) Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131  1-800-435-2336  Fax (408) 435-1100  http://www.pericom.com sretemaraP morF )tupnI( oT stinU f XAM C L Fp05= RL 005= Ω 0510 510 51z HM t DP BroAA roB2 .14 .55 .419 .3 sn Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. stinU f KCOLC ycneuqerfkcolC C L Fp05= R L 005= Ω 00 510 0 510 0 51z HM tW esluP noitaruD hgihEL3 .33 .33 .3 sn wolrohgihKLC3 .33 .33 .3 t US puteS emit KLCerofebataD ↑ 2.21 .27 .1 ELerofebataD ↓ hgihKLC,9 .16 .15 .1 ELerofebataD ↓ wolKLC,3 .11 .10 .1 tH dloH emit KLCretfaataD ↑ 6.06 .07 .0 ELretfaataD ↓ wolrohgihKLC4 .17 .14 .1 ∆ /t∆v )2( llaFroesiRnoitisnarTtupnI0 0 10 0 10 0 1V /sn Notes: 1. See test circuit and waveforms. 2. Unused control inputs must be held HIGH or LOW to prevent them from floating. Operating Characteristics, TA = 25ºC retemaraPs noitidnoCtseT V CC V2.0±V5.2=V CC V3.0±V3.3= stinU lacipyT C DP noitapissiDrewoP ecnaticapaC delbanEstuptuO C L zHM01=f,Fp05= 444 5 Fp delbasiDstuptuO6 6